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authorMichael Krufky <mkrufky@kernellabs.com>2010-03-11 22:32:27 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-08-02 13:46:42 -0400
commitd99a21182246bb9c876c0f48ef1201e8df97535a (patch)
treef4e07e56ee99b3590f82ab705385c9e2359caceb /drivers/media/dvb/frontends
parent241b0f411193ebcfa86aa41a5ab4f22df2ef4c24 (diff)
V4L/DVB: lgdt3305: consolidate init functions
Signed-off-by: Michael Krufky <mkrufky@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends')
-rw-r--r--drivers/media/dvb/frontends/lgdt3305.c165
1 files changed, 67 insertions, 98 deletions
diff --git a/drivers/media/dvb/frontends/lgdt3305.c b/drivers/media/dvb/frontends/lgdt3305.c
index 910cd785081d..de313b13c9e2 100644
--- a/drivers/media/dvb/frontends/lgdt3305.c
+++ b/drivers/media/dvb/frontends/lgdt3305.c
@@ -587,115 +587,84 @@ static int lgdt3305_sleep(struct dvb_frontend *fe)
587 return 0; 587 return 0;
588} 588}
589 589
590static int lgdt3304_init(struct dvb_frontend *fe) 590static int lgdt3305_init(struct dvb_frontend *fe)
591{ 591{
592 struct lgdt3305_state *state = fe->demodulator_priv; 592 struct lgdt3305_state *state = fe->demodulator_priv;
593 int ret; 593 int ret;
594 594
595 static struct lgdt3305_reg lgdt3304_init_data[] = { 595 static struct lgdt3305_reg lgdt3304_init_data[] = {
596 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, 596 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
597 { .reg = 0x000d, .val = 0x02, }, 597 { .reg = 0x000d, .val = 0x02, },
598 { .reg = 0x000e, .val = 0x02, }, 598 { .reg = 0x000e, .val = 0x02, },
599 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, 599 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
600 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, 600 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
601 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, 601 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
602 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, 602 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
603 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, 603 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
604 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, 604 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
605 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, }, 605 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, },
606 { .reg = 0x0112, .val = 0x17, }, 606 { .reg = 0x0112, .val = 0x17, },
607 { .reg = 0x0113, .val = 0x15, }, 607 { .reg = 0x0113, .val = 0x15, },
608 { .reg = 0x0114, .val = 0x18, }, 608 { .reg = 0x0114, .val = 0x18, },
609 { .reg = 0x0115, .val = 0xff, }, 609 { .reg = 0x0115, .val = 0xff, },
610 { .reg = 0x0116, .val = 0x3c, }, 610 { .reg = 0x0116, .val = 0x3c, },
611 { .reg = 0x0214, .val = 0x67, }, 611 { .reg = 0x0214, .val = 0x67, },
612 { .reg = 0x0424, .val = 0x8d, }, 612 { .reg = 0x0424, .val = 0x8d, },
613 { .reg = 0x0427, .val = 0x12, }, 613 { .reg = 0x0427, .val = 0x12, },
614 { .reg = 0x0428, .val = 0x4f, }, 614 { .reg = 0x0428, .val = 0x4f, },
615 { .reg = LGDT3305_IFBW_1, .val = 0x80, }, 615 { .reg = LGDT3305_IFBW_1, .val = 0x80, },
616 { .reg = LGDT3305_IFBW_2, .val = 0x00, }, 616 { .reg = LGDT3305_IFBW_2, .val = 0x00, },
617 { .reg = 0x030a, .val = 0x08, }, 617 { .reg = 0x030a, .val = 0x08, },
618 { .reg = 0x030b, .val = 0x9b, }, 618 { .reg = 0x030b, .val = 0x9b, },
619 { .reg = 0x030d, .val = 0x00, }, 619 { .reg = 0x030d, .val = 0x00, },
620 { .reg = 0x030e, .val = 0x1c, }, 620 { .reg = 0x030e, .val = 0x1c, },
621 { .reg = 0x0314, .val = 0xe1, }, 621 { .reg = 0x0314, .val = 0xe1, },
622 { .reg = 0x000d, .val = 0x82, }, 622 { .reg = 0x000d, .val = 0x82, },
623 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, 623 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
624 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, 624 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
625 }; 625 };
626 626
627 lg_dbg("\n");
628
629 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
630 ARRAY_SIZE(lgdt3304_init_data));
631 if (lg_fail(ret))
632 goto fail;
633
634 ret = lgdt3305_soft_reset(state);
635fail:
636 return ret;
637}
638
639static int lgdt3305_init(struct dvb_frontend *fe)
640{
641 struct lgdt3305_state *state = fe->demodulator_priv;
642 int ret;
643
644 static struct lgdt3305_reg lgdt3305_init_data[] = { 627 static struct lgdt3305_reg lgdt3305_init_data[] = {
645 { .reg = LGDT3305_GEN_CTRL_1, 628 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
646 .val = 0x03, }, 629 { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, },
647 { .reg = LGDT3305_GEN_CTRL_2, 630 { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, },
648 .val = 0xb0, }, 631 { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, },
649 { .reg = LGDT3305_GEN_CTRL_3, 632 { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, },
650 .val = 0x01, }, 633 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
651 { .reg = LGDT3305_GEN_CONTROL, 634 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
652 .val = 0x6f, }, 635 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
653 { .reg = LGDT3305_GEN_CTRL_4, 636 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
654 .val = 0x03, }, 637 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
655 { .reg = LGDT3305_DGTL_AGC_REF_1, 638 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
656 .val = 0x32, }, 639 { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, },
657 { .reg = LGDT3305_DGTL_AGC_REF_2, 640 { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, },
658 .val = 0xc4, }, 641 { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, },
659 { .reg = LGDT3305_CR_CTR_FREQ_1, 642 { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, },
660 .val = 0x00, }, 643 { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, },
661 { .reg = LGDT3305_CR_CTR_FREQ_2, 644 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
662 .val = 0x00, }, 645 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
663 { .reg = LGDT3305_CR_CTR_FREQ_3, 646 { .reg = LGDT3305_IFBW_1, .val = 0x80, },
664 .val = 0x00, }, 647 { .reg = LGDT3305_IFBW_2, .val = 0x00, },
665 { .reg = LGDT3305_CR_CTR_FREQ_4, 648 { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, },
666 .val = 0x00, }, 649 { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, },
667 { .reg = LGDT3305_CR_CTRL_7, 650 { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, },
668 .val = 0x79, }, 651 { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, },
669 { .reg = LGDT3305_AGC_POWER_REF_1,
670 .val = 0x32, },
671 { .reg = LGDT3305_AGC_POWER_REF_2,
672 .val = 0xc4, },
673 { .reg = LGDT3305_AGC_DELAY_PT_1,
674 .val = 0x0d, },
675 { .reg = LGDT3305_AGC_DELAY_PT_2,
676 .val = 0x30, },
677 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1,
678 .val = 0x80, },
679 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2,
680 .val = 0x00, },
681 { .reg = LGDT3305_IFBW_1,
682 .val = 0x80, },
683 { .reg = LGDT3305_IFBW_2,
684 .val = 0x00, },
685 { .reg = LGDT3305_AGC_CTRL_1,
686 .val = 0x30, },
687 { .reg = LGDT3305_AGC_CTRL_4,
688 .val = 0x61, },
689 { .reg = LGDT3305_FEC_BLOCK_CTRL,
690 .val = 0xff, },
691 { .reg = LGDT3305_TP_CTRL_1,
692 .val = 0x1b, },
693 }; 652 };
694 653
695 lg_dbg("\n"); 654 lg_dbg("\n");
696 655
697 ret = lgdt3305_write_regs(state, lgdt3305_init_data, 656 switch (state->cfg->demod_chip) {
698 ARRAY_SIZE(lgdt3305_init_data)); 657 case LGDT3304:
658 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
659 ARRAY_SIZE(lgdt3304_init_data));
660 break;
661 case LGDT3305:
662 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
663 ARRAY_SIZE(lgdt3305_init_data));
664 break;
665 default:
666 ret = -EINVAL;
667 }
699 if (lg_fail(ret)) 668 if (lg_fail(ret))
700 goto fail; 669 goto fail;
701 670
@@ -1198,7 +1167,7 @@ static struct dvb_frontend_ops lgdt3304_ops = {
1198 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 1167 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1199 }, 1168 },
1200 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl, 1169 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
1201 .init = lgdt3304_init, 1170 .init = lgdt3305_init,
1202 .set_frontend = lgdt3304_set_parameters, 1171 .set_frontend = lgdt3304_set_parameters,
1203 .get_frontend = lgdt3305_get_frontend, 1172 .get_frontend = lgdt3305_get_frontend,
1204 .get_tune_settings = lgdt3305_get_tune_settings, 1173 .get_tune_settings = lgdt3305_get_tune_settings,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 08:19:51 -0500