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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-12-26 11:19:48 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-12-31 06:36:04 -0500
commit5f82e6b18cb48e261f0a15a7f12c843b488234a5 (patch)
treef07f0129fa244a6fca2608366e1a4da133e1f8e7 /drivers/media/dvb/frontends
parent0f0d1a393948cc3cf6e16a4558055ca3aa23fcde (diff)
[media] tda1004x: convert set_fontend to use DVBv5 parameters
Instead of using dvb_frontend_parameters struct, that were designed for a subset of the supported standards, use the DVBv5 cache information. Also, fill the supported delivery systems at dvb_frontend_ops struct. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends')
-rw-r--r--drivers/media/dvb/frontends/tda1004x.c114
1 files changed, 58 insertions, 56 deletions
diff --git a/drivers/media/dvb/frontends/tda1004x.c b/drivers/media/dvb/frontends/tda1004x.c
index 2dbb0703529e..fe5b659a9e6b 100644
--- a/drivers/media/dvb/frontends/tda1004x.c
+++ b/drivers/media/dvb/frontends/tda1004x.c
@@ -224,22 +224,22 @@ static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
224} 224}
225 225
226static int tda10045h_set_bandwidth(struct tda1004x_state *state, 226static int tda10045h_set_bandwidth(struct tda1004x_state *state,
227 fe_bandwidth_t bandwidth) 227 u32 bandwidth)
228{ 228{
229 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f }; 229 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
230 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb }; 230 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
231 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 }; 231 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
232 232
233 switch (bandwidth) { 233 switch (bandwidth) {
234 case BANDWIDTH_6_MHZ: 234 case 6000000:
235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz)); 235 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
236 break; 236 break;
237 237
238 case BANDWIDTH_7_MHZ: 238 case 7000000:
239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz)); 239 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
240 break; 240 break;
241 241
242 case BANDWIDTH_8_MHZ: 242 case 8000000:
243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz)); 243 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
244 break; 244 break;
245 245
@@ -253,7 +253,7 @@ static int tda10045h_set_bandwidth(struct tda1004x_state *state,
253} 253}
254 254
255static int tda10046h_set_bandwidth(struct tda1004x_state *state, 255static int tda10046h_set_bandwidth(struct tda1004x_state *state,
256 fe_bandwidth_t bandwidth) 256 u32 bandwidth)
257{ 257{
258 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 }; 258 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
259 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f }; 259 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
@@ -270,7 +270,7 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
270 else 270 else
271 tda10046_clk53m = 1; 271 tda10046_clk53m = 1;
272 switch (bandwidth) { 272 switch (bandwidth) {
273 case BANDWIDTH_6_MHZ: 273 case 6000000:
274 if (tda10046_clk53m) 274 if (tda10046_clk53m)
275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, 275 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
276 sizeof(bandwidth_6mhz_53M)); 276 sizeof(bandwidth_6mhz_53M));
@@ -283,7 +283,7 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
283 } 283 }
284 break; 284 break;
285 285
286 case BANDWIDTH_7_MHZ: 286 case 7000000:
287 if (tda10046_clk53m) 287 if (tda10046_clk53m)
288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, 288 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
289 sizeof(bandwidth_7mhz_53M)); 289 sizeof(bandwidth_7mhz_53M));
@@ -296,7 +296,7 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
296 } 296 }
297 break; 297 break;
298 298
299 case BANDWIDTH_8_MHZ: 299 case 8000000:
300 if (tda10046_clk53m) 300 if (tda10046_clk53m)
301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, 301 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
302 sizeof(bandwidth_8mhz_53M)); 302 sizeof(bandwidth_8mhz_53M));
@@ -409,7 +409,7 @@ static int tda10045_fwupload(struct dvb_frontend* fe)
409 msleep(10); 409 msleep(10);
410 410
411 /* set parameters */ 411 /* set parameters */
412 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ); 412 tda10045h_set_bandwidth(state, 8000000);
413 413
414 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN); 414 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
415 release_firmware(fw); 415 release_firmware(fw);
@@ -473,7 +473,7 @@ static void tda10046_init_plls(struct dvb_frontend* fe)
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); 473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
474 break; 474 break;
475 } 475 }
476 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz 476 tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
477 /* let the PLLs settle */ 477 /* let the PLLs settle */
478 msleep(120); 478 msleep(120);
479} 479}
@@ -697,9 +697,9 @@ static int tda10046_init(struct dvb_frontend* fe)
697 return 0; 697 return 0;
698} 698}
699 699
700static int tda1004x_set_fe(struct dvb_frontend* fe, 700static int tda1004x_set_fe(struct dvb_frontend *fe)
701 struct dvb_frontend_parameters *fe_params)
702{ 701{
702 struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
703 struct tda1004x_state* state = fe->demodulator_priv; 703 struct tda1004x_state* state = fe->demodulator_priv;
704 int tmp; 704 int tmp;
705 int inversion; 705 int inversion;
@@ -726,37 +726,37 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
726 // Hardcoded to use auto as much as possible on the TDA10045 as it 726 // Hardcoded to use auto as much as possible on the TDA10045 as it
727 // is very unreliable if AUTO mode is _not_ used. 727 // is very unreliable if AUTO mode is _not_ used.
728 if (state->demod_type == TDA1004X_DEMOD_TDA10045) { 728 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
729 fe_params->u.ofdm.code_rate_HP = FEC_AUTO; 729 fe_params->code_rate_HP = FEC_AUTO;
730 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO; 730 fe_params->guard_interval = GUARD_INTERVAL_AUTO;
731 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO; 731 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
732 } 732 }
733 733
734 // Set standard params.. or put them to auto 734 // Set standard params.. or put them to auto
735 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) || 735 if ((fe_params->code_rate_HP == FEC_AUTO) ||
736 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) || 736 (fe_params->code_rate_LP == FEC_AUTO) ||
737 (fe_params->u.ofdm.constellation == QAM_AUTO) || 737 (fe_params->modulation == QAM_AUTO) ||
738 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) { 738 (fe_params->hierarchy == HIERARCHY_AUTO)) {
739 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto 739 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits 740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits 741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
742 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits 742 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
743 } else { 743 } else {
744 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto 744 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
745 745
746 // set HP FEC 746 // set HP FEC
747 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP); 747 tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
748 if (tmp < 0) 748 if (tmp < 0)
749 return tmp; 749 return tmp;
750 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); 750 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
751 751
752 // set LP FEC 752 // set LP FEC
753 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP); 753 tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
754 if (tmp < 0) 754 if (tmp < 0)
755 return tmp; 755 return tmp;
756 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); 756 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
757 757
758 // set constellation 758 /* set modulation */
759 switch (fe_params->u.ofdm.constellation) { 759 switch (fe_params->modulation) {
760 case QPSK: 760 case QPSK:
761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); 761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
762 break; 762 break;
@@ -774,7 +774,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
774 } 774 }
775 775
776 // set hierarchy 776 // set hierarchy
777 switch (fe_params->u.ofdm.hierarchy_information) { 777 switch (fe_params->hierarchy) {
778 case HIERARCHY_NONE: 778 case HIERARCHY_NONE:
779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); 779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
780 break; 780 break;
@@ -799,11 +799,11 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
799 // set bandwidth 799 // set bandwidth
800 switch (state->demod_type) { 800 switch (state->demod_type) {
801 case TDA1004X_DEMOD_TDA10045: 801 case TDA1004X_DEMOD_TDA10045:
802 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); 802 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
803 break; 803 break;
804 804
805 case TDA1004X_DEMOD_TDA10046: 805 case TDA1004X_DEMOD_TDA10046:
806 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth); 806 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
807 break; 807 break;
808 } 808 }
809 809
@@ -825,7 +825,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
825 } 825 }
826 826
827 // set guard interval 827 // set guard interval
828 switch (fe_params->u.ofdm.guard_interval) { 828 switch (fe_params->guard_interval) {
829 case GUARD_INTERVAL_1_32: 829 case GUARD_INTERVAL_1_32:
830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); 830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); 831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
@@ -856,7 +856,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
856 } 856 }
857 857
858 // set transmission mode 858 // set transmission mode
859 switch (fe_params->u.ofdm.transmission_mode) { 859 switch (fe_params->transmission_mode) {
860 case TRANSMISSION_MODE_2K: 860 case TRANSMISSION_MODE_2K:
861 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); 861 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
862 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); 862 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
@@ -895,7 +895,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe,
895 return 0; 895 return 0;
896} 896}
897 897
898static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) 898static int tda1004x_get_fe(struct dvb_frontend *fe, struct dtv_frontend_properties *fe_params)
899{ 899{
900 struct tda1004x_state* state = fe->demodulator_priv; 900 struct tda1004x_state* state = fe->demodulator_priv;
901 901
@@ -913,13 +913,13 @@ static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_paramete
913 case TDA1004X_DEMOD_TDA10045: 913 case TDA1004X_DEMOD_TDA10045:
914 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) { 914 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
915 case 0x14: 915 case 0x14:
916 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 916 fe_params->bandwidth_hz = 8000000;
917 break; 917 break;
918 case 0xdb: 918 case 0xdb:
919 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 919 fe_params->bandwidth_hz = 7000000;
920 break; 920 break;
921 case 0x4f: 921 case 0x4f:
922 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 922 fe_params->bandwidth_hz = 6000000;
923 break; 923 break;
924 } 924 }
925 break; 925 break;
@@ -927,73 +927,73 @@ static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_paramete
927 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { 927 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
928 case 0x5c: 928 case 0x5c:
929 case 0x54: 929 case 0x54:
930 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; 930 fe_params->bandwidth_hz = 8000000;
931 break; 931 break;
932 case 0x6a: 932 case 0x6a:
933 case 0x60: 933 case 0x60:
934 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; 934 fe_params->bandwidth_hz = 7000000;
935 break; 935 break;
936 case 0x7b: 936 case 0x7b:
937 case 0x70: 937 case 0x70:
938 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; 938 fe_params->bandwidth_hz = 6000000;
939 break; 939 break;
940 } 940 }
941 break; 941 break;
942 } 942 }
943 943
944 // FEC 944 // FEC
945 fe_params->u.ofdm.code_rate_HP = 945 fe_params->code_rate_HP =
946 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7); 946 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
947 fe_params->u.ofdm.code_rate_LP = 947 fe_params->code_rate_LP =
948 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7); 948 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
949 949
950 // constellation 950 /* modulation */
951 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) { 951 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
952 case 0: 952 case 0:
953 fe_params->u.ofdm.constellation = QPSK; 953 fe_params->modulation = QPSK;
954 break; 954 break;
955 case 1: 955 case 1:
956 fe_params->u.ofdm.constellation = QAM_16; 956 fe_params->modulation = QAM_16;
957 break; 957 break;
958 case 2: 958 case 2:
959 fe_params->u.ofdm.constellation = QAM_64; 959 fe_params->modulation = QAM_64;
960 break; 960 break;
961 } 961 }
962 962
963 // transmission mode 963 // transmission mode
964 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; 964 fe_params->transmission_mode = TRANSMISSION_MODE_2K;
965 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) 965 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
966 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 966 fe_params->transmission_mode = TRANSMISSION_MODE_8K;
967 967
968 // guard interval 968 // guard interval
969 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) { 969 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
970 case 0: 970 case 0:
971 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 971 fe_params->guard_interval = GUARD_INTERVAL_1_32;
972 break; 972 break;
973 case 1: 973 case 1:
974 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; 974 fe_params->guard_interval = GUARD_INTERVAL_1_16;
975 break; 975 break;
976 case 2: 976 case 2:
977 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; 977 fe_params->guard_interval = GUARD_INTERVAL_1_8;
978 break; 978 break;
979 case 3: 979 case 3:
980 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; 980 fe_params->guard_interval = GUARD_INTERVAL_1_4;
981 break; 981 break;
982 } 982 }
983 983
984 // hierarchy 984 // hierarchy
985 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) { 985 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
986 case 0: 986 case 0:
987 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE; 987 fe_params->hierarchy = HIERARCHY_NONE;
988 break; 988 break;
989 case 1: 989 case 1:
990 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1; 990 fe_params->hierarchy = HIERARCHY_1;
991 break; 991 break;
992 case 2: 992 case 2:
993 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2; 993 fe_params->hierarchy = HIERARCHY_2;
994 break; 994 break;
995 case 3: 995 case 3:
996 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4; 996 fe_params->hierarchy = HIERARCHY_4;
997 break; 997 break;
998 } 998 }
999 999
@@ -1231,6 +1231,7 @@ static void tda1004x_release(struct dvb_frontend* fe)
1231} 1231}
1232 1232
1233static struct dvb_frontend_ops tda10045_ops = { 1233static struct dvb_frontend_ops tda10045_ops = {
1234 .delsys = { SYS_DVBT },
1234 .info = { 1235 .info = {
1235 .name = "Philips TDA10045H DVB-T", 1236 .name = "Philips TDA10045H DVB-T",
1236 .type = FE_OFDM, 1237 .type = FE_OFDM,
@@ -1251,8 +1252,8 @@ static struct dvb_frontend_ops tda10045_ops = {
1251 .write = tda1004x_write, 1252 .write = tda1004x_write,
1252 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, 1253 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1253 1254
1254 .set_frontend_legacy = tda1004x_set_fe, 1255 .set_frontend = tda1004x_set_fe,
1255 .get_frontend_legacy = tda1004x_get_fe, 1256 .get_frontend = tda1004x_get_fe,
1256 .get_tune_settings = tda1004x_get_tune_settings, 1257 .get_tune_settings = tda1004x_get_tune_settings,
1257 1258
1258 .read_status = tda1004x_read_status, 1259 .read_status = tda1004x_read_status,
@@ -1301,6 +1302,7 @@ struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1301} 1302}
1302 1303
1303static struct dvb_frontend_ops tda10046_ops = { 1304static struct dvb_frontend_ops tda10046_ops = {
1305 .delsys = { SYS_DVBT },
1304 .info = { 1306 .info = {
1305 .name = "Philips TDA10046H DVB-T", 1307 .name = "Philips TDA10046H DVB-T",
1306 .type = FE_OFDM, 1308 .type = FE_OFDM,
@@ -1321,8 +1323,8 @@ static struct dvb_frontend_ops tda10046_ops = {
1321 .write = tda1004x_write, 1323 .write = tda1004x_write,
1322 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl, 1324 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1323 1325
1324 .set_frontend_legacy = tda1004x_set_fe, 1326 .set_frontend = tda1004x_set_fe,
1325 .get_frontend_legacy = tda1004x_get_fe, 1327 .get_frontend = tda1004x_get_fe,
1326 .get_tune_settings = tda1004x_get_tune_settings, 1328 .get_tune_settings = tda1004x_get_tune_settings,
1327 1329
1328 .read_status = tda1004x_read_status, 1330 .read_status = tda1004x_read_status,