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authorMichael Krufky <mkrufky@linuxtv.org>2007-11-23 14:52:15 -0500
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-01-25 16:02:59 -0500
commit6ca04de36b05aaf2f8122d0e566940969c6df801 (patch)
tree33433eed465b98bb5eb05a130441185a7e4483eb /drivers/media/dvb/frontends/tda18271-fe.c
parent63c254805e38bad4c64b5f5b0e135a2a357fa0bf (diff)
V4L/DVB (6680): tda18271: move tda18271_map tables to a separate source file
Move tda18271_map tables to a separate source file, to improve code readability and ease maintenance. Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends/tda18271-fe.c')
-rw-r--r--drivers/media/dvb/frontends/tda18271-fe.c784
1 files changed, 784 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/tda18271-fe.c b/drivers/media/dvb/frontends/tda18271-fe.c
new file mode 100644
index 000000000000..ba980cf5811b
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271-fe.c
@@ -0,0 +1,784 @@
1/*
2 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include <linux/delay.h>
22#include <linux/videodev2.h>
23#include "tuner-driver.h"
24
25#include "tda18271.h"
26#include "tda18271-priv.h"
27
28static int debug;
29module_param(debug, int, 0644);
30MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
31
32#define dprintk(level, fmt, arg...) do {\
33 if (debug >= level) \
34 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ##arg); } while (0)
35
36/*---------------------------------------------------------------------*/
37
38#define TDA18271_ANALOG 0
39#define TDA18271_DIGITAL 1
40
41struct tda18271_priv {
42 u8 i2c_addr;
43 struct i2c_adapter *i2c_adap;
44 unsigned char tda18271_regs[TDA18271_NUM_REGS];
45 int mode;
46
47 u32 frequency;
48 u32 bandwidth;
49};
50
51static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
52{
53 struct tda18271_priv *priv = fe->tuner_priv;
54 struct analog_tuner_ops *ops = fe->ops.analog_demod_ops;
55 int ret = 0;
56
57 switch (priv->mode) {
58 case TDA18271_ANALOG:
59 if (ops && ops->i2c_gate_ctrl)
60 ret = ops->i2c_gate_ctrl(fe, enable);
61 break;
62 case TDA18271_DIGITAL:
63 if (fe->ops.i2c_gate_ctrl)
64 ret = fe->ops.i2c_gate_ctrl(fe, enable);
65 break;
66 }
67
68 return ret;
69};
70
71/*---------------------------------------------------------------------*/
72
73static void tda18271_dump_regs(struct dvb_frontend *fe)
74{
75 struct tda18271_priv *priv = fe->tuner_priv;
76 unsigned char *regs = priv->tda18271_regs;
77
78 dprintk(1, "=== TDA18271 REG DUMP ===\n");
79 dprintk(1, "ID_BYTE = 0x%x\n", 0xff & regs[R_ID]);
80 dprintk(1, "THERMO_BYTE = 0x%x\n", 0xff & regs[R_TM]);
81 dprintk(1, "POWER_LEVEL_BYTE = 0x%x\n", 0xff & regs[R_PL]);
82 dprintk(1, "EASY_PROG_BYTE_1 = 0x%x\n", 0xff & regs[R_EP1]);
83 dprintk(1, "EASY_PROG_BYTE_2 = 0x%x\n", 0xff & regs[R_EP2]);
84 dprintk(1, "EASY_PROG_BYTE_3 = 0x%x\n", 0xff & regs[R_EP3]);
85 dprintk(1, "EASY_PROG_BYTE_4 = 0x%x\n", 0xff & regs[R_EP4]);
86 dprintk(1, "EASY_PROG_BYTE_5 = 0x%x\n", 0xff & regs[R_EP5]);
87 dprintk(1, "CAL_POST_DIV_BYTE = 0x%x\n", 0xff & regs[R_CPD]);
88 dprintk(1, "CAL_DIV_BYTE_1 = 0x%x\n", 0xff & regs[R_CD1]);
89 dprintk(1, "CAL_DIV_BYTE_2 = 0x%x\n", 0xff & regs[R_CD2]);
90 dprintk(1, "CAL_DIV_BYTE_3 = 0x%x\n", 0xff & regs[R_CD3]);
91 dprintk(1, "MAIN_POST_DIV_BYTE = 0x%x\n", 0xff & regs[R_MPD]);
92 dprintk(1, "MAIN_DIV_BYTE_1 = 0x%x\n", 0xff & regs[R_MD1]);
93 dprintk(1, "MAIN_DIV_BYTE_2 = 0x%x\n", 0xff & regs[R_MD2]);
94 dprintk(1, "MAIN_DIV_BYTE_3 = 0x%x\n", 0xff & regs[R_MD3]);
95}
96
97static void tda18271_read_regs(struct dvb_frontend *fe)
98{
99 struct tda18271_priv *priv = fe->tuner_priv;
100 unsigned char *regs = priv->tda18271_regs;
101 unsigned char buf = 0x00;
102 int ret;
103 struct i2c_msg msg[] = {
104 { .addr = priv->i2c_addr, .flags = 0,
105 .buf = &buf, .len = 1 },
106 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
107 .buf = regs, .len = 16 }
108 };
109
110 tda18271_i2c_gate_ctrl(fe, 1);
111
112 /* read all registers */
113 ret = i2c_transfer(priv->i2c_adap, msg, 2);
114
115 tda18271_i2c_gate_ctrl(fe, 0);
116
117 if (ret != 2)
118 printk("ERROR: %s: i2c_transfer returned: %d\n",
119 __FUNCTION__, ret);
120
121 if (debug > 2)
122 tda18271_dump_regs(fe);
123}
124
125static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
126{
127 struct tda18271_priv *priv = fe->tuner_priv;
128 unsigned char *regs = priv->tda18271_regs;
129 unsigned char buf[TDA18271_NUM_REGS+1];
130 struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
131 .buf = buf, .len = len+1 };
132 int i, ret;
133
134 BUG_ON((len == 0) || (idx+len > sizeof(buf)));
135
136 buf[0] = idx;
137 for (i = 1; i <= len; i++) {
138 buf[i] = regs[idx-1+i];
139 }
140
141 tda18271_i2c_gate_ctrl(fe, 1);
142
143 /* write registers */
144 ret = i2c_transfer(priv->i2c_adap, &msg, 1);
145
146 tda18271_i2c_gate_ctrl(fe, 0);
147
148 if (ret != 1)
149 printk(KERN_WARNING "ERROR: %s: i2c_transfer returned: %d\n",
150 __FUNCTION__, ret);
151}
152
153/*---------------------------------------------------------------------*/
154
155static int tda18271_init_regs(struct dvb_frontend *fe)
156{
157 struct tda18271_priv *priv = fe->tuner_priv;
158 unsigned char *regs = priv->tda18271_regs;
159
160 printk(KERN_INFO "tda18271: initializing registers\n");
161
162 /* initialize registers */
163 regs[R_ID] = 0x83;
164 regs[R_TM] = 0x08;
165 regs[R_PL] = 0x80;
166 regs[R_EP1] = 0xc6;
167 regs[R_EP2] = 0xdf;
168 regs[R_EP3] = 0x16;
169 regs[R_EP4] = 0x60;
170 regs[R_EP5] = 0x80;
171 regs[R_CPD] = 0x80;
172 regs[R_CD1] = 0x00;
173 regs[R_CD2] = 0x00;
174 regs[R_CD3] = 0x00;
175 regs[R_MPD] = 0x00;
176 regs[R_MD1] = 0x00;
177 regs[R_MD2] = 0x00;
178 regs[R_MD3] = 0x00;
179 regs[R_EB1] = 0xff;
180 regs[R_EB2] = 0x01;
181 regs[R_EB3] = 0x84;
182 regs[R_EB4] = 0x41;
183 regs[R_EB5] = 0x01;
184 regs[R_EB6] = 0x84;
185 regs[R_EB7] = 0x40;
186 regs[R_EB8] = 0x07;
187 regs[R_EB9] = 0x00;
188 regs[R_EB10] = 0x00;
189 regs[R_EB11] = 0x96;
190 regs[R_EB12] = 0x0f;
191 regs[R_EB13] = 0xc1;
192 regs[R_EB14] = 0x00;
193 regs[R_EB15] = 0x8f;
194 regs[R_EB16] = 0x00;
195 regs[R_EB17] = 0x00;
196 regs[R_EB18] = 0x00;
197 regs[R_EB19] = 0x00;
198 regs[R_EB20] = 0x20;
199 regs[R_EB21] = 0x33;
200 regs[R_EB22] = 0x48;
201 regs[R_EB23] = 0xb0;
202
203 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
204 /* setup AGC1 & AGC2 */
205 regs[R_EB17] = 0x00;
206 tda18271_write_regs(fe, R_EB17, 1);
207 regs[R_EB17] = 0x03;
208 tda18271_write_regs(fe, R_EB17, 1);
209 regs[R_EB17] = 0x43;
210 tda18271_write_regs(fe, R_EB17, 1);
211 regs[R_EB17] = 0x4c;
212 tda18271_write_regs(fe, R_EB17, 1);
213
214 regs[R_EB20] = 0xa0;
215 tda18271_write_regs(fe, R_EB20, 1);
216 regs[R_EB20] = 0xa7;
217 tda18271_write_regs(fe, R_EB20, 1);
218 regs[R_EB20] = 0xe7;
219 tda18271_write_regs(fe, R_EB20, 1);
220 regs[R_EB20] = 0xec;
221 tda18271_write_regs(fe, R_EB20, 1);
222
223 /* image rejection calibration */
224
225 /* low-band */
226 regs[R_EP3] = 0x1f;
227 regs[R_EP4] = 0x66;
228 regs[R_EP5] = 0x81;
229 regs[R_CPD] = 0xcc;
230 regs[R_CD1] = 0x6c;
231 regs[R_CD2] = 0x00;
232 regs[R_CD3] = 0x00;
233 regs[R_MPD] = 0xcd;
234 regs[R_MD1] = 0x77;
235 regs[R_MD2] = 0x08;
236 regs[R_MD3] = 0x00;
237
238 tda18271_write_regs(fe, R_EP3, 11);
239 msleep(5); /* pll locking */
240
241 regs[R_EP1] = 0xc6;
242 tda18271_write_regs(fe, R_EP1, 1);
243 msleep(5); /* wanted low measurement */
244
245 regs[R_EP3] = 0x1f;
246 regs[R_EP4] = 0x66;
247 regs[R_EP5] = 0x85;
248 regs[R_CPD] = 0xcb;
249 regs[R_CD1] = 0x66;
250 regs[R_CD2] = 0x70;
251 regs[R_CD3] = 0x00;
252
253 tda18271_write_regs(fe, R_EP3, 7);
254 msleep(5); /* pll locking */
255
256 regs[R_EP2] = 0xdf;
257 tda18271_write_regs(fe, R_EP2, 1);
258 msleep(30); /* image low optimization completion */
259
260 /* mid-band */
261 regs[R_EP3] = 0x1f;
262 regs[R_EP4] = 0x66;
263 regs[R_EP5] = 0x82;
264 regs[R_CPD] = 0xa8;
265 regs[R_CD1] = 0x66;
266 regs[R_CD2] = 0x00;
267 regs[R_CD3] = 0x00;
268 regs[R_MPD] = 0xa9;
269 regs[R_MD1] = 0x73;
270 regs[R_MD2] = 0x1a;
271 regs[R_MD3] = 0x00;
272
273 tda18271_write_regs(fe, R_EP3, 11);
274 msleep(5); /* pll locking */
275
276 regs[R_EP1] = 0xc6;
277 tda18271_write_regs(fe, R_EP1, 1);
278 msleep(5); /* wanted mid measurement */
279
280 regs[R_EP3] = 0x1f;
281 regs[R_EP4] = 0x66;
282 regs[R_EP5] = 0x86;
283 regs[R_CPD] = 0xa8;
284 regs[R_CD1] = 0x66;
285 regs[R_CD2] = 0xa0;
286 regs[R_CD3] = 0x00;
287
288 tda18271_write_regs(fe, R_EP3, 7);
289 msleep(5); /* pll locking */
290
291 regs[R_EP2] = 0xdf;
292 tda18271_write_regs(fe, R_EP2, 1);
293 msleep(30); /* image mid optimization completion */
294
295 /* high-band */
296 regs[R_EP3] = 0x1f;
297 regs[R_EP4] = 0x66;
298 regs[R_EP5] = 0x83;
299 regs[R_CPD] = 0x98;
300 regs[R_CD1] = 0x65;
301 regs[R_CD2] = 0x00;
302 regs[R_CD3] = 0x00;
303 regs[R_MPD] = 0x99;
304 regs[R_MD1] = 0x71;
305 regs[R_MD2] = 0xcd;
306 regs[R_MD3] = 0x00;
307
308 tda18271_write_regs(fe, R_EP3, 11);
309 msleep(5); /* pll locking */
310
311 regs[R_EP1] = 0xc6;
312 tda18271_write_regs(fe, R_EP1, 1);
313 msleep(5); /* wanted high measurement */
314
315 regs[R_EP3] = 0x1f;
316 regs[R_EP4] = 0x66;
317 regs[R_EP5] = 0x87;
318 regs[R_CPD] = 0x98;
319 regs[R_CD1] = 0x65;
320 regs[R_CD2] = 0x50;
321 regs[R_CD3] = 0x00;
322
323 tda18271_write_regs(fe, R_EP3, 7);
324 msleep(5); /* pll locking */
325
326 regs[R_EP2] = 0xdf;
327
328 tda18271_write_regs(fe, R_EP2, 1);
329 msleep(30); /* image high optimization completion */
330
331 regs[R_EP4] = 0x64;
332 tda18271_write_regs(fe, R_EP4, 1);
333
334 regs[R_EP1] = 0xc6;
335 tda18271_write_regs(fe, R_EP1, 1);
336
337 return 0;
338}
339
340static int tda18271_tune(struct dvb_frontend *fe,
341 u32 ifc, u32 freq, u32 bw, u8 std)
342{
343 struct tda18271_priv *priv = fe->tuner_priv;
344 unsigned char *regs = priv->tda18271_regs;
345 u32 div, N = 0;
346 int i;
347
348 tda18271_read_regs(fe);
349
350 /* test IR_CAL_OK to see if we need init */
351 if ((regs[R_EP1] & 0x08) == 0)
352 tda18271_init_regs(fe);
353
354
355 dprintk(1, "freq = %d, ifc = %d\n", freq, ifc);
356
357 /* RF tracking filter calibration */
358
359 /* calculate BP_Filter */
360 i = 0;
361 while ((tda18271_bp_filter[i].rfmax * 1000) < freq) {
362 if (tda18271_bp_filter[i + 1].rfmax == 0)
363 break;
364 i++;
365 }
366 dprintk(2, "bp filter = 0x%x, i = %d\n", tda18271_bp_filter[i].val, i);
367
368 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
369 regs[R_EP1] |= tda18271_bp_filter[i].val;
370 tda18271_write_regs(fe, R_EP1, 1);
371
372 regs[R_EB4] &= 0x07;
373 regs[R_EB4] |= 0x60;
374 tda18271_write_regs(fe, R_EB4, 1);
375
376 regs[R_EB7] = 0x60;
377 tda18271_write_regs(fe, R_EB7, 1);
378
379 regs[R_EB14] = 0x00;
380 tda18271_write_regs(fe, R_EB14, 1);
381
382 regs[R_EB20] = 0xcc;
383 tda18271_write_regs(fe, R_EB20, 1);
384
385 /* set CAL mode to RF tracking filter calibration */
386 regs[R_EB4] |= 0x03;
387
388 /* calculate CAL PLL */
389
390 switch (priv->mode) {
391 case TDA18271_ANALOG:
392 N = freq - 1250000;
393 break;
394 case TDA18271_DIGITAL:
395 N = freq + bw / 2;
396 break;
397 }
398
399 i = 0;
400 while ((tda18271_cal_pll[i].lomax * 1000) < N) {
401 if (tda18271_cal_pll[i + 1].lomax == 0)
402 break;
403 i++;
404 }
405 dprintk(2, "cal pll, pd = 0x%x, d = 0x%x, i = %d\n",
406 tda18271_cal_pll[i].pd, tda18271_cal_pll[i].d, i);
407
408 regs[R_CPD] = tda18271_cal_pll[i].pd;
409
410 div = ((tda18271_cal_pll[i].d * (N / 1000)) << 7) / 125;
411 regs[R_CD1] = 0xff & (div >> 16);
412 regs[R_CD2] = 0xff & (div >> 8);
413 regs[R_CD3] = 0xff & div;
414
415 /* calculate MAIN PLL */
416
417 switch (priv->mode) {
418 case TDA18271_ANALOG:
419 N = freq - 250000;
420 break;
421 case TDA18271_DIGITAL:
422 N = freq + bw / 2 + 1000000;
423 break;
424 }
425
426 i = 0;
427 while ((tda18271_main_pll[i].lomax * 1000) < N) {
428 if (tda18271_main_pll[i + 1].lomax == 0)
429 break;
430 i++;
431 }
432 dprintk(2, "main pll, pd = 0x%x, d = 0x%x, i = %d\n",
433 tda18271_main_pll[i].pd, tda18271_main_pll[i].d, i);
434
435 regs[R_MPD] = (0x7f & tda18271_main_pll[i].pd);
436
437 switch (priv->mode) {
438 case TDA18271_ANALOG:
439 regs[R_MPD] &= ~0x08;
440 break;
441 case TDA18271_DIGITAL:
442 regs[R_MPD] |= 0x08;
443 break;
444 }
445
446 div = ((tda18271_main_pll[i].d * (N / 1000)) << 7) / 125;
447 regs[R_MD1] = 0xff & (div >> 16);
448 regs[R_MD2] = 0xff & (div >> 8);
449 regs[R_MD3] = 0xff & div;
450
451 tda18271_write_regs(fe, R_EP3, 11);
452 msleep(5); /* RF tracking filter calibration initialization */
453
454 /* search for K,M,CO for RF Calibration */
455 i = 0;
456 while ((tda18271_km[i].rfmax * 1000) < freq) {
457 if (tda18271_km[i + 1].rfmax == 0)
458 break;
459 i++;
460 }
461 dprintk(2, "km = 0x%x, i = %d\n", tda18271_km[i].val, i);
462
463 regs[R_EB13] &= 0x83;
464 regs[R_EB13] |= tda18271_km[i].val;
465 tda18271_write_regs(fe, R_EB13, 1);
466
467 /* search for RF_BAND */
468 i = 0;
469 while ((tda18271_rf_band[i].rfmax * 1000) < freq) {
470 if (tda18271_rf_band[i + 1].rfmax == 0)
471 break;
472 i++;
473 }
474 dprintk(2, "rf band = 0x%x, i = %d\n", tda18271_rf_band[i].val, i);
475
476 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
477 regs[R_EP2] |= (tda18271_rf_band[i].val << 5);
478
479 /* search for Gain_Taper */
480 i = 0;
481 while ((tda18271_gain_taper[i].rfmax * 1000) < freq) {
482 if (tda18271_gain_taper[i + 1].rfmax == 0)
483 break;
484 i++;
485 }
486 dprintk(2, "gain taper = 0x%x, i = %d\n",
487 tda18271_gain_taper[i].val, i);
488
489 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
490 regs[R_EP2] |= tda18271_gain_taper[i].val;
491
492 tda18271_write_regs(fe, R_EP2, 1);
493 tda18271_write_regs(fe, R_EP1, 1);
494 tda18271_write_regs(fe, R_EP2, 1);
495 tda18271_write_regs(fe, R_EP1, 1);
496
497 regs[R_EB4] &= 0x07;
498 regs[R_EB4] |= 0x40;
499 tda18271_write_regs(fe, R_EB4, 1);
500
501 regs[R_EB7] = 0x40;
502 tda18271_write_regs(fe, R_EB7, 1);
503 msleep(10);
504
505 regs[R_EB20] = 0xec;
506 tda18271_write_regs(fe, R_EB20, 1);
507 msleep(60); /* RF tracking filter calibration completion */
508
509 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
510 tda18271_write_regs(fe, R_EP4, 1);
511
512 tda18271_write_regs(fe, R_EP1, 1);
513
514 /* RF tracking filer correction for VHF_Low band */
515 i = 0;
516 while ((tda18271_rf_cal[i].rfmax * 1000) < freq) {
517 if (tda18271_rf_cal[i].rfmax == 0)
518 break;
519 i++;
520 }
521 dprintk(2, "rf cal = 0x%x, i = %d\n", tda18271_rf_cal[i].val, i);
522
523 /* VHF_Low band only */
524 if (tda18271_rf_cal[i].rfmax != 0) {
525 regs[R_EB14] = tda18271_rf_cal[i].val;
526 tda18271_write_regs(fe, R_EB14, 1);
527 }
528
529 /* Channel Configuration */
530
531 switch (priv->mode) {
532 case TDA18271_ANALOG:
533 regs[R_EB22] = 0x2c;
534 break;
535 case TDA18271_DIGITAL:
536 regs[R_EB22] = 0x37;
537 break;
538 }
539 tda18271_write_regs(fe, R_EB22, 1);
540
541 regs[R_EP1] |= 0x40; /* set dis power level on */
542
543 /* set standard */
544 regs[R_EP3] &= ~0x1f; /* clear std bits */
545
546 /* see table 22 */
547 regs[R_EP3] |= std;
548
549 regs[R_EP4] &= ~0x03; /* set cal mode to normal */
550
551 regs[R_EP4] &= ~0x1c; /* clear if level bits */
552 switch (priv->mode) {
553 case TDA18271_ANALOG:
554 regs[R_MPD] &= ~0x80; /* IF notch = 0 */
555 break;
556 case TDA18271_DIGITAL:
557 regs[R_EP4] |= 0x04;
558 regs[R_MPD] |= 0x80;
559 break;
560 }
561
562 regs[R_EP4] &= ~0x80; /* turn this bit on only for fm */
563
564 /* FIXME: image rejection validity EP5[2:0] */
565
566 /* calculate MAIN PLL */
567 N = freq + ifc;
568
569 i = 0;
570 while ((tda18271_main_pll[i].lomax * 1000) < N) {
571 if (tda18271_main_pll[i + 1].lomax == 0)
572 break;
573 i++;
574 }
575 dprintk(2, "main pll, pd = 0x%x, d = 0x%x, i = %d\n",
576 tda18271_main_pll[i].pd, tda18271_main_pll[i].d, i);
577
578 regs[R_MPD] = (0x7f & tda18271_main_pll[i].pd);
579 switch (priv->mode) {
580 case TDA18271_ANALOG:
581 regs[R_MPD] &= ~0x08;
582 break;
583 case TDA18271_DIGITAL:
584 regs[R_MPD] |= 0x08;
585 break;
586 }
587
588 div = ((tda18271_main_pll[i].d * (N / 1000)) << 7) / 125;
589 regs[R_MD1] = 0xff & (div >> 16);
590 regs[R_MD2] = 0xff & (div >> 8);
591 regs[R_MD3] = 0xff & div;
592
593 tda18271_write_regs(fe, R_TM, 15);
594 msleep(5);
595
596 return 0;
597}
598
599/* ------------------------------------------------------------------ */
600
601static int tda18271_set_params(struct dvb_frontend *fe,
602 struct dvb_frontend_parameters *params)
603{
604 struct tda18271_priv *priv = fe->tuner_priv;
605 u8 std;
606 u32 bw, sgIF = 0;
607
608 u32 freq = params->frequency;
609
610 priv->mode = TDA18271_DIGITAL;
611
612 /* see table 22 */
613 if (fe->ops.info.type == FE_ATSC) {
614 switch (params->u.vsb.modulation) {
615 case VSB_8:
616 case VSB_16:
617 std = 0x1b; /* device-specific (spec says 0x1c) */
618 sgIF = 5380000;
619 break;
620 case QAM_64:
621 case QAM_256:
622 std = 0x18; /* device-specific (spec says 0x1d) */
623 sgIF = 4000000;
624 break;
625 default:
626 printk(KERN_WARNING "%s: modulation not set!\n",
627 __FUNCTION__);
628 return -EINVAL;
629 }
630 freq += 1750000; /* Adjust to center (+1.75MHZ) */
631 bw = 6000000;
632 } else if (fe->ops.info.type == FE_OFDM) {
633 switch (params->u.ofdm.bandwidth) {
634 case BANDWIDTH_6_MHZ:
635 std = 0x1b; /* device-specific (spec says 0x1c) */
636 bw = 6000000;
637 sgIF = 3300000;
638 break;
639 case BANDWIDTH_7_MHZ:
640 std = 0x19; /* device-specific (spec says 0x1d) */
641 bw = 7000000;
642 sgIF = 3800000;
643 break;
644 case BANDWIDTH_8_MHZ:
645 std = 0x1a; /* device-specific (spec says 0x1e) */
646 bw = 8000000;
647 sgIF = 4300000;
648 break;
649 default:
650 printk(KERN_WARNING "%s: bandwidth not set!\n",
651 __FUNCTION__);
652 return -EINVAL;
653 }
654 } else {
655 printk(KERN_WARNING "%s: modulation type not supported!\n",
656 __FUNCTION__);
657 return -EINVAL;
658 }
659
660 return tda18271_tune(fe, sgIF, freq, bw, std);
661}
662
663static int tda18271_set_analog_params(struct dvb_frontend *fe,
664 struct analog_parameters *params)
665{
666 struct tda18271_priv *priv = fe->tuner_priv;
667 u8 std;
668 unsigned int sgIF;
669 char *mode;
670
671 priv->mode = TDA18271_ANALOG;
672
673 /* see table 22 */
674 if (params->std & V4L2_STD_MN) {
675 std = 0x0d;
676 sgIF = 92;
677 mode = "MN";
678 } else if (params->std & V4L2_STD_B) {
679 std = 0x0e;
680 sgIF = 108;
681 mode = "B";
682 } else if (params->std & V4L2_STD_GH) {
683 std = 0x0f;
684 sgIF = 124;
685 mode = "GH";
686 } else if (params->std & V4L2_STD_PAL_I) {
687 std = 0x0f;
688 sgIF = 124;
689 mode = "I";
690 } else if (params->std & V4L2_STD_DK) {
691 std = 0x0f;
692 sgIF = 124;
693 mode = "DK";
694 } else if (params->std & V4L2_STD_SECAM_L) {
695 std = 0x0f;
696 sgIF = 124;
697 mode = "L";
698 } else if (params->std & V4L2_STD_SECAM_LC) {
699 std = 0x0f;
700 sgIF = 20;
701 mode = "LC";
702 } else {
703 std = 0x0f;
704 sgIF = 124;
705 mode = "xx";
706 }
707
708 if (params->mode == V4L2_TUNER_RADIO)
709 sgIF = 88; /* if frequency is 5.5 MHz */
710
711 dprintk(1, "setting tda18271 to system %s\n", mode);
712
713 return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
714 0, std);
715}
716
717static int tda18271_release(struct dvb_frontend *fe)
718{
719 kfree(fe->tuner_priv);
720 fe->tuner_priv = NULL;
721 return 0;
722}
723
724static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
725{
726 struct tda18271_priv *priv = fe->tuner_priv;
727 *frequency = priv->frequency;
728 return 0;
729}
730
731static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
732{
733 struct tda18271_priv *priv = fe->tuner_priv;
734 *bandwidth = priv->bandwidth;
735 return 0;
736}
737
738static struct dvb_tuner_ops tda18271_tuner_ops = {
739 .info = {
740 .name = "NXP TDA18271HD",
741 .frequency_min = 45000000,
742 .frequency_max = 864000000,
743 .frequency_step = 62500
744 },
745 .init = tda18271_init_regs,
746 .set_params = tda18271_set_params,
747 .set_analog_params = tda18271_set_analog_params,
748 .release = tda18271_release,
749 .get_frequency = tda18271_get_frequency,
750 .get_bandwidth = tda18271_get_bandwidth,
751};
752
753struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
754 struct i2c_adapter *i2c)
755{
756 struct tda18271_priv *priv = NULL;
757
758 dprintk(1, "@ %d-%04x\n", i2c_adapter_id(i2c), addr);
759 priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
760 if (priv == NULL)
761 return NULL;
762
763 priv->i2c_addr = addr;
764 priv->i2c_adap = i2c;
765
766 memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
767 sizeof(struct dvb_tuner_ops));
768
769 fe->tuner_priv = priv;
770
771 return fe;
772}
773EXPORT_SYMBOL_GPL(tda18271_attach);
774MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
775MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
776MODULE_LICENSE("GPL");
777
778/*
779 * Overrides for Emacs so that we follow Linus's tabbing style.
780 * ---------------------------------------------------------------------------
781 * Local variables:
782 * c-basic-offset: 8
783 * End:
784 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 22:09:32 -0500