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authorAntti Palosaari <crope@iki.fi>2007-01-21 13:56:10 -0500
committerMauro Carvalho Chehab <mchehab@infradead.org>2007-02-21 10:34:53 -0500
commitcbdc80ed8f59e204c031b52ea7e44f419029f75b (patch)
tree86e58128fc49ad39beeba4971bfbbbc077faae5a /drivers/media/dvb/frontends/qt1010.c
parent1f61f3bab303c02cfd822c952284a381089452a0 (diff)
V4L/DVB (5137): Dvb: add new qt1010 tuner module
QT1010: - old qt1010-code totally rewritten and put in own kernel module - same enhancements as my earlier QT1010 125kHz patch - tuner initialization - register 1f calculation - register 20 calculation - register 25 calculation m920x: (MSI Megasky) - use new QT1010 module instead of old code Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends/qt1010.c')
-rw-r--r--drivers/media/dvb/frontends/qt1010.c452
1 files changed, 452 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/qt1010.c b/drivers/media/dvb/frontends/qt1010.c
new file mode 100644
index 000000000000..d7360f45355a
--- /dev/null
+++ b/drivers/media/dvb/frontends/qt1010.c
@@ -0,0 +1,452 @@
1/*
2 * Driver for Quantek QT1010 silicon tuner
3 *
4 * Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
5 * Aapo Tahkola <aet@rasterburn.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21#include "qt1010.h"
22#include "qt1010_priv.h"
23
24static int debug;
25module_param(debug, int, 0644);
26MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
27
28#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "QT1010: " args); printk("\n"); }} while (0)
29
30/* read single register */
31static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
32{
33 struct i2c_msg msg[2] = {
34 { .addr = priv->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 },
35 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 },
36 };
37
38 if (i2c_transfer(priv->i2c, msg, 2) != 2) {
39 printk(KERN_WARNING "qt1010 I2C read failed\n");
40 return -EREMOTEIO;
41 }
42 return 0;
43}
44
45/* write single register */
46static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
47{
48 u8 buf[2] = { reg, val };
49 struct i2c_msg msg = {
50 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
51 };
52
53 if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
54 printk(KERN_WARNING "qt1010 I2C write failed\n");
55 return -EREMOTEIO;
56 }
57 return 0;
58}
59
60/* dump all registers */
61static void qt1010_dump_regs(struct qt1010_priv *priv)
62{
63 char buf[52], buf2[4];
64 u8 reg, val;
65
66 for (reg = 0; ; reg++) {
67 if (reg % 16 == 0) {
68 if (reg)
69 printk("%s\n", buf);
70 sprintf(buf, "%02x: ", reg);
71 }
72 if (qt1010_readreg(priv, reg, &val) == 0)
73 sprintf(buf2, "%02x ", val);
74 else
75 strcpy(buf2, "-- ");
76 strcat(buf, buf2);
77 if (reg == 0x2f)
78 break;
79 }
80 printk("%s\n", buf);
81}
82
83static int qt1010_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
84{
85 struct qt1010_priv *priv;
86 int err;
87 u32 freq, div, mod1, mod2;
88 u8 i, tmpval, reg05;
89 qt1010_i2c_oper_t rd[48] = {
90 { QT1010_WR, 0x01, 0x80 },
91 { QT1010_WR, 0x02, 0x3f },
92 { QT1010_WR, 0x05, 0xff }, /* 02 c write */
93 { QT1010_WR, 0x06, 0x44 },
94 { QT1010_WR, 0x07, 0xff }, /* 04 c write */
95 { QT1010_WR, 0x08, 0x08 },
96 { QT1010_WR, 0x09, 0xff }, /* 06 c write */
97 { QT1010_WR, 0x0a, 0xff }, /* 07 c write */
98 { QT1010_WR, 0x0b, 0xff }, /* 08 c write */
99 { QT1010_WR, 0x0c, 0xe1 },
100 { QT1010_WR, 0x1a, 0xff }, /* 10 c write */
101 { QT1010_WR, 0x1b, 0x00 },
102 { QT1010_WR, 0x1c, 0x89 },
103 { QT1010_WR, 0x11, 0xff }, /* 13 c write */
104 { QT1010_WR, 0x12, 0xff }, /* 14 c write */
105 { QT1010_WR, 0x22, 0xff }, /* 15 c write */
106 { QT1010_WR, 0x1e, 0x00 },
107 { QT1010_WR, 0x1e, 0xd0 },
108 { QT1010_RD, 0x22, 0xff }, /* 16 c read */
109 { QT1010_WR, 0x1e, 0x00 },
110 { QT1010_RD, 0x05, 0xff }, /* 20 c read */
111 { QT1010_RD, 0x22, 0xff }, /* 21 c read */
112 { QT1010_WR, 0x23, 0xd0 },
113 { QT1010_WR, 0x1e, 0x00 },
114 { QT1010_WR, 0x1e, 0xe0 },
115 { QT1010_RD, 0x23, 0xff }, /* 25 c read */
116 { QT1010_RD, 0x23, 0xff }, /* 26 c read */
117 { QT1010_WR, 0x1e, 0x00 },
118 { QT1010_WR, 0x24, 0xd0 },
119 { QT1010_WR, 0x1e, 0x00 },
120 { QT1010_WR, 0x1e, 0xf0 },
121 { QT1010_RD, 0x24, 0xff }, /* 31 c read */
122 { QT1010_WR, 0x1e, 0x00 },
123 { QT1010_WR, 0x14, 0x7f },
124 { QT1010_WR, 0x15, 0x7f },
125 { QT1010_WR, 0x05, 0xff }, /* 35 c write */
126 { QT1010_WR, 0x06, 0x00 },
127 { QT1010_WR, 0x15, 0x1f },
128 { QT1010_WR, 0x16, 0xff },
129 { QT1010_WR, 0x18, 0xff },
130 { QT1010_WR, 0x1f, 0xff }, /* 40 c write */
131 { QT1010_WR, 0x20, 0xff }, /* 41 c write */
132 { QT1010_WR, 0x21, 0x53 },
133 { QT1010_WR, 0x25, 0xff }, /* 43 c write */
134 { QT1010_WR, 0x26, 0x15 },
135 { QT1010_WR, 0x00, 0xff }, /* 45 c write */
136 { QT1010_WR, 0x02, 0x00 },
137 { QT1010_WR, 0x01, 0x00 }
138 };
139
140#define FREQ1 32000000 /* 32 MHz */
141#define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */
142
143 priv = fe->tuner_priv;
144 freq = params->frequency;
145 div = (freq + QT1010_OFFSET) / QT1010_STEP;
146 freq = (div * QT1010_STEP) - QT1010_OFFSET;
147 mod1 = (freq + QT1010_OFFSET) % FREQ1;
148 mod2 = (freq + QT1010_OFFSET) % FREQ2;
149 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
150 priv->frequency = freq;
151
152 /* reg 05 base value */
153 if (freq < 290000000) reg05 = 0x14; /* 290 MHz */
154 else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
155 else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
156 else reg05 = 0x74;
157
158 /* 0x5 */
159 rd[2].val = reg05;
160
161 /* 07 - set frequency: 32 MHz scale */
162 rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
163
164 /* 09 - changes every 8/24 MHz */
165 if (mod1 < 8000000) rd[6].val = 0x1d;
166 else rd[6].val = 0x1c;
167
168 /* 0a - set frequency: 4 MHz scale (max 28 MHz) */
169 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */
170 else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */
171 else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */
172 else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
173 else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
174 else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
175 else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
176 else rd[7].val = 0x0a; /* +28 MHz */
177
178 /* 0b - changes every 2/2 MHz */
179 if (mod2 < 2000000) rd[8].val = 0x45;
180 else rd[8].val = 0x44;
181
182 /* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
183 tmpval = 0x78; /* byte, overflows intentionally */
184 rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
185
186 /* 11 */
187 rd[13].val = 0xfd; /* TODO: correct value calculation */
188
189 /* 12 */
190 rd[14].val = 0x91; /* TODO: correct value calculation */
191
192 /* 22 */
193 if (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
194 else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
195 else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
196 else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
197 else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
198 else rd[15].val = 0xd0;
199
200 /* 05 */
201 rd[35].val = (reg05 & 0xf0);
202
203 /* 1f */
204 if (mod1 < 8000000) tmpval = 0x00;
205 else if (mod1 < 12000000) tmpval = 0x01;
206 else if (mod1 < 16000000) tmpval = 0x02;
207 else if (mod1 < 24000000) tmpval = 0x03;
208 else if (mod1 < 28000000) tmpval = 0x04;
209 else tmpval = 0x05;
210 rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
211
212 /* 20 */
213 if (mod1 < 8000000) tmpval = 0x00;
214 else if (mod1 < 12000000) tmpval = 0x01;
215 else if (mod1 < 20000000) tmpval = 0x02;
216 else if (mod1 < 24000000) tmpval = 0x03;
217 else if (mod1 < 28000000) tmpval = 0x04;
218 else tmpval = 0x05;
219 rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
220
221 /* 25 */
222 rd[43].val = priv->reg25_init_val;
223
224 /* 00 */
225 rd[45].val = 0x92; /* TODO: correct value calculation */
226
227 dprintk("freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x 1a:%02x 11:%02x " \
228 "12:%02x 22:%02x 05:%02x 1f:%02x 20:%02x 25:%02x 00:%02x", \
229 freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, rd[8].val, \
230 rd[10].val, rd[13].val, rd[14].val, rd[15].val, rd[35].val, \
231 rd[40].val, rd[41].val, rd[43].val, rd[45].val);
232
233 for (i = 0; i < sizeof(rd) / sizeof(*rd); i++) {
234 if (rd[i].oper == QT1010_WR) {
235 err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
236 } else { /* read is required to proper locking */
237 err = qt1010_readreg(priv, rd[i].reg, &tmpval);
238 }
239 if (err) return err;
240 }
241
242 if (debug)
243 qt1010_dump_regs(priv);
244
245 return 0;
246}
247
248static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
249{
250 u8 i, val1, val2;
251 int err;
252
253 qt1010_i2c_oper_t i2c_data[] = {
254 { QT1010_WR, reg, reg_init_val },
255 { QT1010_WR, 0x1e, 0x00 },
256 { QT1010_WR, 0x1e, oper },
257 { QT1010_RD, reg, 0xff }
258 };
259
260 for (i = 0; i < sizeof(i2c_data) / sizeof(*i2c_data); i++) {
261 if (i2c_data[i].oper == QT1010_WR) {
262 err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val);
263 } else {
264 err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
265 }
266 if (err) return err;
267 }
268
269 do {
270 val1 = val2;
271 err = qt1010_readreg(priv, reg, &val2);
272 if (err) return err;
273 dprintk("compare reg:%02x %02x %02x", reg, val1, val2);
274 } while (val1 != val2);
275 *retval = val1;
276
277 return qt1010_writereg(priv, 0x1e, 0x00);
278}
279
280
281static u8 qt1010_init_meas2(struct qt1010_priv *priv, u8 reg_init_val, u8 *retval)
282{
283 u8 i, val;
284 int err;
285 qt1010_i2c_oper_t i2c_data[] = {
286 { QT1010_WR, 0x07, reg_init_val },
287 { QT1010_WR, 0x22, 0xd0 },
288 { QT1010_WR, 0x1e, 0x00 },
289 { QT1010_WR, 0x1e, 0xd0 },
290 { QT1010_RD, 0x22, 0xff },
291 { QT1010_WR, 0x1e, 0x00 },
292 { QT1010_WR, 0x22, 0xff }
293 };
294 for (i = 0; i < sizeof(i2c_data) / sizeof(*i2c_data); i++) {
295 if (i2c_data[i].oper == QT1010_WR) {
296 err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val);
297 } else {
298 err = qt1010_readreg(priv, i2c_data[i].reg, &val);
299 }
300 if (err) return err;
301 }
302 *retval = val;
303 return 0;
304}
305
306static int qt1010_init(struct dvb_frontend *fe)
307{
308 struct qt1010_priv *priv = fe->tuner_priv;
309 struct dvb_frontend_parameters params;
310 int err;
311 u8 i, tmpval, *valptr = NULL;
312
313 qt1010_i2c_oper_t i2c_data[] = {
314 { QT1010_WR, 0x01, 0x80 },
315 { QT1010_WR, 0x0d, 0x84 },
316 { QT1010_WR, 0x0e, 0xb7 },
317 { QT1010_WR, 0x2a, 0x23 },
318 { QT1010_WR, 0x2c, 0xdc },
319 { QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
320 { QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
321 { QT1010_WR, 0x2b, 0x70 },
322 { QT1010_WR, 0x2a, 0x23 },
323 { QT1010_M1, 0x26, 0x08 },
324 { QT1010_M1, 0x82, 0xff },
325 { QT1010_WR, 0x05, 0x14 },
326 { QT1010_WR, 0x06, 0x44 },
327 { QT1010_WR, 0x07, 0x28 },
328 { QT1010_WR, 0x08, 0x0b },
329 { QT1010_WR, 0x11, 0xfd },
330 { QT1010_M1, 0x22, 0x0d },
331 { QT1010_M1, 0xd0, 0xff },
332 { QT1010_WR, 0x06, 0x40 },
333 { QT1010_WR, 0x16, 0xf0 },
334 { QT1010_WR, 0x02, 0x38 },
335 { QT1010_WR, 0x03, 0x18 },
336 { QT1010_WR, 0x20, 0xe0 },
337 { QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
338 { QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
339 { QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
340 { QT1010_WR, 0x03, 0x19 },
341 { QT1010_WR, 0x02, 0x3f },
342 { QT1010_WR, 0x21, 0x53 },
343 { QT1010_RD, 0x21, 0xff },
344 { QT1010_WR, 0x11, 0xfd },
345 { QT1010_WR, 0x05, 0x34 },
346 { QT1010_WR, 0x06, 0x44 },
347 { QT1010_WR, 0x08, 0x08 }
348 };
349
350 for (i = 0; i < sizeof(i2c_data) / sizeof(*i2c_data); i++) {
351 switch (i2c_data[i].oper) {
352 case QT1010_WR:
353 err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val);
354 break;
355 case QT1010_RD:
356 if (i2c_data[i].val == 0x20) valptr = &priv->reg20_init_val;
357 else valptr = &tmpval;
358 err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
359 break;
360 case QT1010_M1:
361 if (i2c_data[i].val == 0x25) valptr = &priv->reg25_init_val;
362 else if (i2c_data[i].val == 0x1f) valptr = &priv->reg1f_init_val;
363 else valptr = &tmpval;
364 err = qt1010_init_meas1(priv, i2c_data[i+1].reg, i2c_data[i].reg,
365 i2c_data[i].val, valptr);
366 i++;
367 break;
368 }
369 if (err) return err;
370 }
371
372 for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
373 if ((err = qt1010_init_meas2(priv, i, &tmpval)))
374 return err;
375
376 params.frequency = 545000000; /* Sigmatek DVB-110 545000000 */
377 /* MSI Megasky 580 GL861 533000000 */
378 return qt1010_set_params(fe, &params);
379}
380
381static int qt1010_release(struct dvb_frontend *fe)
382{
383 kfree(fe->tuner_priv);
384 fe->tuner_priv = NULL;
385 return 0;
386}
387
388static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
389{
390 struct qt1010_priv *priv = fe->tuner_priv;
391 *frequency = priv->frequency;
392 return 0;
393}
394
395static int qt1010_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
396{
397 struct qt1010_priv *priv = fe->tuner_priv;
398 *bandwidth = priv->bandwidth;
399 return 0;
400}
401
402static const struct dvb_tuner_ops qt1010_tuner_ops = {
403 .info = {
404 .name = "Quantek QT1010",
405 .frequency_min = QT1010_MIN_FREQ,
406 .frequency_max = QT1010_MAX_FREQ,
407 .frequency_step = QT1010_STEP,
408 },
409
410 .release = qt1010_release,
411 .init = qt1010_init,
412 /* TODO: implement sleep */
413
414 .set_params = qt1010_set_params,
415 .get_frequency = qt1010_get_frequency,
416 .get_bandwidth = qt1010_get_bandwidth
417};
418
419struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
420 struct i2c_adapter *i2c,
421 struct qt1010_config *cfg)
422{
423 struct qt1010_priv *priv = NULL;
424 u8 id;
425
426 priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
427 if (priv == NULL)
428 return NULL;
429
430 priv->cfg = cfg;
431 priv->i2c = i2c;
432
433
434 /* Try to detect tuner chip. Probably this is not correct register. */
435 if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
436 kfree(priv);
437 return NULL;
438 }
439
440 printk(KERN_INFO "Quantek QT1010 successfully identified.\n");
441 memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops, sizeof(struct dvb_tuner_ops));
442
443 fe->tuner_priv = priv;
444 return fe;
445}
446EXPORT_SYMBOL(qt1010_attach);
447
448MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
449MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
450MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
451MODULE_VERSION("0.1");
452MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 22:52:42 -0500