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authorMatthias Schwarzott <zzam@gentoo.org>2007-12-24 05:12:55 -0500
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-01-25 16:04:18 -0500
commit994fc28b6cd087cf6ef8d3ebd4eeef97c8194e4e (patch)
treee0ba2204f931b274a75a56ec88f5b23be2cf9400 /drivers/media/dvb/frontends/mt312.c
parent478f42292df86a618afbe3c22d11cf08c036d413 (diff)
V4L/DVB (6903): mt312: CodingStyle fix
Fixes all occurences of assignment in if checkpatch marks them as ERROR. Signed-off-by: Matthias Schwarzott <zzam@gentoo.org> Reviewed-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends/mt312.c')
-rw-r--r--drivers/media/dvb/frontends/mt312.c134
1 files changed, 83 insertions, 51 deletions
diff --git a/drivers/media/dvb/frontends/mt312.c b/drivers/media/dvb/frontends/mt312.c
index 2d68fafc0ef8..1638301fbd6e 100644
--- a/drivers/media/dvb/frontends/mt312.c
+++ b/drivers/media/dvb/frontends/mt312.c
@@ -152,7 +152,8 @@ static int mt312_get_inversion(struct mt312_state *state,
152 int ret; 152 int ret;
153 u8 vit_mode; 153 u8 vit_mode;
154 154
155 if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0) 155 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
156 if (ret < 0)
156 return ret; 157 return ret;
157 158
158 if (vit_mode & 0x80) /* auto inversion was used */ 159 if (vit_mode & 0x80) /* auto inversion was used */
@@ -170,15 +171,18 @@ static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
170 u16 monitor; 171 u16 monitor;
171 u8 buf[2]; 172 u8 buf[2];
172 173
173 if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0) 174 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
175 if (ret < 0)
174 return ret; 176 return ret;
175 177
176 if (sym_rate_h & 0x80) { 178 if (sym_rate_h & 0x80) {
177 /* symbol rate search was used */ 179 /* symbol rate search was used */
178 if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0) 180 ret = mt312_writereg(state, MON_CTRL, 0x03);
181 if (ret < 0)
179 return ret; 182 return ret;
180 183
181 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0) 184 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
185 if (ret < 0)
182 return ret; 186 return ret;
183 187
184 monitor = (buf[0] << 8) | buf[1]; 188 monitor = (buf[0] << 8) | buf[1];
@@ -186,16 +190,18 @@ static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
186 dprintk("sr(auto) = %u\n", 190 dprintk("sr(auto) = %u\n",
187 mt312_div(monitor * 15625, 4)); 191 mt312_div(monitor * 15625, 4));
188 } else { 192 } else {
189 if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0) 193 ret = mt312_writereg(state, MON_CTRL, 0x05);
194 if (ret < 0)
190 return ret; 195 return ret;
191 196
192 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0) 197 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
198 if (ret < 0)
193 return ret; 199 return ret;
194 200
195 dec_ratio = ((buf[0] >> 5) & 0x07) * 32; 201 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
196 202
197 if ((ret = mt312_read(state, SYM_RAT_OP_H, buf, 203 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
198 sizeof(buf))) < 0) 204 if (ret < 0)
199 return ret; 205 return ret;
200 206
201 sym_rat_op = (buf[0] << 8) | buf[1]; 207 sym_rat_op = (buf[0] << 8) | buf[1];
@@ -219,7 +225,8 @@ static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr)
219 int ret; 225 int ret;
220 u8 fec_status; 226 u8 fec_status;
221 227
222 if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0) 228 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
229 if (ret < 0)
223 return ret; 230 return ret;
224 231
225 *cr = fec_tab[(fec_status >> 4) & 0x07]; 232 *cr = fec_tab[(fec_status >> 4) & 0x07];
@@ -234,15 +241,17 @@ static int mt312_initfe(struct dvb_frontend *fe)
234 u8 buf[2]; 241 u8 buf[2];
235 242
236 /* wake up */ 243 /* wake up */
237 if ((ret = mt312_writereg(state, CONFIG, 244 ret = mt312_writereg(state, CONFIG,
238 (state->frequency == 60 ? 0x88 : 0x8c))) < 0) 245 (state->frequency == 60 ? 0x88 : 0x8c));
246 if (ret < 0)
239 return ret; 247 return ret;
240 248
241 /* wait at least 150 usec */ 249 /* wait at least 150 usec */
242 udelay(150); 250 udelay(150);
243 251
244 /* full reset */ 252 /* full reset */
245 if ((ret = mt312_reset(state, 1)) < 0) 253 ret = mt312_reset(state, 1);
254 if (ret < 0)
246 return ret; 255 return ret;
247 256
248/* Per datasheet, write correct values. 09/28/03 ACCJr. 257/* Per datasheet, write correct values. 09/28/03 ACCJr.
@@ -251,8 +260,8 @@ static int mt312_initfe(struct dvb_frontend *fe)
251 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02, 260 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
252 0x01, 0x00, 0x00, 0x00 }; 261 0x01, 0x00, 0x00, 0x00 };
253 262
254 if ((ret = mt312_write(state, VIT_SETUP, buf_def, 263 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
255 sizeof(buf_def))) < 0) 264 if (ret < 0)
256 return ret; 265 return ret;
257 } 266 }
258 267
@@ -263,23 +272,28 @@ static int mt312_initfe(struct dvb_frontend *fe)
263 /* DISEQC_RATIO */ 272 /* DISEQC_RATIO */
264 buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4); 273 buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
265 274
266 if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0) 275 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
276 if (ret < 0)
267 return ret; 277 return ret;
268 278
269 if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0) 279 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
280 if (ret < 0)
270 return ret; 281 return ret;
271 282
272 if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0) 283 ret = mt312_writereg(state, OP_CTRL, 0x53);
284 if (ret < 0)
273 return ret; 285 return ret;
274 286
275 /* TS_SW_LIM */ 287 /* TS_SW_LIM */
276 buf[0] = 0x8c; 288 buf[0] = 0x8c;
277 buf[1] = 0x98; 289 buf[1] = 0x98;
278 290
279 if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0) 291 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
292 if (ret < 0)
280 return ret; 293 return ret;
281 294
282 if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0) 295 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
296 if (ret < 0)
283 return ret; 297 return ret;
284 298
285 return 0; 299 return 0;
@@ -295,24 +309,26 @@ static int mt312_send_master_cmd(struct dvb_frontend *fe,
295 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg))) 309 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
296 return -EINVAL; 310 return -EINVAL;
297 311
298 if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0) 312 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
313 if (ret < 0)
299 return ret; 314 return ret;
300 315
301 if ((ret = 316 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
302 mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0) 317 if (ret < 0)
303 return ret; 318 return ret;
304 319
305 if ((ret = 320 ret = mt312_writereg(state, DISEQC_MODE,
306 mt312_writereg(state, DISEQC_MODE, 321 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
307 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3) 322 | 0x04);
308 | 0x04)) < 0) 323 if (ret < 0)
309 return ret; 324 return ret;
310 325
311 /* set DISEQC_MODE[2:0] to zero if a return message is expected */ 326 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
312 if (c->msg[0] & 0x02) 327 if (c->msg[0] & 0x02) {
313 if ((ret = mt312_writereg(state, DISEQC_MODE, 328 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
314 (diseqc_mode & 0x40))) < 0) 329 if (ret < 0)
315 return ret; 330 return ret;
331 }
316 332
317 return 0; 333 return 0;
318} 334}
@@ -328,12 +344,13 @@ static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c)
328 if (c > SEC_MINI_B) 344 if (c > SEC_MINI_B)
329 return -EINVAL; 345 return -EINVAL;
330 346
331 if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0) 347 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
348 if (ret < 0)
332 return ret; 349 return ret;
333 350
334 if ((ret = 351 ret = mt312_writereg(state, DISEQC_MODE,
335 mt312_writereg(state, DISEQC_MODE, 352 (diseqc_mode & 0x40) | mini_tab[c]);
336 (diseqc_mode & 0x40) | mini_tab[c])) < 0) 353 if (ret < 0)
337 return ret; 354 return ret;
338 355
339 return 0; 356 return 0;
@@ -350,12 +367,13 @@ static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t)
350 if (t > SEC_TONE_OFF) 367 if (t > SEC_TONE_OFF)
351 return -EINVAL; 368 return -EINVAL;
352 369
353 if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0) 370 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
371 if (ret < 0)
354 return ret; 372 return ret;
355 373
356 if ((ret = 374 ret = mt312_writereg(state, DISEQC_MODE,
357 mt312_writereg(state, DISEQC_MODE, 375 (diseqc_mode & 0x40) | tone_tab[t]);
358 (diseqc_mode & 0x40) | tone_tab[t])) < 0) 376 if (ret < 0)
359 return ret; 377 return ret;
360 378
361 return 0; 379 return 0;
@@ -380,7 +398,8 @@ static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s)
380 398
381 *s = 0; 399 *s = 0;
382 400
383 if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0) 401 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
402 if (ret < 0)
384 return ret; 403 return ret;
385 404
386 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x," 405 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
@@ -406,7 +425,8 @@ static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
406 int ret; 425 int ret;
407 u8 buf[3]; 426 u8 buf[3];
408 427
409 if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0) 428 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
429 if (ret < 0)
410 return ret; 430 return ret;
411 431
412 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64; 432 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
@@ -423,7 +443,8 @@ static int mt312_read_signal_strength(struct dvb_frontend *fe,
423 u16 agc; 443 u16 agc;
424 s16 err_db; 444 s16 err_db;
425 445
426 if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0) 446 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
447 if (ret < 0)
427 return ret; 448 return ret;
428 449
429 agc = (buf[0] << 6) | (buf[1] >> 2); 450 agc = (buf[0] << 6) | (buf[1] >> 2);
@@ -442,7 +463,8 @@ static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
442 int ret; 463 int ret;
443 u8 buf[2]; 464 u8 buf[2];
444 465
445 if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0) 466 ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf));
467 if (ret < 0)
446 return ret; 468 return ret;
447 469
448 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1); 470 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
@@ -456,7 +478,8 @@ static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
456 int ret; 478 int ret;
457 u8 buf[2]; 479 u8 buf[2];
458 480
459 if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0) 481 ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf));
482 if (ret < 0)
460 return ret; 483 return ret;
461 484
462 *ubc = (buf[0] << 8) | buf[1]; 485 *ubc = (buf[0] << 8) | buf[1];
@@ -512,14 +535,16 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
512 if ((config_val & 0x0c) == 0x08) { 535 if ((config_val & 0x0c) == 0x08) {
513 /* We are running 60MHz */ 536 /* We are running 60MHz */
514 state->frequency = 90; 537 state->frequency = 90;
515 if ((ret = mt312_initfe(fe)) < 0) 538 ret = mt312_initfe(fe);
539 if (ret < 0)
516 return ret; 540 return ret;
517 } 541 }
518 } else { 542 } else {
519 if ((config_val & 0x0c) == 0x0C) { 543 if ((config_val & 0x0c) == 0x0C) {
520 /* We are running 90MHz */ 544 /* We are running 90MHz */
521 state->frequency = 60; 545 state->frequency = 60;
522 if ((ret = mt312_initfe(fe)) < 0) 546 ret = mt312_initfe(fe);
547 if (ret < 0)
523 return ret; 548 return ret;
524 } 549 }
525 } 550 }
@@ -557,7 +582,8 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
557 /* GO */ 582 /* GO */
558 buf[4] = 0x01; 583 buf[4] = 0x01;
559 584
560 if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0) 585 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
586 if (ret < 0)
561 return ret; 587 return ret;
562 588
563 mt312_reset(state, 0); 589 mt312_reset(state, 0);
@@ -571,13 +597,16 @@ static int mt312_get_frontend(struct dvb_frontend *fe,
571 struct mt312_state *state = fe->demodulator_priv; 597 struct mt312_state *state = fe->demodulator_priv;
572 int ret; 598 int ret;
573 599
574 if ((ret = mt312_get_inversion(state, &p->inversion)) < 0) 600 ret = mt312_get_inversion(state, &p->inversion);
601 if (ret < 0)
575 return ret; 602 return ret;
576 603
577 if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0) 604 ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate);
605 if (ret < 0)
578 return ret; 606 return ret;
579 607
580 if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0) 608 ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner);
609 if (ret < 0)
581 return ret; 610 return ret;
582 611
583 return 0; 612 return 0;
@@ -601,14 +630,17 @@ static int mt312_sleep(struct dvb_frontend *fe)
601 u8 config; 630 u8 config;
602 631
603 /* reset all registers to defaults */ 632 /* reset all registers to defaults */
604 if ((ret = mt312_reset(state, 1)) < 0) 633 ret = mt312_reset(state, 1);
634 if (ret < 0)
605 return ret; 635 return ret;
606 636
607 if ((ret = mt312_readreg(state, CONFIG, &config)) < 0) 637 ret = mt312_readreg(state, CONFIG, &config);
638 if (ret < 0)
608 return ret; 639 return ret;
609 640
610 /* enter standby */ 641 /* enter standby */
611 if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0) 642 ret = mt312_writereg(state, CONFIG, config & 0x7f);
643 if (ret < 0)
612 return ret; 644 return ret;
613 645
614 return 0; 646 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 21:51:07 -0500