diff options
author | Patrick Boettcher <pb@linuxtv.org> | 2006-07-29 16:33:44 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2006-09-26 10:53:46 -0400 |
commit | 42afd061700edb43bb082bc65a2ddde431151d6b (patch) | |
tree | b8d6331b47c158f29c8271e6d8e58a256937f35a /drivers/media/dvb/frontends/dibx000_common.h | |
parent | b7571f8d7e12cd70048331e6a0199a42dc995d99 (diff) |
V4L/DVB (4461): Added missing dibx000-common code and headers
The first commit omitted the common-code and header-files.
Signed-off-by: Patrick Boettcher <pb@linuxtv.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends/dibx000_common.h')
-rw-r--r-- | drivers/media/dvb/frontends/dibx000_common.h | 166 |
1 files changed, 166 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h new file mode 100644 index 000000000000..bb0c65f8aee8 --- /dev/null +++ b/drivers/media/dvb/frontends/dibx000_common.h | |||
@@ -0,0 +1,166 @@ | |||
1 | #ifndef DIBX000_COMMON_H | ||
2 | #define DIBX000_COMMON_H | ||
3 | |||
4 | enum dibx000_i2c_interface { | ||
5 | DIBX000_I2C_INTERFACE_TUNER = 0, | ||
6 | DIBX000_I2C_INTERFACE_GPIO_1_2 = 1, | ||
7 | DIBX000_I2C_INTERFACE_GPIO_3_4 = 2 | ||
8 | }; | ||
9 | |||
10 | struct dibx000_i2c_master { | ||
11 | #define DIB3000MC 1 | ||
12 | #define DIB7000 2 | ||
13 | #define DIB7000P 11 | ||
14 | #define DIB7000MC 12 | ||
15 | u16 device_rev; | ||
16 | |||
17 | enum dibx000_i2c_interface selected_interface; | ||
18 | |||
19 | // struct i2c_adapter tuner_i2c_adap; | ||
20 | struct i2c_adapter gated_tuner_i2c_adap; | ||
21 | |||
22 | struct i2c_adapter *i2c_adap; | ||
23 | u8 i2c_addr; | ||
24 | |||
25 | u16 base_reg; | ||
26 | }; | ||
27 | |||
28 | extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, struct i2c_adapter *i2c_adap, u8 i2c_addr); | ||
29 | extern struct i2c_adapter * dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, enum dibx000_i2c_interface intf, int gating); | ||
30 | extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); | ||
31 | |||
32 | #define BAND_LBAND 0x01 | ||
33 | #define BAND_UHF 0x02 | ||
34 | #define BAND_VHF 0x04 | ||
35 | |||
36 | struct dibx000_agc_config { | ||
37 | /* defines the capabilities of this AGC-setting - using the BAND_-defines*/ | ||
38 | u8 band_caps; | ||
39 | |||
40 | u16 setup; | ||
41 | |||
42 | u16 inv_gain; | ||
43 | u16 time_stabiliz; | ||
44 | |||
45 | u8 alpha_level; | ||
46 | u16 thlock; | ||
47 | |||
48 | u8 wbd_inv; | ||
49 | u16 wbd_ref; | ||
50 | u8 wbd_sel; | ||
51 | u8 wbd_alpha; | ||
52 | |||
53 | u16 agc1_max; | ||
54 | u16 agc1_min; | ||
55 | u16 agc2_max; | ||
56 | u16 agc2_min; | ||
57 | |||
58 | u8 agc1_pt1; | ||
59 | u8 agc1_pt2; | ||
60 | u8 agc1_pt3; | ||
61 | |||
62 | u8 agc1_slope1; | ||
63 | u8 agc1_slope2; | ||
64 | |||
65 | u8 agc2_pt1; | ||
66 | u8 agc2_pt2; | ||
67 | |||
68 | u8 agc2_slope1; | ||
69 | u8 agc2_slope2; | ||
70 | |||
71 | u8 alpha_mant; | ||
72 | u8 alpha_exp; | ||
73 | |||
74 | u8 beta_mant; | ||
75 | u8 beta_exp; | ||
76 | |||
77 | u8 perform_agc_softsplit; | ||
78 | |||
79 | struct { | ||
80 | u16 min; | ||
81 | u16 max; | ||
82 | u16 min_thres; | ||
83 | u16 max_thres; | ||
84 | } split; | ||
85 | }; | ||
86 | |||
87 | struct dibx000_bandwidth_config { | ||
88 | u32 internal; | ||
89 | u32 sampling; | ||
90 | |||
91 | u8 pll_prediv; | ||
92 | u8 pll_ratio; | ||
93 | u8 pll_range; | ||
94 | u8 pll_reset; | ||
95 | u8 pll_bypass; | ||
96 | |||
97 | u8 enable_refdiv; | ||
98 | u8 bypclk_div; | ||
99 | u8 IO_CLK_en_core; | ||
100 | u8 ADClkSrc; | ||
101 | u8 modulo; | ||
102 | |||
103 | u16 sad_cfg; | ||
104 | |||
105 | u32 ifreq; | ||
106 | u32 timf; | ||
107 | }; | ||
108 | |||
109 | enum dibx000_adc_states { | ||
110 | DIBX000_SLOW_ADC_ON = 0, | ||
111 | DIBX000_SLOW_ADC_OFF, | ||
112 | DIBX000_ADC_ON, | ||
113 | DIBX000_ADC_OFF, | ||
114 | DIBX000_VBG_ENABLE, | ||
115 | DIBX000_VBG_DISABLE, | ||
116 | }; | ||
117 | |||
118 | #define BW_INDEX_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \ | ||
119 | (v) == BANDWIDTH_7_MHZ ? 7000 : \ | ||
120 | (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 ) | ||
121 | |||
122 | /* Chip output mode. */ | ||
123 | #define OUTMODE_HIGH_Z 0 | ||
124 | #define OUTMODE_MPEG2_PAR_GATED_CLK 1 | ||
125 | #define OUTMODE_MPEG2_PAR_CONT_CLK 2 | ||
126 | #define OUTMODE_MPEG2_SERIAL 7 | ||
127 | #define OUTMODE_DIVERSITY 4 | ||
128 | #define OUTMODE_MPEG2_FIFO 5 | ||
129 | |||
130 | /* I hope I can get rid of the following kludge in the near future */ | ||
131 | struct dibx000_ofdm_channel { | ||
132 | u8 Bw; | ||
133 | s16 nfft; | ||
134 | s16 guard; | ||
135 | s16 nqam; | ||
136 | s16 vit_hrch; | ||
137 | s16 vit_select_hp; | ||
138 | s16 vit_alpha; | ||
139 | s16 vit_code_rate_hp; | ||
140 | s16 vit_code_rate_lp; | ||
141 | }; | ||
142 | |||
143 | #define FEP2DIB(fep,ch) \ | ||
144 | (ch)->Bw = (fep)->u.ofdm.bandwidth; \ | ||
145 | (ch)->nfft = (fep)->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ? -1 : (fep)->u.ofdm.transmission_mode; \ | ||
146 | (ch)->guard = (fep)->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ? -1 : (fep)->u.ofdm.guard_interval; \ | ||
147 | (ch)->nqam = (fep)->u.ofdm.constellation == QAM_AUTO ? -1 : (fep)->u.ofdm.constellation == QAM_64 ? 2 : (fep)->u.ofdm.constellation; \ | ||
148 | (ch)->vit_hrch = 0; /* linux-dvb is not prepared for HIERARCHICAL TRANSMISSION */ \ | ||
149 | (ch)->vit_select_hp = 1; \ | ||
150 | (ch)->vit_alpha = 1; \ | ||
151 | (ch)->vit_code_rate_hp = (fep)->u.ofdm.code_rate_HP == FEC_AUTO ? -1 : (fep)->u.ofdm.code_rate_HP; \ | ||
152 | (ch)->vit_code_rate_lp = (fep)->u.ofdm.code_rate_LP == FEC_AUTO ? -1 : (fep)->u.ofdm.code_rate_LP; | ||
153 | |||
154 | #define INIT_OFDM_CHANNEL(ch) do {\ | ||
155 | (ch)->Bw = 0; \ | ||
156 | (ch)->nfft = -1; \ | ||
157 | (ch)->guard = -1; \ | ||
158 | (ch)->nqam = -1; \ | ||
159 | (ch)->vit_hrch = -1; \ | ||
160 | (ch)->vit_select_hp = -1; \ | ||
161 | (ch)->vit_alpha = -1; \ | ||
162 | (ch)->vit_code_rate_hp = -1; \ | ||
163 | (ch)->vit_code_rate_lp = -1; \ | ||
164 | } while (0) | ||
165 | |||
166 | #endif | ||