diff options
author | Olivier Grenie <Olivier.Grenie@dibcom.fr> | 2009-12-07 05:49:40 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2009-12-15 21:18:16 -0500 |
commit | 9c78303681278b983fac3c6c3c0aa3f93cf2ffa8 (patch) | |
tree | 1407987d9fa1d4234c46fcab6d22da1997e303a2 /drivers/media/dvb/frontends/dib0070.c | |
parent | 03245a5ee69a5faa99b020fe1aca9bafe10c46a9 (diff) |
V4L/DVB (13584): DiBXXX0: fix most of the Codingstyle violations from the previous patch
This patch changes most of the Codingstyle violations which were
introduced by the previous patch. Line length less that 80 chars are
not corrected.
Signed-off-by: Olivier Grenie <Olivier.Grenie@dibcom.fr>
Signed-off-by: Patrick Boettcher <pboettcher@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends/dib0070.c')
-rw-r--r-- | drivers/media/dvb/frontends/dib0070.c | 226 |
1 files changed, 114 insertions, 112 deletions
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c index 81860b2cfe98..0d12763603b4 100644 --- a/drivers/media/dvb/frontends/dib0070.c +++ b/drivers/media/dvb/frontends/dib0070.c | |||
@@ -163,7 +163,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state | |||
163 | 163 | ||
164 | adc = dib0070_read_reg(state, 0x19); | 164 | adc = dib0070_read_reg(state, 0x19); |
165 | 165 | ||
166 | dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024); | 166 | dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024); |
167 | 167 | ||
168 | if (adc >= 400) { | 168 | if (adc >= 400) { |
169 | adc -= 400; | 169 | adc -= 400; |
@@ -174,7 +174,7 @@ static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state | |||
174 | } | 174 | } |
175 | 175 | ||
176 | if (adc < state->adc_diff) { | 176 | if (adc < state->adc_diff) { |
177 | dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff); | 177 | dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)", state->captrim, adc, state->adc_diff); |
178 | state->adc_diff = adc; | 178 | state->adc_diff = adc; |
179 | state->fcaptrim = state->captrim; | 179 | state->fcaptrim = state->captrim; |
180 | 180 | ||
@@ -201,7 +201,7 @@ static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf | |||
201 | { | 201 | { |
202 | struct dib0070_state *state = fe->tuner_priv; | 202 | struct dib0070_state *state = fe->tuner_priv; |
203 | u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); | 203 | u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0); |
204 | dprintk( "CTRL_LO5: 0x%x", lo5); | 204 | dprintk("CTRL_LO5: 0x%x", lo5); |
205 | return dib0070_write_reg(state, 0x15, lo5); | 205 | return dib0070_write_reg(state, 0x15, lo5); |
206 | } | 206 | } |
207 | 207 | ||
@@ -215,10 +215,10 @@ void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open) | |||
215 | } else { | 215 | } else { |
216 | dib0070_write_reg(state, 0x1b, 0x4112); | 216 | dib0070_write_reg(state, 0x1b, 0x4112); |
217 | if (state->cfg->vga_filter != 0) { | 217 | if (state->cfg->vga_filter != 0) { |
218 | dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); | 218 | dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); |
219 | dprintk( "vga filter register is set to %x", state->cfg->vga_filter); | 219 | dprintk("vga filter register is set to %x", state->cfg->vga_filter); |
220 | } else | 220 | } else |
221 | dib0070_write_reg(state, 0x1a, 0x0009); | 221 | dib0070_write_reg(state, 0x1a, 0x0009); |
222 | } | 222 | } |
223 | } | 223 | } |
224 | 224 | ||
@@ -255,7 +255,7 @@ static const struct dib0070_tuning dib0070_tuning_table[] = { | |||
255 | { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 }, | 255 | { 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 }, |
256 | { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 }, | 256 | { 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 }, |
257 | { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */ | 257 | { 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */ |
258 | { 699999, 2, 0 ,1, 4, 2, 2, 0x4000 | 0x0800 }, | 258 | { 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 }, |
259 | { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 }, | 259 | { 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 }, |
260 | { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */ | 260 | { 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */ |
261 | }; | 261 | }; |
@@ -291,7 +291,7 @@ static const struct dib0070_lna_match dib0070_lna[] = { | |||
291 | { 0xffffffff, 7 }, | 291 | { 0xffffffff, 7 }, |
292 | }; | 292 | }; |
293 | 293 | ||
294 | #define LPF 100 // define for the loop filter 100kHz by default 16-07-06 | 294 | #define LPF 100 |
295 | static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) | 295 | static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch) |
296 | { | 296 | { |
297 | struct dib0070_state *state = fe->tuner_priv; | 297 | struct dib0070_state *state = fe->tuner_priv; |
@@ -313,7 +313,7 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par | |||
313 | && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2))) | 313 | && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2))) |
314 | || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) | 314 | || (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0) |
315 | && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))) | 315 | && (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))) |
316 | freq += 850; | 316 | freq += 850; |
317 | #endif | 317 | #endif |
318 | if (state->current_rf != freq) { | 318 | if (state->current_rf != freq) { |
319 | 319 | ||
@@ -340,95 +340,95 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par | |||
340 | } | 340 | } |
341 | 341 | ||
342 | if (*tune_state == CT_TUNER_START) { | 342 | if (*tune_state == CT_TUNER_START) { |
343 | dprintk( "Tuning for Band: %hd (%d kHz)", band, freq); | 343 | dprintk("Tuning for Band: %hd (%d kHz)", band, freq); |
344 | if (state->current_rf != freq) { | 344 | if (state->current_rf != freq) { |
345 | u8 REFDIV; | 345 | u8 REFDIV; |
346 | u32 FBDiv, Rest, FREF, VCOF_kHz; | 346 | u32 FBDiv, Rest, FREF, VCOF_kHz; |
347 | u8 Den; | 347 | u8 Den; |
348 | 348 | ||
349 | state->current_rf = freq; | 349 | state->current_rf = freq; |
350 | state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7); | 350 | state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7); |
351 | 351 | ||
352 | 352 | ||
353 | dib0070_write_reg(state, 0x17, 0x30); | 353 | dib0070_write_reg(state, 0x17, 0x30); |
354 | 354 | ||
355 | 355 | ||
356 | VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2; | 356 | VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2; |
357 | 357 | ||
358 | switch (band) { | 358 | switch (band) { |
359 | case BAND_VHF: | 359 | case BAND_VHF: |
360 | REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000); | 360 | REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000); |
361 | break; | 361 | break; |
362 | case BAND_FM: | 362 | case BAND_FM: |
363 | REFDIV = (u8) ((state->cfg->clock_khz) / 1000); | 363 | REFDIV = (u8) ((state->cfg->clock_khz) / 1000); |
364 | break; | 364 | break; |
365 | default: | 365 | default: |
366 | REFDIV = (u8) ( state->cfg->clock_khz / 10000); | 366 | REFDIV = (u8) (state->cfg->clock_khz / 10000); |
367 | break; | 367 | break; |
368 | } | 368 | } |
369 | FREF = state->cfg->clock_khz / REFDIV; | 369 | FREF = state->cfg->clock_khz / REFDIV; |
370 | 370 | ||
371 | 371 | ||
372 | 372 | ||
373 | switch (state->revision) { | 373 | switch (state->revision) { |
374 | case DIB0070S_P1A: | 374 | case DIB0070S_P1A: |
375 | FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF); | 375 | FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF); |
376 | Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF; | 376 | Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF; |
377 | break; | 377 | break; |
378 | 378 | ||
379 | case DIB0070_P1G: | 379 | case DIB0070_P1G: |
380 | case DIB0070_P1F: | 380 | case DIB0070_P1F: |
381 | default: | 381 | default: |
382 | FBDiv = (freq / (FREF / 2)); | 382 | FBDiv = (freq / (FREF / 2)); |
383 | Rest = 2 * freq - FBDiv * FREF; | 383 | Rest = 2 * freq - FBDiv * FREF; |
384 | break; | 384 | break; |
385 | } | 385 | } |
386 | 386 | ||
387 | if (Rest < LPF) | 387 | if (Rest < LPF) |
388 | Rest = 0; | 388 | Rest = 0; |
389 | else if (Rest < 2 * LPF) | 389 | else if (Rest < 2 * LPF) |
390 | Rest = 2 * LPF; | 390 | Rest = 2 * LPF; |
391 | else if (Rest > (FREF - LPF)) { | 391 | else if (Rest > (FREF - LPF)) { |
392 | Rest = 0; | 392 | Rest = 0; |
393 | FBDiv += 1; | 393 | FBDiv += 1; |
394 | } else if (Rest > (FREF - 2 * LPF)) | 394 | } else if (Rest > (FREF - 2 * LPF)) |
395 | Rest = FREF - 2 * LPF; | 395 | Rest = FREF - 2 * LPF; |
396 | Rest = (Rest * 6528) / (FREF / 10); | 396 | Rest = (Rest * 6528) / (FREF / 10); |
397 | 397 | ||
398 | Den = 1; | 398 | Den = 1; |
399 | if (Rest > 0) { | 399 | if (Rest > 0) { |
400 | state->lo4 |= (1 << 14) | (1 << 12); | 400 | state->lo4 |= (1 << 14) | (1 << 12); |
401 | Den = 255; | 401 | Den = 255; |
402 | } | 402 | } |
403 | 403 | ||
404 | 404 | ||
405 | dib0070_write_reg(state, 0x11, (u16)FBDiv); | 405 | dib0070_write_reg(state, 0x11, (u16)FBDiv); |
406 | dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); | 406 | dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); |
407 | dib0070_write_reg(state, 0x13, (u16) Rest); | 407 | dib0070_write_reg(state, 0x13, (u16) Rest); |
408 | 408 | ||
409 | if (state->revision == DIB0070S_P1A) { | 409 | if (state->revision == DIB0070S_P1A) { |
410 | 410 | ||
411 | if (band == BAND_SBAND) { | 411 | if (band == BAND_SBAND) { |
412 | dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); | 412 | dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0); |
413 | dib0070_write_reg(state, 0x1d,0xFFFF); | 413 | dib0070_write_reg(state, 0x1d, 0xFFFF); |
414 | } else | 414 | } else |
415 | dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1); | 415 | dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1); |
416 | } | 416 | } |
417 | 417 | ||
418 | dib0070_write_reg(state, 0x20, | 418 | dib0070_write_reg(state, 0x20, |
419 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable); | 419 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable); |
420 | 420 | ||
421 | dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF); | 421 | dprintk("REFDIV: %hd, FREF: %d", REFDIV, FREF); |
422 | dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest); | 422 | dprintk("FBDIV: %d, Rest: %d", FBDiv, Rest); |
423 | dprintk( "Num: %hd, Den: %hd, SD: %hd",(u16) Rest, Den, (state->lo4 >> 12) & 0x1); | 423 | dprintk("Num: %hd, Den: %hd, SD: %hd", (u16) Rest, Den, (state->lo4 >> 12) & 0x1); |
424 | dprintk( "HFDIV code: %hd", state->current_tune_table_index->hfdiv); | 424 | dprintk("HFDIV code: %hd", state->current_tune_table_index->hfdiv); |
425 | dprintk( "VCO = %hd", state->current_tune_table_index->vco_band); | 425 | dprintk("VCO = %hd", state->current_tune_table_index->vco_band); |
426 | dprintk( "VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq); | 426 | dprintk("VCOF: ((%hd*%d) << 1))", state->current_tune_table_index->vco_multi, freq); |
427 | 427 | ||
428 | *tune_state = CT_TUNER_STEP_0; | 428 | *tune_state = CT_TUNER_STEP_0; |
429 | } else { /* we are already tuned to this frequency - the configuration is correct */ | 429 | } else { /* we are already tuned to this frequency - the configuration is correct */ |
430 | ret = 50; /* wakeup time */ | 430 | ret = 50; /* wakeup time */ |
431 | *tune_state = CT_TUNER_STEP_5; | 431 | *tune_state = CT_TUNER_STEP_5; |
432 | } | 432 | } |
433 | } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) { | 433 | } else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) { |
434 | 434 | ||
@@ -437,13 +437,13 @@ static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_par | |||
437 | } else if (*tune_state == CT_TUNER_STEP_4) { | 437 | } else if (*tune_state == CT_TUNER_STEP_4) { |
438 | const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; | 438 | const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain; |
439 | if (tmp != NULL) { | 439 | if (tmp != NULL) { |
440 | while (freq/1000 > tmp->freq) /* find the right one */ | 440 | while (freq/1000 > tmp->freq) /* find the right one */ |
441 | tmp++; | 441 | tmp++; |
442 | dib0070_write_reg(state, 0x0f, | 442 | dib0070_write_reg(state, 0x0f, |
443 | (0 << 15) | (1 << 14) | (3 << 12) | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) | (state-> | 443 | (0 << 15) | (1 << 14) | (3 << 12) |
444 | current_tune_table_index-> | 444 | | (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7) |
445 | wbdmux << 0)); | 445 | | (state->current_tune_table_index->wbdmux << 0)); |
446 | state->wbd_gain_current = tmp->wbd_gain_val; | 446 | state->wbd_gain_current = tmp->wbd_gain_val; |
447 | } else { | 447 | } else { |
448 | dib0070_write_reg(state, 0x0f, | 448 | dib0070_write_reg(state, 0x0f, |
449 | (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index-> | 449 | (0 << 15) | (1 << 14) | (3 << 12) | (6 << 9) | (0 << 8) | (1 << 7) | (state->current_tune_table_index-> |
@@ -483,7 +483,7 @@ static int dib0070_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters | |||
483 | do { | 483 | do { |
484 | ret = dib0070_tune_digital(fe, p); | 484 | ret = dib0070_tune_digital(fe, p); |
485 | if (ret != FE_CALLBACK_TIME_NEVER) | 485 | if (ret != FE_CALLBACK_TIME_NEVER) |
486 | msleep(ret/10); | 486 | msleep(ret/10); |
487 | else | 487 | else |
488 | break; | 488 | break; |
489 | } while (state->tune_state != CT_TUNER_STOP); | 489 | } while (state->tune_state != CT_TUNER_STOP); |
@@ -512,18 +512,20 @@ u8 dib0070_get_rf_output(struct dvb_frontend *fe) | |||
512 | struct dib0070_state *state = fe->tuner_priv; | 512 | struct dib0070_state *state = fe->tuner_priv; |
513 | return (dib0070_read_reg(state, 0x07) >> 11) & 0x3; | 513 | return (dib0070_read_reg(state, 0x07) >> 11) & 0x3; |
514 | } | 514 | } |
515 | |||
516 | EXPORT_SYMBOL(dib0070_get_rf_output); | 515 | EXPORT_SYMBOL(dib0070_get_rf_output); |
516 | |||
517 | int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no) | 517 | int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no) |
518 | { | 518 | { |
519 | struct dib0070_state *state = fe->tuner_priv; | 519 | struct dib0070_state *state = fe->tuner_priv; |
520 | u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff; | 520 | u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff; |
521 | if (no > 3) no = 3; | 521 | if (no > 3) |
522 | if (no < 1) no = 1; | 522 | no = 3; |
523 | if (no < 1) | ||
524 | no = 1; | ||
523 | return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); | 525 | return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); |
524 | } | 526 | } |
525 | |||
526 | EXPORT_SYMBOL(dib0070_set_rf_output); | 527 | EXPORT_SYMBOL(dib0070_set_rf_output); |
528 | |||
527 | static const u16 dib0070_p1f_defaults[] = | 529 | static const u16 dib0070_p1f_defaults[] = |
528 | 530 | ||
529 | { | 531 | { |
@@ -582,7 +584,7 @@ static void dib0070_wbd_offset_calibration(struct dib0070_state *state) | |||
582 | u8 gain; | 584 | u8 gain; |
583 | for (gain = 6; gain < 8; gain++) { | 585 | for (gain = 6; gain < 8; gain++) { |
584 | state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); | 586 | state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2); |
585 | dprintk( "Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]); | 587 | dprintk("Gain: %d, WBDOffset (3.3V) = %hd", gain, state->wbd_offset_3_3[gain-6]); |
586 | } | 588 | } |
587 | } | 589 | } |
588 | 590 | ||
@@ -622,10 +624,10 @@ static int dib0070_reset(struct dvb_frontend *fe) | |||
622 | state->revision = DIB0070S_P1A; | 624 | state->revision = DIB0070S_P1A; |
623 | 625 | ||
624 | /* P1F or not */ | 626 | /* P1F or not */ |
625 | dprintk( "Revision: %x", state->revision); | 627 | dprintk("Revision: %x", state->revision); |
626 | 628 | ||
627 | if (state->revision == DIB0070_P1D) { | 629 | if (state->revision == DIB0070_P1D) { |
628 | dprintk( "Error: this driver is not to be used meant for P1D or earlier"); | 630 | dprintk("Error: this driver is not to be used meant for P1D or earlier"); |
629 | return -EINVAL; | 631 | return -EINVAL; |
630 | } | 632 | } |
631 | 633 | ||
@@ -702,7 +704,7 @@ static const struct dvb_tuner_ops dib0070_ops = { | |||
702 | // .get_bandwidth = dib0070_get_bandwidth | 704 | // .get_bandwidth = dib0070_get_bandwidth |
703 | }; | 705 | }; |
704 | 706 | ||
705 | struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) | 707 | struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg) |
706 | { | 708 | { |
707 | struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); | 709 | struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL); |
708 | if (state == NULL) | 710 | if (state == NULL) |