diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-09 16:03:58 -0500 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-09 16:03:58 -0500 |
commit | f17578decc40df8fceff82b106582e30bdfb3189 (patch) | |
tree | 911a435a2094ac03ae649f020237674224e4124a /drivers/media/dvb/frontends/cx24110.c | |
parent | 682e852e2638ed0aff84aa51181c9e5d2f939562 (diff) | |
parent | cec418346e5a411e907293aba7cc21ac53c95834 (diff) |
Merge master.kernel.org:/pub/scm/linux/kernel/git/mchehab/v4l-dvb
Diffstat (limited to 'drivers/media/dvb/frontends/cx24110.c')
-rw-r--r-- | drivers/media/dvb/frontends/cx24110.c | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c index 0c4db80ec332..d15d32c51dc5 100644 --- a/drivers/media/dvb/frontends/cx24110.c +++ b/drivers/media/dvb/frontends/cx24110.c | |||
@@ -27,7 +27,6 @@ | |||
27 | #include <linux/module.h> | 27 | #include <linux/module.h> |
28 | #include <linux/moduleparam.h> | 28 | #include <linux/moduleparam.h> |
29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
30 | #include <linux/jiffies.h> | ||
31 | 30 | ||
32 | #include "dvb_frontend.h" | 31 | #include "dvb_frontend.h" |
33 | #include "cx24110.h" | 32 | #include "cx24110.h" |
@@ -56,7 +55,7 @@ static int debug; | |||
56 | 55 | ||
57 | static struct {u8 reg; u8 data;} cx24110_regdata[]= | 56 | static struct {u8 reg; u8 data;} cx24110_regdata[]= |
58 | /* Comments beginning with @ denote this value should | 57 | /* Comments beginning with @ denote this value should |
59 | be the default */ | 58 | be the default */ |
60 | {{0x09,0x01}, /* SoftResetAll */ | 59 | {{0x09,0x01}, /* SoftResetAll */ |
61 | {0x09,0x00}, /* release reset */ | 60 | {0x09,0x00}, /* release reset */ |
62 | {0x01,0xe8}, /* MSB of code rate 27.5MS/s */ | 61 | {0x01,0xe8}, /* MSB of code rate 27.5MS/s */ |
@@ -67,26 +66,26 @@ static struct {u8 reg; u8 data;} cx24110_regdata[]= | |||
67 | {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */ | 66 | {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */ |
68 | {0x0a,0x00}, /* @ partial chip disables, do not set */ | 67 | {0x0a,0x00}, /* @ partial chip disables, do not set */ |
69 | {0x0b,0x01}, /* set output clock in gapped mode, start signal low | 68 | {0x0b,0x01}, /* set output clock in gapped mode, start signal low |
70 | active for first byte */ | 69 | active for first byte */ |
71 | {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */ | 70 | {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */ |
72 | {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */ | 71 | {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */ |
73 | {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1 | 72 | {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1 |
74 | to avoid starting the BER counter. Reset the | 73 | to avoid starting the BER counter. Reset the |
75 | CRC test bit. Finite counting selected */ | 74 | CRC test bit. Finite counting selected */ |
76 | {0x15,0xff}, /* @ size of the limited time window for RS BER | 75 | {0x15,0xff}, /* @ size of the limited time window for RS BER |
77 | estimation. It is <value>*256 RS blocks, this | 76 | estimation. It is <value>*256 RS blocks, this |
78 | gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */ | 77 | gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */ |
79 | {0x16,0x00}, /* @ enable all RS output ports */ | 78 | {0x16,0x00}, /* @ enable all RS output ports */ |
80 | {0x17,0x04}, /* @ time window allowed for the RS to sync */ | 79 | {0x17,0x04}, /* @ time window allowed for the RS to sync */ |
81 | {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned | 80 | {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned |
82 | for automatically */ | 81 | for automatically */ |
83 | /* leave the current code rate and normalization | 82 | /* leave the current code rate and normalization |
84 | registers as they are after reset... */ | 83 | registers as they are after reset... */ |
85 | {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting | 84 | {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting |
86 | only once */ | 85 | only once */ |
87 | {0x23,0x18}, /* @ size of the limited time window for Viterbi BER | 86 | {0x23,0x18}, /* @ size of the limited time window for Viterbi BER |
88 | estimation. It is <value>*65536 channel bits, i.e. | 87 | estimation. It is <value>*65536 channel bits, i.e. |
89 | approx. 38ms at 27.5MS/s, rate 3/4 */ | 88 | approx. 38ms at 27.5MS/s, rate 3/4 */ |
90 | {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */ | 89 | {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */ |
91 | /* leave front-end AGC parameters at default values */ | 90 | /* leave front-end AGC parameters at default values */ |
92 | /* leave decimation AGC parameters at default values */ | 91 | /* leave decimation AGC parameters at default values */ |