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authorSteven Toth <stoth@hauppauge.com>2008-05-01 18:35:54 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-05-14 01:56:39 -0400
commitd211017b954436bfc516e93d839e8746ec2bbbfe (patch)
tree59bd8a24f36992fc72e2b259f5657319ccda7082 /drivers/media/common
parent48937295a63b4e81db907605afcbd81e0464b00f (diff)
V4L/DVB(7872): mxl5005s: checkpatch.pl compliance
4 exceptions where the code would read very ugly otherwise. Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/common')
-rw-r--r--drivers/media/common/tuners/mxl5005s.c2496
-rw-r--r--drivers/media/common/tuners/mxl5005s.h4
2 files changed, 1029 insertions, 1471 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 45ac6a9e71a3..21dca5bdca77 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -86,34 +86,30 @@ static int debug = 2;
86#define MASTER_CONTROL_ADDR 9 86#define MASTER_CONTROL_ADDR 9
87 87
88/* Enumeration of Master Control Register State */ 88/* Enumeration of Master Control Register State */
89typedef enum 89enum master_control_state {
90{
91 MC_LOAD_START = 1, 90 MC_LOAD_START = 1,
92 MC_POWER_DOWN, 91 MC_POWER_DOWN,
93 MC_SYNTH_RESET, 92 MC_SYNTH_RESET,
94 MC_SEQ_OFF 93 MC_SEQ_OFF
95} Master_Control_State; 94};
96 95
97/* Enumeration of MXL5005 Tuner Modulation Type */ 96/* Enumeration of MXL5005 Tuner Modulation Type */
98typedef enum 97enum {
99{
100 MXL_DEFAULT_MODULATION = 0, 98 MXL_DEFAULT_MODULATION = 0,
101 MXL_DVBT, 99 MXL_DVBT,
102 MXL_ATSC, 100 MXL_ATSC,
103 MXL_QAM, 101 MXL_QAM,
104 MXL_ANALOG_CABLE, 102 MXL_ANALOG_CABLE,
105 MXL_ANALOG_OTA 103 MXL_ANALOG_OTA
106} Tuner_Modu_Type; 104} tuner_modu_type;
107 105
108/* MXL5005 Tuner Register Struct */ 106/* MXL5005 Tuner Register Struct */
109typedef struct _TunerReg_struct 107struct TunerReg {
110{
111 u16 Reg_Num; /* Tuner Register Address */ 108 u16 Reg_Num; /* Tuner Register Address */
112 u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ 109 u16 Reg_Val; /* Current sw programmed value waiting to be writen */
113} TunerReg_struct; 110};
114 111
115typedef enum 112enum {
116{
117 /* Initialization Control Names */ 113 /* Initialization Control Names */
118 DN_IQTN_AMP_CUT = 1, /* 1 */ 114 DN_IQTN_AMP_CUT = 1, /* 1 */
119 BB_MODE, /* 2 */ 115 BB_MODE, /* 2 */
@@ -219,16 +215,14 @@ typedef enum
219#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 215#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
220 216
221/* Standard modes */ 217/* Standard modes */
222enum 218enum {
223{
224 MXL5005S_STANDARD_DVBT, 219 MXL5005S_STANDARD_DVBT,
225 MXL5005S_STANDARD_ATSC, 220 MXL5005S_STANDARD_ATSC,
226}; 221};
227#define MXL5005S_STANDARD_MODE_NUM 2 222#define MXL5005S_STANDARD_MODE_NUM 2
228 223
229/* Bandwidth modes */ 224/* Bandwidth modes */
230enum 225enum {
231{
232 MXL5005S_BANDWIDTH_6MHZ = 6000000, 226 MXL5005S_BANDWIDTH_6MHZ = 6000000,
233 MXL5005S_BANDWIDTH_7MHZ = 7000000, 227 MXL5005S_BANDWIDTH_7MHZ = 7000000,
234 MXL5005S_BANDWIDTH_8MHZ = 8000000, 228 MXL5005S_BANDWIDTH_8MHZ = 8000000,
@@ -236,17 +230,16 @@ enum
236#define MXL5005S_BANDWIDTH_MODE_NUM 3 230#define MXL5005S_BANDWIDTH_MODE_NUM 3
237 231
238/* MXL5005 Tuner Control Struct */ 232/* MXL5005 Tuner Control Struct */
239typedef struct _TunerControl_struct { 233struct TunerControl {
240 u16 Ctrl_Num; /* Control Number */ 234 u16 Ctrl_Num; /* Control Number */
241 u16 size; /* Number of bits to represent Value */ 235 u16 size; /* Number of bits to represent Value */
242 u16 addr[25]; /* Array of Tuner Register Address for each bit position */ 236 u16 addr[25]; /* Array of Tuner Register Address for each bit pos */
243 u16 bit[25]; /* Array of bit position in Register Address for each bit position */ 237 u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */
244 u16 val[25]; /* Binary representation of Value */ 238 u16 val[25]; /* Binary representation of Value */
245} TunerControl_struct; 239};
246 240
247/* MXL5005 Tuner Struct */ 241/* MXL5005 Tuner Struct */
248struct mxl5005s_state 242struct mxl5005s_state {
249{
250 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ 243 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
251 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ 244 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
252 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ 245 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
@@ -256,14 +249,18 @@ struct mxl5005s_state
256 u32 Fxtal; /* XTAL Frequency */ 249 u32 Fxtal; /* XTAL Frequency */
257 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ 250 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
258 u16 TOP; /* Value: take over point */ 251 u16 TOP; /* Value: take over point */
259 u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ 252 u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */
260 u8 DIV_OUT; /* 4MHz or 16MHz */ 253 u8 DIV_OUT; /* 4MHz or 16MHz */
261 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ 254 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
262 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ 255 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
263 u8 Mod_Type; /* Modulation Type; */ 256
264 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ 257 /* Modulation Type; */
265 u8 TF_Type; /* Tracking Filter Type */ 258 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
266 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ 259 u8 Mod_Type;
260
261 /* Tracking Filter Type */
262 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
263 u8 TF_Type;
267 264
268 /* Calculated Settings */ 265 /* Calculated Settings */
269 u32 RF_LO; /* Synth RF LO Frequency */ 266 u32 RF_LO; /* Synth RF LO Frequency */
@@ -271,22 +268,22 @@ struct mxl5005s_state
271 u32 TG_LO; /* Synth TG_LO Frequency */ 268 u32 TG_LO; /* Synth TG_LO Frequency */
272 269
273 /* Pointers to ControlName Arrays */ 270 /* Pointers to ControlName Arrays */
274 u16 Init_Ctrl_Num; /* Number of INIT Control Names */ 271 u16 Init_Ctrl_Num; /* Number of INIT Control Names */
275 TunerControl_struct 272 struct TunerControl
276 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ 273 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
277 274
278 u16 CH_Ctrl_Num; /* Number of CH Control Names */ 275 u16 CH_Ctrl_Num; /* Number of CH Control Names */
279 TunerControl_struct 276 struct TunerControl
280 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ 277 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
281 278
282 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ 279 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
283 TunerControl_struct 280 struct TunerControl
284 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ 281 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
285 282
286 /* Pointer to Tuner Register Array */ 283 /* Pointer to Tuner Register Array */
287 u16 TunerRegs_Num; /* Number of Tuner Registers */ 284 u16 TunerRegs_Num; /* Number of Tuner Registers */
288 TunerReg_struct 285 struct TunerReg
289 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ 286 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
290 287
291 /* Linux driver framework specific */ 288 /* Linux driver framework specific */
292 struct mxl5005s_config *config; 289 struct mxl5005s_config *config;
@@ -302,21 +299,27 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
302u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); 299u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
303u16 MXL_GetMasterControl(u8 *MasterReg, int state); 300u16 MXL_GetMasterControl(u8 *MasterReg, int state);
304void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); 301void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal);
305u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); 302u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
303 u8 *RegVal, int *count);
306u32 MXL_Ceiling(u32 value, u32 resolution); 304u32 MXL_Ceiling(u32 value, u32 resolution);
307u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); 305u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
308u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); 306u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
309u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); 307u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
308 u32 value, u16 controlGroup);
310u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); 309u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
311u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); 310u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
311 u8 *RegVal, int *count);
312u32 MXL_GetXtalInt(u32 Xtal_Freq); 312u32 MXL_GetXtalInt(u32 Xtal_Freq);
313u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); 313u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
314void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); 314void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
315void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); 315void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
316u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); 316u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
317int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); 317 u8 *RegVal, int *count);
318int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
319 u8 *datatable, u8 len);
318u16 MXL_IFSynthInit(struct dvb_frontend *fe); 320u16 MXL_IFSynthInit(struct dvb_frontend *fe);
319int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); 321int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
322 u32 bandwidth);
320int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); 323int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
321 324
322/* ---------------------------------------------------------------- 325/* ----------------------------------------------------------------
@@ -343,16 +346,16 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
343 346
344 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); 347 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
345 348
346 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. 349 /* Set MxL5005S tuner RF frequency according to example code. */
347 350
348 // Tuner RF frequency setting stage 0 351 /* Tuner RF frequency setting stage 0 */
349 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; 352 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
350 AddrTable[0] = MASTER_CONTROL_ADDR; 353 AddrTable[0] = MASTER_CONTROL_ADDR;
351 ByteTable[0] |= state->config->AgcMasterByte; 354 ByteTable[0] |= state->config->AgcMasterByte;
352 355
353 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); 356 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
354 357
355 // Tuner RF frequency setting stage 1 358 /* Tuner RF frequency setting stage 1 */
356 MXL_TuneRF(fe, RfFreqHz); 359 MXL_TuneRF(fe, RfFreqHz);
357 360
358 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); 361 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
@@ -360,26 +363,28 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
360 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); 363 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
361 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); 364 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
362 MXL_ControlWrite(fe, IF_DIVVAL, 8); 365 MXL_ControlWrite(fe, IF_DIVVAL, 8);
363 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; 366 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
364 367
365 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; 368 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
366 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 369 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
367 ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; 370 ByteTable[TableLen] = MasterControlByte |
371 state->config->AgcMasterByte;
368 TableLen += 1; 372 TableLen += 1;
369 373
370 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); 374 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
371 375
372 // Wait 30 ms. 376 /* Wait 30 ms. */
373 msleep(150); 377 msleep(150);
374 378
375 // Tuner RF frequency setting stage 2 379 /* Tuner RF frequency setting stage 2 */
376 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; 380 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
377 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; 381 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
378 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; 382 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
379 383
380 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; 384 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START);
381 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 385 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
382 ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; 386 ByteTable[TableLen] = MasterControlByte |
387 state->config->AgcMasterByte ;
383 TableLen += 1; 388 TableLen += 1;
384 389
385 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); 390 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
@@ -398,7 +403,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
398{ 403{
399 struct mxl5005s_state *state = fe->tuner_priv; 404 struct mxl5005s_state *state = fe->tuner_priv;
400 state->TunerRegs_Num = TUNER_REGS_NUM ; 405 state->TunerRegs_Num = TUNER_REGS_NUM ;
401// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
402 406
403 state->TunerRegs[0].Reg_Num = 9 ; 407 state->TunerRegs[0].Reg_Num = 9 ;
404 state->TunerRegs[0].Reg_Val = 0x40 ; 408 state->TunerRegs[0].Reg_Val = 0x40 ;
@@ -1655,9 +1659,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe)
1655 return 0 ; 1659 return 0 ;
1656} 1660}
1657 1661
1658// MaxLinear source code - MXL5005_c.cpp
1659// MXL5005.cpp : Defines the initialization routines for the DLL.
1660// 2.6.12
1661void InitTunerControls(struct dvb_frontend *fe) 1662void InitTunerControls(struct dvb_frontend *fe)
1662{ 1663{
1663 MXL5005_RegisterInit(fe); 1664 MXL5005_RegisterInit(fe);
@@ -1667,57 +1668,28 @@ void InitTunerControls(struct dvb_frontend *fe)
1667#endif 1668#endif
1668} 1669}
1669 1670
1670///////////////////////////////////////////////////////////////////////////////
1671// //
1672// Function: MXL_ConfigTuner //
1673// //
1674// Description: Configure MXL5005Tuner structure for desired //
1675// Channel Bandwidth/Channel Frequency //
1676// //
1677// //
1678// Functions used: //
1679// MXL_SynthIFLO_Calc //
1680// //
1681// Inputs: //
1682// Tuner_struct: structure defined at higher level //
1683// Mode: Tuner Mode (Analog/Digital) //
1684// IF_Mode: IF Mode ( Zero/Low ) //
1685// Bandwidth: Filter Channel Bandwidth (in Hz) //
1686// IF_out: Desired IF out Frequency (in Hz) //
1687// Fxtal: Crystal Frerquency (in Hz) //
1688// TOP: 0: Dual AGC; Value: take over point //
1689// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) //
1690// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out //
1691// DIV_OUT: 0: Div-1; 1: Div-4 //
1692// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable //
1693// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI //
1694// //
1695// Outputs: //
1696// Tuner //
1697// //
1698// Return: //
1699// 0 : Successful //
1700// > 0 : Failed //
1701// //
1702///////////////////////////////////////////////////////////////////////////////
1703u16 MXL5005_TunerConfig(struct dvb_frontend *fe, 1671u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1704 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ 1672 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
1705 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ 1673 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
1706 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ 1674 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
1707 u32 IF_out, /* Desired IF Out Frequency */ 1675 u32 IF_out, /* Desired IF Out Frequency */
1708 u32 Fxtal, /* XTAL Frequency */ 1676 u32 Fxtal, /* XTAL Frequency */
1709 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ 1677 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1710 u16 TOP, /* 0: Dual AGC; Value: take over point */ 1678 u16 TOP, /* 0: Dual AGC; Value: take over point */
1711 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ 1679 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
1712 u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ 1680 u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */
1713 u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ 1681 u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
1714 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ 1682 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
1715 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ 1683 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
1716 u8 Mod_Type, /* Modulation Type; */ 1684
1717 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ 1685 /* Modulation Type; */
1718 u8 TF_Type /* Tracking Filter */ 1686 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1719 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ 1687 u8 Mod_Type,
1720 ) 1688
1689 /* Tracking Filter */
1690 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1691 u8 TF_Type
1692 )
1721{ 1693{
1722 struct mxl5005s_state *state = fe->tuner_priv; 1694 struct mxl5005s_state *state = fe->tuner_priv;
1723 u16 status = 0; 1695 u16 status = 0;
@@ -1746,105 +1718,40 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1746 return status; 1718 return status;
1747} 1719}
1748 1720
1749///////////////////////////////////////////////////////////////////////////////
1750// //
1751// Function: MXL_SynthIFLO_Calc //
1752// //
1753// Description: Calculate Internal IF-LO Frequency //
1754// //
1755// Globals: //
1756// NONE //
1757// //
1758// Functions used: //
1759// NONE //
1760// //
1761// Inputs: //
1762// Tuner_struct: structure defined at higher level //
1763// //
1764// Outputs: //
1765// Tuner //
1766// //
1767// Return: //
1768// 0 : Successful //
1769// > 0 : Failed //
1770// //
1771///////////////////////////////////////////////////////////////////////////////
1772void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) 1721void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1773{ 1722{
1774 struct mxl5005s_state *state = fe->tuner_priv; 1723 struct mxl5005s_state *state = fe->tuner_priv;
1775 if (state->Mode == 1) /* Digital Mode */ 1724 if (state->Mode == 1) /* Digital Mode */
1776 state->IF_LO = state->IF_OUT; 1725 state->IF_LO = state->IF_OUT;
1777 else /* Analog Mode */ 1726 else /* Analog Mode */ {
1778 { 1727 if (state->IF_Mode == 0) /* Analog Zero IF mode */
1779 if(state->IF_Mode == 0) /* Analog Zero IF mode */
1780 state->IF_LO = state->IF_OUT + 400000; 1728 state->IF_LO = state->IF_OUT + 400000;
1781 else /* Analog Low IF mode */ 1729 else /* Analog Low IF mode */
1782 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; 1730 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
1783 } 1731 }
1784} 1732}
1785 1733
1786///////////////////////////////////////////////////////////////////////////////
1787// //
1788// Function: MXL_SynthRFTGLO_Calc //
1789// //
1790// Description: Calculate Internal RF-LO frequency and //
1791// internal Tone-Gen(TG)-LO frequency //
1792// //
1793// Globals: //
1794// NONE //
1795// //
1796// Functions used: //
1797// NONE //
1798// //
1799// Inputs: //
1800// Tuner_struct: structure defined at higher level //
1801// //
1802// Outputs: //
1803// Tuner //
1804// //
1805// Return: //
1806// 0 : Successful //
1807// > 0 : Failed //
1808// //
1809///////////////////////////////////////////////////////////////////////////////
1810void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) 1734void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1811{ 1735{
1812 struct mxl5005s_state *state = fe->tuner_priv; 1736 struct mxl5005s_state *state = fe->tuner_priv;
1813 1737
1814 if (state->Mode == 1) /* Digital Mode */ { 1738 if (state->Mode == 1) /* Digital Mode */ {
1815 //remove 20.48MHz setting for 2.6.10 1739 /* remove 20.48MHz setting for 2.6.10 */
1816 state->RF_LO = state->RF_IN; 1740 state->RF_LO = state->RF_IN;
1817 state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 1741 /* change for 2.6.6 */
1742 state->TG_LO = state->RF_IN - 750000;
1818 } else /* Analog Mode */ { 1743 } else /* Analog Mode */ {
1819 if(state->IF_Mode == 0) /* Analog Zero IF mode */ { 1744 if (state->IF_Mode == 0) /* Analog Zero IF mode */ {
1820 state->RF_LO = state->RF_IN - 400000; 1745 state->RF_LO = state->RF_IN - 400000;
1821 state->TG_LO = state->RF_IN - 1750000; 1746 state->TG_LO = state->RF_IN - 1750000;
1822 } else /* Analog Low IF mode */ { 1747 } else /* Analog Low IF mode */ {
1823 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; 1748 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1824 state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; 1749 state->TG_LO = state->RF_IN -
1750 state->Chan_Bandwidth + 500000;
1825 } 1751 }
1826 } 1752 }
1827} 1753}
1828 1754
1829///////////////////////////////////////////////////////////////////////////////
1830// //
1831// Function: MXL_OverwriteICDefault //
1832// //
1833// Description: Overwrite the Default Register Setting //
1834// //
1835// //
1836// Functions used: //
1837// //
1838// Inputs: //
1839// Tuner_struct: structure defined at higher level //
1840// Outputs: //
1841// Tuner //
1842// //
1843// Return: //
1844// 0 : Successful //
1845// > 0 : Failed //
1846// //
1847///////////////////////////////////////////////////////////////////////////////
1848u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) 1755u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1849{ 1756{
1850 u16 status = 0; 1757 u16 status = 0;
@@ -1857,31 +1764,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1857 return status; 1764 return status;
1858} 1765}
1859 1766
1860///////////////////////////////////////////////////////////////////////////////
1861// //
1862// Function: MXL_BlockInit //
1863// //
1864// Description: Tuner Initialization as a function of 'User Settings' //
1865// * User settings in Tuner strcuture must be assigned //
1866// first //
1867// //
1868// Globals: //
1869// NONE //
1870// //
1871// Functions used: //
1872// Tuner_struct: structure defined at higher level //
1873// //
1874// Inputs: //
1875// Tuner : Tuner structure defined at higher level //
1876// //
1877// Outputs: //
1878// Tuner //
1879// //
1880// Return: //
1881// 0 : Successful //
1882// > 0 : Failed //
1883// //
1884///////////////////////////////////////////////////////////////////////////////
1885u16 MXL_BlockInit(struct dvb_frontend *fe) 1767u16 MXL_BlockInit(struct dvb_frontend *fe)
1886{ 1768{
1887 struct mxl5005s_state *state = fe->tuner_priv; 1769 struct mxl5005s_state *state = fe->tuner_priv;
@@ -1902,42 +1784,45 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
1902 /* Initialize Low-Pass Filter */ 1784 /* Initialize Low-Pass Filter */
1903 if (state->Mode) { /* Digital Mode */ 1785 if (state->Mode) { /* Digital Mode */
1904 switch (state->Chan_Bandwidth) { 1786 switch (state->Chan_Bandwidth) {
1905 case 8000000: 1787 case 8000000:
1906 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); 1788 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1907 break; 1789 break;
1908 case 7000000: 1790 case 7000000:
1909 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); 1791 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1910 break; 1792 break;
1911 case 6000000: 1793 case 6000000:
1912 printk("%s() doing 6MHz digital\n", __func__); 1794 status += MXL_ControlWrite(fe,
1913 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); 1795 BB_DLPF_BANDSEL, 3);
1914 break; 1796 break;
1915 } 1797 }
1916 } else { /* Analog Mode */ 1798 } else { /* Analog Mode */
1917 switch (state->Chan_Bandwidth) { 1799 switch (state->Chan_Bandwidth) {
1918 case 8000000: /* Low Zero */ 1800 case 8000000: /* Low Zero */
1919 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); 1801 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1920 break; 1802 (state->IF_Mode ? 0 : 3));
1921 case 7000000: 1803 break;
1922 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); 1804 case 7000000:
1923 break; 1805 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1924 case 6000000: 1806 (state->IF_Mode ? 1 : 4));
1925 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); 1807 break;
1926 break; 1808 case 6000000:
1809 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1810 (state->IF_Mode ? 2 : 5));
1811 break;
1927 } 1812 }
1928 } 1813 }
1929 1814
1930 /* Charge Pump Control Dig Ana */ 1815 /* Charge Pump Control Dig Ana */
1931 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); 1816 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1932 status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); 1817 status += MXL_ControlWrite(fe,
1818 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1933 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); 1819 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1934 1820
1935 /* AGC TOP Control */ 1821 /* AGC TOP Control */
1936 if (state->AGC_Mode == 0) /* Dual AGC */ { 1822 if (state->AGC_Mode == 0) /* Dual AGC */ {
1937 status += MXL_ControlWrite(fe, AGC_IF, 15); 1823 status += MXL_ControlWrite(fe, AGC_IF, 15);
1938 status += MXL_ControlWrite(fe, AGC_RF, 15); 1824 status += MXL_ControlWrite(fe, AGC_RF, 15);
1939 } 1825 } else /* Single AGC Mode Dig Ana */
1940 else /* Single AGC Mode Dig Ana */
1941 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); 1826 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1942 1827
1943 if (state->TOP == 55) /* TOP == 5.5 */ 1828 if (state->TOP == 55) /* TOP == 5.5 */
@@ -2008,7 +1893,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2008 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1893 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2009 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); 1894 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2010 } 1895 }
2011 if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { 1896 if ((state->IF_OUT == 36125000UL) ||
1897 (state->IF_OUT == 36150000UL)) {
2012 status += MXL_ControlWrite(fe, EN_AAF, 1); 1898 status += MXL_ControlWrite(fe, EN_AAF, 1);
2013 status += MXL_ControlWrite(fe, EN_3P, 1); 1899 status += MXL_ControlWrite(fe, EN_3P, 1);
2014 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1900 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
@@ -2021,15 +1907,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2021 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); 1907 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2022 } 1908 }
2023 } else { /* Analog Mode */ 1909 } else { /* Analog Mode */
2024 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) 1910 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) {
2025 {
2026 status += MXL_ControlWrite(fe, EN_AAF, 1); 1911 status += MXL_ControlWrite(fe, EN_AAF, 1);
2027 status += MXL_ControlWrite(fe, EN_3P, 1); 1912 status += MXL_ControlWrite(fe, EN_3P, 1);
2028 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1913 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2029 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); 1914 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2030 } 1915 }
2031 if (state->IF_OUT > 5000000UL) 1916 if (state->IF_OUT > 5000000UL) {
2032 {
2033 status += MXL_ControlWrite(fe, EN_AAF, 0); 1917 status += MXL_ControlWrite(fe, EN_AAF, 0);
2034 status += MXL_ControlWrite(fe, EN_3P, 0); 1918 status += MXL_ControlWrite(fe, EN_3P, 0);
2035 status += MXL_ControlWrite(fe, EN_AUX_3P, 0); 1919 status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
@@ -2073,13 +1957,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2073 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ 1957 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
2074 1958
2075 /* Set TG_R_DIV */ 1959 /* Set TG_R_DIV */
2076 status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); 1960 status += MXL_ControlWrite(fe, TG_R_DIV,
1961 MXL_Ceiling(state->Fxtal, 1000000));
2077 1962
2078 /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ 1963 /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
2079 1964
2080 /* RSSI Control */ 1965 /* RSSI Control */
2081 if (state->EN_RSSI) 1966 if (state->EN_RSSI) {
2082 {
2083 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 1967 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2084 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 1968 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2085 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); 1969 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
@@ -2098,8 +1982,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2098 /* Modulation type bit settings 1982 /* Modulation type bit settings
2099 * Override the control values preset 1983 * Override the control values preset
2100 */ 1984 */
2101 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ 1985 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ {
2102 {
2103 state->AGC_Mode = 1; /* Single AGC Mode */ 1986 state->AGC_Mode = 1; /* Single AGC Mode */
2104 1987
2105 /* Enable RSSI */ 1988 /* Enable RSSI */
@@ -2122,8 +2005,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2122 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2005 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2123 2006
2124 } 2007 }
2125 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ 2008 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ {
2126 {
2127 state->AGC_Mode = 1; /* Single AGC Mode */ 2009 state->AGC_Mode = 1; /* Single AGC Mode */
2128 2010
2129 /* Enable RSSI */ 2011 /* Enable RSSI */
@@ -2141,14 +2023,15 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2141 status += MXL_ControlWrite(fe, RFA_FLR, 2); 2023 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2142 status += MXL_ControlWrite(fe, RFA_CEIL, 13); 2024 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2143 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); 2025 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2144 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ 2026 /* Low Zero */
2027 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2028
2145 if (state->IF_OUT <= 6280000UL) /* Low IF */ 2029 if (state->IF_OUT <= 6280000UL) /* Low IF */
2146 status += MXL_ControlWrite(fe, BB_IQSWAP, 0); 2030 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2147 else /* High IF */ 2031 else /* High IF */
2148 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2032 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2149 } 2033 }
2150 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ 2034 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ {
2151 {
2152 state->Mode = MXL_DIGITAL_MODE; 2035 state->Mode = MXL_DIGITAL_MODE;
2153 2036
2154 /* state->AGC_Mode = 1; */ /* Single AGC Mode */ 2037 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
@@ -2163,7 +2046,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2163 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); 2046 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2164 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); 2047 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2165 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); 2048 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2166 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ 2049 /* change here for v2.6.5 */
2050 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2167 2051
2168 if (state->IF_OUT <= 6280000UL) /* Low IF */ 2052 if (state->IF_OUT <= 6280000UL) /* Low IF */
2169 status += MXL_ControlWrite(fe, BB_IQSWAP, 0); 2053 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
@@ -2183,7 +2067,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2183 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2067 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2184 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 2068 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2185 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 2069 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2186 status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ 2070 /* change for 2.6.3 */
2071 status += MXL_ControlWrite(fe, AGC_IF, 1);
2187 status += MXL_ControlWrite(fe, AGC_RF, 15); 2072 status += MXL_ControlWrite(fe, AGC_RF, 15);
2188 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2073 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2189 } 2074 }
@@ -2207,7 +2092,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2207 } 2092 }
2208 2093
2209 /* RSSI disable */ 2094 /* RSSI disable */
2210 if(state->EN_RSSI == 0) { 2095 if (state->EN_RSSI == 0) {
2211 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2096 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2212 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2097 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2213 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 2098 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
@@ -2217,34 +2102,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2217 return status; 2102 return status;
2218} 2103}
2219 2104
2220///////////////////////////////////////////////////////////////////////////////
2221// //
2222// Function: MXL_IFSynthInit //
2223// //
2224// Description: Tuner IF Synthesizer related register initialization //
2225// //
2226// Globals: //
2227// NONE //
2228// //
2229// Functions used: //
2230// Tuner_struct: structure defined at higher level //
2231// //
2232// Inputs: //
2233// Tuner : Tuner structure defined at higher level //
2234// //
2235// Outputs: //
2236// Tuner //
2237// //
2238// Return: //
2239// 0 : Successful //
2240// > 0 : Failed //
2241// //
2242///////////////////////////////////////////////////////////////////////////////
2243u16 MXL_IFSynthInit(struct dvb_frontend *fe) 2105u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2244{ 2106{
2245 struct mxl5005s_state *state = fe->tuner_priv; 2107 struct mxl5005s_state *state = fe->tuner_priv;
2246 u16 status = 0 ; 2108 u16 status = 0 ;
2247 // Declare Local Variables
2248 u32 Fref = 0 ; 2109 u32 Fref = 0 ;
2249 u32 Kdbl, intModVal ; 2110 u32 Kdbl, intModVal ;
2250 u32 fracModVal ; 2111 u32 fracModVal ;
@@ -2255,268 +2116,207 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2255 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) 2116 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2256 Kdbl = 1 ; 2117 Kdbl = 1 ;
2257 2118
2258 // 2119 /* IF Synthesizer Control */
2259 // IF Synthesizer Control 2120 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ {
2260 //
2261 if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode
2262 {
2263 if (state->IF_LO == 41000000UL) { 2121 if (state->IF_LO == 41000000UL) {
2264 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2122 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2265 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2123 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2266 Fref = 328000000UL ; 2124 Fref = 328000000UL ;
2267 } 2125 }
2268 if (state->IF_LO == 47000000UL) { 2126 if (state->IF_LO == 47000000UL) {
2269 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2127 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2270 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2128 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2271 Fref = 376000000UL ; 2129 Fref = 376000000UL ;
2272 } 2130 }
2273 if (state->IF_LO == 54000000UL) { 2131 if (state->IF_LO == 54000000UL) {
2274 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2132 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2275 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2133 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2276 Fref = 324000000UL ; 2134 Fref = 324000000UL ;
2277 } 2135 }
2278 if (state->IF_LO == 60000000UL) { 2136 if (state->IF_LO == 60000000UL) {
2279 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2137 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2280 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2138 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2281 Fref = 360000000UL ; 2139 Fref = 360000000UL ;
2282 } 2140 }
2283 if (state->IF_LO == 39250000UL) { 2141 if (state->IF_LO == 39250000UL) {
2284 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2142 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2285 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2143 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2286 Fref = 314000000UL ; 2144 Fref = 314000000UL ;
2287 } 2145 }
2288 if (state->IF_LO == 39650000UL) { 2146 if (state->IF_LO == 39650000UL) {
2289 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2147 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2290 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2148 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2291 Fref = 317200000UL ; 2149 Fref = 317200000UL ;
2292 } 2150 }
2293 if (state->IF_LO == 40150000UL) { 2151 if (state->IF_LO == 40150000UL) {
2294 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2152 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2295 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2153 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2296 Fref = 321200000UL ; 2154 Fref = 321200000UL ;
2297 } 2155 }
2298 if (state->IF_LO == 40650000UL) { 2156 if (state->IF_LO == 40650000UL) {
2299 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2157 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2300 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2158 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2301 Fref = 325200000UL ; 2159 Fref = 325200000UL ;
2302 } 2160 }
2303 } 2161 }
2304 2162
2305 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) 2163 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) {
2306 {
2307 if (state->IF_LO == 57000000UL) { 2164 if (state->IF_LO == 57000000UL) {
2308 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2165 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2309 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2166 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2310 Fref = 342000000UL ; 2167 Fref = 342000000UL ;
2311 } 2168 }
2312 if (state->IF_LO == 44000000UL) { 2169 if (state->IF_LO == 44000000UL) {
2313 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2170 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2314 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2171 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2315 Fref = 352000000UL ; 2172 Fref = 352000000UL ;
2316 } 2173 }
2317 if (state->IF_LO == 43750000UL) { 2174 if (state->IF_LO == 43750000UL) {
2318 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2175 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2319 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2176 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2320 Fref = 350000000UL ; 2177 Fref = 350000000UL ;
2321 } 2178 }
2322 if (state->IF_LO == 36650000UL) { 2179 if (state->IF_LO == 36650000UL) {
2323 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2180 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2324 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2181 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2325 Fref = 366500000UL ; 2182 Fref = 366500000UL ;
2326 } 2183 }
2327 if (state->IF_LO == 36150000UL) { 2184 if (state->IF_LO == 36150000UL) {
2328 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2185 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2329 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2186 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2330 Fref = 361500000UL ; 2187 Fref = 361500000UL ;
2331 } 2188 }
2332 if (state->IF_LO == 36000000UL) { 2189 if (state->IF_LO == 36000000UL) {
2333 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2190 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2334 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2191 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2335 Fref = 360000000UL ; 2192 Fref = 360000000UL ;
2336 } 2193 }
2337 if (state->IF_LO == 35250000UL) { 2194 if (state->IF_LO == 35250000UL) {
2338 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2195 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2339 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2196 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2340 Fref = 352500000UL ; 2197 Fref = 352500000UL ;
2341 } 2198 }
2342 if (state->IF_LO == 34750000UL) { 2199 if (state->IF_LO == 34750000UL) {
2343 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2200 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2344 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2201 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2345 Fref = 347500000UL ; 2202 Fref = 347500000UL ;
2346 } 2203 }
2347 if (state->IF_LO == 6280000UL) { 2204 if (state->IF_LO == 6280000UL) {
2348 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2205 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2349 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2206 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2350 Fref = 376800000UL ; 2207 Fref = 376800000UL ;
2351 } 2208 }
2352 if (state->IF_LO == 5000000UL) { 2209 if (state->IF_LO == 5000000UL) {
2353 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; 2210 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2354 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2211 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2355 Fref = 360000000UL ; 2212 Fref = 360000000UL ;
2356 } 2213 }
2357 if (state->IF_LO == 4500000UL) { 2214 if (state->IF_LO == 4500000UL) {
2358 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; 2215 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2359 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2216 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2360 Fref = 360000000UL ; 2217 Fref = 360000000UL ;
2361 } 2218 }
2362 if (state->IF_LO == 4570000UL) { 2219 if (state->IF_LO == 4570000UL) {
2363 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; 2220 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2364 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2221 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2365 Fref = 365600000UL ; 2222 Fref = 365600000UL ;
2366 } 2223 }
2367 if (state->IF_LO == 4000000UL) { 2224 if (state->IF_LO == 4000000UL) {
2368 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; 2225 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2369 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2226 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2370 Fref = 360000000UL ; 2227 Fref = 360000000UL ;
2371 } 2228 }
2372 if (state->IF_LO == 57400000UL) 2229 if (state->IF_LO == 57400000UL) {
2373 { 2230 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2374 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2231 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2375 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2376 Fref = 344400000UL ; 2232 Fref = 344400000UL ;
2377 } 2233 }
2378 if (state->IF_LO == 44400000UL) 2234 if (state->IF_LO == 44400000UL) {
2379 { 2235 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2380 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2236 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2381 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2382 Fref = 355200000UL ; 2237 Fref = 355200000UL ;
2383 } 2238 }
2384 if (state->IF_LO == 44150000UL) 2239 if (state->IF_LO == 44150000UL) {
2385 { 2240 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2386 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2241 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2387 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2388 Fref = 353200000UL ; 2242 Fref = 353200000UL ;
2389 } 2243 }
2390 if (state->IF_LO == 37050000UL) 2244 if (state->IF_LO == 37050000UL) {
2391 { 2245 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2392 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2246 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2393 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2394 Fref = 370500000UL ; 2247 Fref = 370500000UL ;
2395 } 2248 }
2396 if (state->IF_LO == 36550000UL) 2249 if (state->IF_LO == 36550000UL) {
2397 { 2250 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2398 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2251 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2399 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2400 Fref = 365500000UL ; 2252 Fref = 365500000UL ;
2401 } 2253 }
2402 if (state->IF_LO == 36125000UL) { 2254 if (state->IF_LO == 36125000UL) {
2403 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2255 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2404 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2256 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2405 Fref = 361250000UL ; 2257 Fref = 361250000UL ;
2406 } 2258 }
2407 if (state->IF_LO == 6000000UL) { 2259 if (state->IF_LO == 6000000UL) {
2408 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2260 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2409 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2261 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2410 Fref = 360000000UL ; 2262 Fref = 360000000UL ;
2411 } 2263 }
2412 if (state->IF_LO == 5400000UL) 2264 if (state->IF_LO == 5400000UL) {
2413 { 2265 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2414 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2266 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2415 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2416 Fref = 324000000UL ; 2267 Fref = 324000000UL ;
2417 } 2268 }
2418 if (state->IF_LO == 5380000UL) { 2269 if (state->IF_LO == 5380000UL) {
2419 printk("%s() doing 5.38\n", __func__); 2270 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2420 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2271 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2421 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2422 Fref = 322800000UL ; 2272 Fref = 322800000UL ;
2423 } 2273 }
2424 if (state->IF_LO == 5200000UL) { 2274 if (state->IF_LO == 5200000UL) {
2425 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; 2275 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2426 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2276 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2427 Fref = 374400000UL ; 2277 Fref = 374400000UL ;
2428 } 2278 }
2429 if (state->IF_LO == 4900000UL) 2279 if (state->IF_LO == 4900000UL) {
2430 { 2280 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2431 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; 2281 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2432 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2433 Fref = 352800000UL ; 2282 Fref = 352800000UL ;
2434 } 2283 }
2435 if (state->IF_LO == 4400000UL) 2284 if (state->IF_LO == 4400000UL) {
2436 { 2285 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2437 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; 2286 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2438 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2439 Fref = 352000000UL ; 2287 Fref = 352000000UL ;
2440 } 2288 }
2441 if (state->IF_LO == 4063000UL) //add for 2.6.8 2289 if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ {
2442 { 2290 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2443 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; 2291 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2444 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2445 Fref = 365670000UL ; 2292 Fref = 365670000UL ;
2446 } 2293 }
2447 } 2294 }
2448 // CHCAL_INT_MOD_IF 2295 /* CHCAL_INT_MOD_IF */
2449 // CHCAL_FRAC_MOD_IF 2296 /* CHCAL_FRAC_MOD_IF */
2450 intModVal = Fref / (state->Fxtal * Kdbl/2) ; 2297 intModVal = Fref / (state->Fxtal * Kdbl/2);
2451 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; 2298 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2299
2300 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) *
2301 intModVal);
2452 2302
2453 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); 2303 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000);
2454 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; 2304 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2455 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ;
2456 2305
2457 return status ; 2306 return status ;
2458} 2307}
2459 2308
2460///////////////////////////////////////////////////////////////////////////////
2461// //
2462// Function: MXL_GetXtalInt //
2463// //
2464// Description: return the Crystal Integration Value for //
2465// TG_VCO_BIAS calculation //
2466// //
2467// Globals: //
2468// NONE //
2469// //
2470// Functions used: //
2471// NONE //
2472// //
2473// Inputs: //
2474// Crystal Frequency Value in Hz //
2475// //
2476// Outputs: //
2477// Calculated Crystal Frequency Integration Value //
2478// //
2479// Return: //
2480// 0 : Successful //
2481// > 0 : Failed //
2482// //
2483///////////////////////////////////////////////////////////////////////////////
2484u32 MXL_GetXtalInt(u32 Xtal_Freq) 2309u32 MXL_GetXtalInt(u32 Xtal_Freq)
2485{ 2310{
2486 if ((Xtal_Freq % 1000000) == 0) 2311 if ((Xtal_Freq % 1000000) == 0)
2487 return (Xtal_Freq / 10000) ; 2312 return (Xtal_Freq / 10000);
2488 else 2313 else
2489 return (((Xtal_Freq / 1000000) + 1)*100) ; 2314 return (((Xtal_Freq / 1000000) + 1)*100);
2490} 2315}
2491 2316
2492///////////////////////////////////////////////////////////////////////////////
2493// //
2494// Function: MXL5005_TuneRF //
2495// //
2496// Description: Set control names to tune to requested RF_IN frequency //
2497// //
2498// Globals: //
2499// None //
2500// //
2501// Functions used: //
2502// MXL_SynthRFTGLO_Calc //
2503// MXL5005_ControlWrite //
2504// MXL_GetXtalInt //
2505// //
2506// Inputs: //
2507// Tuner : Tuner structure defined at higher level //
2508// //
2509// Outputs: //
2510// Tuner //
2511// //
2512// Return: //
2513// 0 : Successful //
2514// 1 : Unsuccessful //
2515///////////////////////////////////////////////////////////////////////////////
2516u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) 2317u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2517{ 2318{
2518 struct mxl5005s_state *state = fe->tuner_priv; 2319 struct mxl5005s_state *state = fe->tuner_priv;
2519 // Declare Local Variables
2520 u16 status = 0; 2320 u16 status = 0;
2521 u32 divider_val, E3, E4, E5, E5A; 2321 u32 divider_val, E3, E4, E5, E5A;
2522 u32 Fmax, Fmin, FmaxBin, FminBin; 2322 u32 Fmax, Fmin, FmaxBin, FminBin;
@@ -2527,8 +2327,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2527 2327
2528 u32 Fref_TG; 2328 u32 Fref_TG;
2529 u32 Fvco; 2329 u32 Fvco;
2530// u32 temp;
2531
2532 2330
2533 Xtal_Int = MXL_GetXtalInt(state->Fxtal); 2331 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
2534 2332
@@ -2541,21 +2339,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2541 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) 2339 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2542 Kdbl_RF = 1; 2340 Kdbl_RF = 1;
2543 2341
2544 // 2342 /* Downconverter Controls
2545 // Downconverter Controls 2343 * Look-Up Table Implementation for:
2546 // 2344 * DN_POLY
2547 // Look-Up Table Implementation for: 2345 * DN_RFGAIN
2548 // DN_POLY 2346 * DN_CAP_RFLPF
2549 // DN_RFGAIN 2347 * DN_EN_VHFUHFBAR
2550 // DN_CAP_RFLPF 2348 * DN_GAIN_ADJUST
2551 // DN_EN_VHFUHFBAR 2349 * Change the boundary reference from RF_IN to RF_LO
2552 // DN_GAIN_ADJUST 2350 */
2553 // Change the boundary reference from RF_IN to RF_LO 2351 if (state->RF_LO < 40000000UL)
2554 if (state->RF_LO < 40000000UL) {
2555 return -1; 2352 return -1;
2556 } 2353
2557 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { 2354 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2558 // Look-Up Table implementation
2559 status += MXL_ControlWrite(fe, DN_POLY, 2); 2355 status += MXL_ControlWrite(fe, DN_POLY, 2);
2560 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2356 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2561 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); 2357 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
@@ -2563,7 +2359,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2563 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); 2359 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2564 } 2360 }
2565 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { 2361 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2566 // Look-Up Table implementation
2567 status += MXL_ControlWrite(fe, DN_POLY, 3); 2362 status += MXL_ControlWrite(fe, DN_POLY, 3);
2568 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2363 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2569 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); 2364 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
@@ -2571,7 +2366,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2571 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); 2366 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2572 } 2367 }
2573 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { 2368 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2574 // Look-Up Table implementation
2575 status += MXL_ControlWrite(fe, DN_POLY, 3); 2369 status += MXL_ControlWrite(fe, DN_POLY, 3);
2576 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2370 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2577 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); 2371 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
@@ -2579,7 +2373,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2579 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); 2373 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2580 } 2374 }
2581 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { 2375 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2582 // Look-Up Table implementation
2583 status += MXL_ControlWrite(fe, DN_POLY, 3); 2376 status += MXL_ControlWrite(fe, DN_POLY, 3);
2584 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2377 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2585 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); 2378 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
@@ -2587,34 +2380,31 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2587 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); 2380 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2588 } 2381 }
2589 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { 2382 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2590 // Look-Up Table implementation 2383 status += MXL_ControlWrite(fe, DN_POLY, 3);
2591 status += MXL_ControlWrite(fe, DN_POLY, 3) ; 2384 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2592 status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; 2385 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2593 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; 2386 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2594 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; 2387 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2595 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
2596 } 2388 }
2597 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { 2389 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
2598 // Look-Up Table implementation 2390 status += MXL_ControlWrite(fe, DN_POLY, 3);
2599 status += MXL_ControlWrite(fe, DN_POLY, 3) ; 2391 status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
2600 status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; 2392 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2601 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; 2393 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2602 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; 2394 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2603 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
2604 } 2395 }
2605 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { 2396 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
2606 // Look-Up Table implementation 2397 status += MXL_ControlWrite(fe, DN_POLY, 3);
2607 status += MXL_ControlWrite(fe, DN_POLY, 3) ; 2398 status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
2608 status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; 2399 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2609 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; 2400 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2610 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; 2401 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2611 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
2612 } 2402 }
2613 if (state->RF_LO > 900000000UL) { 2403 if (state->RF_LO > 900000000UL)
2614 return -1; 2404 return -1;
2615 } 2405
2616 // DN_IQTNBUF_AMP 2406 /* DN_IQTNBUF_AMP */
2617 // DN_IQTNGNBFBIAS_BST 2407 /* DN_IQTNGNBFBIAS_BST */
2618 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { 2408 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2619 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2409 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2620 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2410 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
@@ -2680,18 +2470,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2680 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); 2470 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2681 } 2471 }
2682 2472
2683 // 2473 /*
2684 // Set RF Synth and LO Path Control 2474 * Set RF Synth and LO Path Control
2685 // 2475 *
2686 // Look-Up table implementation for: 2476 * Look-Up table implementation for:
2687 // RFSYN_EN_OUTMUX 2477 * RFSYN_EN_OUTMUX
2688 // RFSYN_SEL_VCO_OUT 2478 * RFSYN_SEL_VCO_OUT
2689 // RFSYN_SEL_VCO_HI 2479 * RFSYN_SEL_VCO_HI
2690 // RFSYN_SEL_DIVM 2480 * RFSYN_SEL_DIVM
2691 // RFSYN_RF_DIV_BIAS 2481 * RFSYN_RF_DIV_BIAS
2692 // DN_SEL_FREQ 2482 * DN_SEL_FREQ
2693 // 2483 *
2694 // Set divider_val, Fmax, Fmix to use in Equations 2484 * Set divider_val, Fmax, Fmix to use in Equations
2485 */
2695 FminBin = 28000000UL ; 2486 FminBin = 28000000UL ;
2696 FmaxBin = 42500000UL ; 2487 FmaxBin = 42500000UL ;
2697 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { 2488 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
@@ -2721,12 +2512,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2721 FminBin = 56000000UL ; 2512 FminBin = 56000000UL ;
2722 FmaxBin = 85000000UL ; 2513 FmaxBin = 85000000UL ;
2723 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2514 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2724 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2515 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2725 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2516 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2726 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; 2517 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2727 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2518 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2728 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2519 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2729 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; 2520 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2730 divider_val = 32 ; 2521 divider_val = 32 ;
2731 Fmax = FmaxBin ; 2522 Fmax = FmaxBin ;
2732 Fmin = FminBin ; 2523 Fmin = FminBin ;
@@ -2734,12 +2525,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2734 FminBin = 85000000UL ; 2525 FminBin = 85000000UL ;
2735 FmaxBin = 112000000UL ; 2526 FmaxBin = 112000000UL ;
2736 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2527 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2737 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2528 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2738 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2529 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2739 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; 2530 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2740 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2531 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2741 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2532 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2742 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; 2533 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2743 divider_val = 32 ; 2534 divider_val = 32 ;
2744 Fmax = FmaxBin ; 2535 Fmax = FmaxBin ;
2745 Fmin = FminBin ; 2536 Fmin = FminBin ;
@@ -2747,12 +2538,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2747 FminBin = 112000000UL ; 2538 FminBin = 112000000UL ;
2748 FmaxBin = 170000000UL ; 2539 FmaxBin = 170000000UL ;
2749 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2540 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2750 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2541 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2751 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2542 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2752 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; 2543 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2753 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2544 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2754 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2545 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2755 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; 2546 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2756 divider_val = 16 ; 2547 divider_val = 16 ;
2757 Fmax = FmaxBin ; 2548 Fmax = FmaxBin ;
2758 Fmin = FminBin ; 2549 Fmin = FminBin ;
@@ -2760,12 +2551,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2760 FminBin = 170000000UL ; 2551 FminBin = 170000000UL ;
2761 FmaxBin = 225000000UL ; 2552 FmaxBin = 225000000UL ;
2762 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2553 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2763 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2554 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2764 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2555 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2765 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; 2556 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2766 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2557 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2767 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2558 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2768 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; 2559 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2769 divider_val = 16 ; 2560 divider_val = 16 ;
2770 Fmax = FmaxBin ; 2561 Fmax = FmaxBin ;
2771 Fmin = FminBin ; 2562 Fmin = FminBin ;
@@ -2773,12 +2564,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2773 FminBin = 225000000UL ; 2564 FminBin = 225000000UL ;
2774 FmaxBin = 300000000UL ; 2565 FmaxBin = 300000000UL ;
2775 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2566 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2776 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2567 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2777 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2568 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2778 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; 2569 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2779 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2570 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2780 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2571 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2781 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; 2572 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
2782 divider_val = 8 ; 2573 divider_val = 8 ;
2783 Fmax = 340000000UL ; 2574 Fmax = 340000000UL ;
2784 Fmin = FminBin ; 2575 Fmin = FminBin ;
@@ -2786,12 +2577,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2786 FminBin = 300000000UL ; 2577 FminBin = 300000000UL ;
2787 FmaxBin = 340000000UL ; 2578 FmaxBin = 340000000UL ;
2788 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2579 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2789 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; 2580 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2790 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; 2581 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2791 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; 2582 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2792 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2583 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2793 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2584 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2794 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; 2585 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2795 divider_val = 8 ; 2586 divider_val = 8 ;
2796 Fmax = FmaxBin ; 2587 Fmax = FmaxBin ;
2797 Fmin = 225000000UL ; 2588 Fmin = 225000000UL ;
@@ -2799,12 +2590,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2799 FminBin = 340000000UL ; 2590 FminBin = 340000000UL ;
2800 FmaxBin = 450000000UL ; 2591 FmaxBin = 450000000UL ;
2801 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2592 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2802 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; 2593 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2803 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; 2594 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2804 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; 2595 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2805 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; 2596 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2806 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; 2597 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
2807 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; 2598 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2808 divider_val = 8 ; 2599 divider_val = 8 ;
2809 Fmax = FmaxBin ; 2600 Fmax = FmaxBin ;
2810 Fmin = FminBin ; 2601 Fmin = FminBin ;
@@ -2812,12 +2603,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2812 FminBin = 450000000UL ; 2603 FminBin = 450000000UL ;
2813 FmaxBin = 680000000UL ; 2604 FmaxBin = 680000000UL ;
2814 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2605 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2815 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2606 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2816 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2607 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2817 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; 2608 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2818 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; 2609 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2819 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2610 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2820 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; 2611 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2821 divider_val = 4 ; 2612 divider_val = 4 ;
2822 Fmax = FmaxBin ; 2613 Fmax = FmaxBin ;
2823 Fmin = FminBin ; 2614 Fmin = FminBin ;
@@ -2825,67 +2616,66 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2825 FminBin = 680000000UL ; 2616 FminBin = 680000000UL ;
2826 FmaxBin = 900000000UL ; 2617 FmaxBin = 900000000UL ;
2827 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2618 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2828 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; 2619 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2829 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; 2620 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2830 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; 2621 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2831 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; 2622 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2832 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; 2623 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2833 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; 2624 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2834 divider_val = 4 ; 2625 divider_val = 4 ;
2835 Fmax = FmaxBin ; 2626 Fmax = FmaxBin ;
2836 Fmin = FminBin ; 2627 Fmin = FminBin ;
2837 } 2628 }
2838 2629
2839 // CHCAL_INT_MOD_RF 2630 /* CHCAL_INT_MOD_RF
2840 // CHCAL_FRAC_MOD_RF 2631 * CHCAL_FRAC_MOD_RF
2841 // RFSYN_LPF_R 2632 * RFSYN_LPF_R
2842 // CHCAL_EN_INT_RF 2633 * CHCAL_EN_INT_RF
2843 2634 */
2844 // Equation E3 2635 /* Equation E3 RFSYN_VCO_BIAS */
2845 // RFSYN_VCO_BIAS
2846 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; 2636 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2847 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; 2637 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2848 2638
2849 // Equation E4 2639 /* Equation E4 CHCAL_INT_MOD_RF */
2850 // CHCAL_INT_MOD_RF 2640 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000);
2851 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; 2641 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2852 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ;
2853 2642
2854 // Equation E5 2643 /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */
2855 // CHCAL_FRAC_MOD_RF 2644 E5 = ((2<<17)*(state->RF_LO/10000*divider_val -
2856 // CHCAL_EN_INT_RF 2645 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) /
2857 E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; 2646 (2*state->Fxtal*Kdbl_RF/10000);
2858 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
2859 2647
2860 // Equation E5A 2648 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2861 // RFSYN_LPF_R 2649
2650 /* Equation E5A RFSYN_LPF_R */
2862 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; 2651 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2863 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; 2652 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2864 2653
2865 // Euqation E5B 2654 /* Euqation E5B CHCAL_EN_INIT_RF */
2866 // CHCAL_EN_INIT_RF
2867 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); 2655 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2868 //if (E5 == 0) 2656 /*if (E5 == 0)
2869 // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); 2657 * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2870 //else 2658 *else
2871 // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; 2659 * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2872 2660 */
2873 // 2661
2874 // Set TG Synth 2662 /*
2875 // 2663 * Set TG Synth
2876 // Look-Up table implementation for: 2664 *
2877 // TG_LO_DIVVAL 2665 * Look-Up table implementation for:
2878 // TG_LO_SELVAL 2666 * TG_LO_DIVVAL
2879 // 2667 * TG_LO_SELVAL
2880 // Set divider_val, Fmax, Fmix to use in Equations 2668 *
2881 if (state->TG_LO < 33000000UL) { 2669 * Set divider_val, Fmax, Fmix to use in Equations
2670 */
2671 if (state->TG_LO < 33000000UL)
2882 return -1; 2672 return -1;
2883 } 2673
2884 FminBin = 33000000UL ; 2674 FminBin = 33000000UL ;
2885 FmaxBin = 50000000UL ; 2675 FmaxBin = 50000000UL ;
2886 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { 2676 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2887 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; 2677 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
2888 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; 2678 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2889 divider_val = 36 ; 2679 divider_val = 36 ;
2890 Fmax = FmaxBin ; 2680 Fmax = FmaxBin ;
2891 Fmin = FminBin ; 2681 Fmin = FminBin ;
@@ -2893,8 +2683,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2893 FminBin = 50000000UL ; 2683 FminBin = 50000000UL ;
2894 FmaxBin = 67000000UL ; 2684 FmaxBin = 67000000UL ;
2895 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2685 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2896 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; 2686 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
2897 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; 2687 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2898 divider_val = 24 ; 2688 divider_val = 24 ;
2899 Fmax = FmaxBin ; 2689 Fmax = FmaxBin ;
2900 Fmin = FminBin ; 2690 Fmin = FminBin ;
@@ -2902,8 +2692,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2902 FminBin = 67000000UL ; 2692 FminBin = 67000000UL ;
2903 FmaxBin = 100000000UL ; 2693 FmaxBin = 100000000UL ;
2904 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2694 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2905 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; 2695 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
2906 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; 2696 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2907 divider_val = 18 ; 2697 divider_val = 18 ;
2908 Fmax = FmaxBin ; 2698 Fmax = FmaxBin ;
2909 Fmin = FminBin ; 2699 Fmin = FminBin ;
@@ -2911,8 +2701,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2911 FminBin = 100000000UL ; 2701 FminBin = 100000000UL ;
2912 FmaxBin = 150000000UL ; 2702 FmaxBin = 150000000UL ;
2913 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2703 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2914 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; 2704 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2915 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; 2705 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2916 divider_val = 12 ; 2706 divider_val = 12 ;
2917 Fmax = FmaxBin ; 2707 Fmax = FmaxBin ;
2918 Fmin = FminBin ; 2708 Fmin = FminBin ;
@@ -2920,8 +2710,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2920 FminBin = 150000000UL ; 2710 FminBin = 150000000UL ;
2921 FmaxBin = 200000000UL ; 2711 FmaxBin = 200000000UL ;
2922 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2712 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2923 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; 2713 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2924 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; 2714 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2925 divider_val = 8 ; 2715 divider_val = 8 ;
2926 Fmax = FmaxBin ; 2716 Fmax = FmaxBin ;
2927 Fmin = FminBin ; 2717 Fmin = FminBin ;
@@ -2929,8 +2719,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2929 FminBin = 200000000UL ; 2719 FminBin = 200000000UL ;
2930 FmaxBin = 300000000UL ; 2720 FmaxBin = 300000000UL ;
2931 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2721 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2932 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; 2722 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2933 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; 2723 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2934 divider_val = 6 ; 2724 divider_val = 6 ;
2935 Fmax = FmaxBin ; 2725 Fmax = FmaxBin ;
2936 Fmin = FminBin ; 2726 Fmin = FminBin ;
@@ -2938,8 +2728,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2938 FminBin = 300000000UL ; 2728 FminBin = 300000000UL ;
2939 FmaxBin = 400000000UL ; 2729 FmaxBin = 400000000UL ;
2940 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2730 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2941 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; 2731 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2942 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; 2732 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2943 divider_val = 4 ; 2733 divider_val = 4 ;
2944 Fmax = FmaxBin ; 2734 Fmax = FmaxBin ;
2945 Fmin = FminBin ; 2735 Fmin = FminBin ;
@@ -2947,8 +2737,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2947 FminBin = 400000000UL ; 2737 FminBin = 400000000UL ;
2948 FmaxBin = 600000000UL ; 2738 FmaxBin = 600000000UL ;
2949 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2739 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2950 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; 2740 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2951 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; 2741 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2952 divider_val = 3 ; 2742 divider_val = 3 ;
2953 Fmax = FmaxBin ; 2743 Fmax = FmaxBin ;
2954 Fmin = FminBin ; 2744 Fmin = FminBin ;
@@ -2956,682 +2746,608 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2956 FminBin = 600000000UL ; 2746 FminBin = 600000000UL ;
2957 FmaxBin = 900000000UL ; 2747 FmaxBin = 900000000UL ;
2958 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2748 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2959 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; 2749 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2960 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; 2750 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2961 divider_val = 2 ; 2751 divider_val = 2 ;
2962 Fmax = FmaxBin ; 2752 Fmax = FmaxBin ;
2963 Fmin = FminBin ; 2753 Fmin = FminBin ;
2964 } 2754 }
2965 2755
2966 // TG_DIV_VAL 2756 /* TG_DIV_VAL */
2967 tg_divval = (state->TG_LO*divider_val/100000) 2757 tg_divval = (state->TG_LO*divider_val/100000) *
2968 *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; 2758 (MXL_Ceiling(state->Fxtal, 1000000) * 100) /
2969 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; 2759 (state->Fxtal/1000);
2760
2761 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2970 2762
2971 if (state->TG_LO > 600000000UL) 2763 if (state->TG_LO > 600000000UL)
2972 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; 2764 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2973 2765
2974 Fmax = 1800000000UL ; 2766 Fmax = 1800000000UL ;
2975 Fmin = 1200000000UL ; 2767 Fmin = 1200000000UL ;
2976 2768
2769 /* prevent overflow of 32 bit unsigned integer, use
2770 * following equation. Edit for v2.6.4
2771 */
2772 /* Fref_TF = Fref_TG * 1000 */
2773 Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000);
2977 2774
2978 2775 /* Fvco = Fvco/10 */
2979 // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 2776 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG;
2980 Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
2981
2982 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10
2983 2777
2984 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; 2778 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
2985 2779
2986 //below equation is same as above but much harder to debug. 2780 /* below equation is same as above but much harder to debug.
2987 //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; 2781 * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) -
2988 2782 * ((state->TG_LO/10000)*divider_val *
2989 2783 * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 *
2990 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; 2784 * Xtal_Int/100) + 8;
2991 2785 */
2992 2786
2787 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2993 2788
2994 //add for 2.6.5 2789 /* add for 2.6.5 Special setting for QAM */
2995 //Special setting for QAM 2790 if (state->Mod_Type == MXL_QAM) {
2996 if(state->Mod_Type == MXL_QAM) 2791 if (state->RF_IN < 680000000)
2997 { 2792 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2998 if(state->RF_IN < 680000000) 2793 else
2999 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; 2794 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
3000 else
3001 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ;
3002 } 2795 }
3003 2796
3004 2797 /* Off Chip Tracking Filter Control */
3005 //remove 20.48MHz setting for 2.6.10 2798 if (state->TF_Type == MXL_TF_OFF) {
3006 2799 /* Tracking Filter Off State; turn off all the banks */
3007 // 2800 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3008 // Off Chip Tracking Filter Control 2801 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3009 // 2802 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
3010 if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks 2803 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
3011 { 2804 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
3012 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
3013 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
3014
3015 status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1
3016 status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2
3017 status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3
3018 } 2805 }
3019 2806
3020 if (state->TF_Type == MXL_TF_C) // Tracking Filter type C 2807 if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ {
3021 { 2808 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3022 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; 2809 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
3023 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 2810
3024 2811 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
3025 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) 2812 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3026 { 2813 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3027 2814 status += MXL_SetGPIO(fe, 3, 0);
3028 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2815 status += MXL_SetGPIO(fe, 1, 1);
3029 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 2816 status += MXL_SetGPIO(fe, 4, 1);
3030 status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On 2817 }
3031 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2818 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
3032 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off 2819 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3033 } 2820 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3034 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) 2821 status += MXL_SetGPIO(fe, 3, 1);
3035 { 2822 status += MXL_SetGPIO(fe, 1, 0);
3036 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2823 status += MXL_SetGPIO(fe, 4, 1);
3037 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 2824 }
3038 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off 2825 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
3039 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 2826 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3040 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off 2827 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3041 } 2828 status += MXL_SetGPIO(fe, 3, 1);
3042 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) 2829 status += MXL_SetGPIO(fe, 1, 0);
3043 { 2830 status += MXL_SetGPIO(fe, 4, 0);
3044 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2831 }
3045 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 2832 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
3046 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off 2833 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3047 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 2834 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3048 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On 2835 status += MXL_SetGPIO(fe, 3, 1);
3049 } 2836 status += MXL_SetGPIO(fe, 1, 1);
3050 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) 2837 status += MXL_SetGPIO(fe, 4, 0);
3051 { 2838 }
3052 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2839 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
3053 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 2840 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3054 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off 2841 status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
3055 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2842 status += MXL_SetGPIO(fe, 3, 1);
3056 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On 2843 status += MXL_SetGPIO(fe, 1, 1);
3057 } 2844 status += MXL_SetGPIO(fe, 4, 0);
3058 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) 2845 }
3059 { 2846 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
3060 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2847 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3061 status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; 2848 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3062 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off 2849 status += MXL_SetGPIO(fe, 3, 1);
3063 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2850 status += MXL_SetGPIO(fe, 1, 1);
3064 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On 2851 status += MXL_SetGPIO(fe, 4, 0);
3065 } 2852 }
3066 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) 2853 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
3067 { 2854 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3068 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2855 status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
3069 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 2856 status += MXL_SetGPIO(fe, 3, 1);
3070 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off 2857 status += MXL_SetGPIO(fe, 1, 1);
3071 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2858 status += MXL_SetGPIO(fe, 4, 1);
3072 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On 2859 }
3073 } 2860 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
3074 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) 2861 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3075 { 2862 status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
3076 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2863 status += MXL_SetGPIO(fe, 3, 1);
3077 status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; 2864 status += MXL_SetGPIO(fe, 1, 1);
3078 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off 2865 status += MXL_SetGPIO(fe, 4, 1);
3079 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2866 }
3080 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off 2867 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
3081 } 2868 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3082 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) 2869 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3083 { 2870 status += MXL_SetGPIO(fe, 3, 1);
3084 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2871 status += MXL_SetGPIO(fe, 1, 1);
3085 status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; 2872 status += MXL_SetGPIO(fe, 4, 1);
3086 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3087 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3088 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3089 }
3090 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
3091 {
3092 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3093 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3094 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3095 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3096 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
3097 } 2873 }
3098 } 2874 }
3099 2875
3100 if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only 2876 if (state->TF_Type == MXL_TF_C_H) {
3101 { 2877
3102 printk("%s() CH filter\n", __func__); 2878 /* Tracking Filter type C-H for Hauppauge only */
3103 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 2879 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
3104 2880
3105 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) 2881 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) {
3106 { 2882 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3107 2883 status += MXL_SetGPIO(fe, 4, 0);
3108 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2884 status += MXL_SetGPIO(fe, 3, 1);
3109 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 2885 status += MXL_SetGPIO(fe, 1, 1);
3110 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off 2886 }
3111 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off 2887 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) {
3112 } 2888 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3113 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) 2889 status += MXL_SetGPIO(fe, 4, 1);
3114 { 2890 status += MXL_SetGPIO(fe, 3, 0);
3115 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2891 status += MXL_SetGPIO(fe, 1, 1);
3116 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2892 }
3117 status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On 2893 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) {
3118 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off 2894 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3119 } 2895 status += MXL_SetGPIO(fe, 4, 1);
3120 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) 2896 status += MXL_SetGPIO(fe, 3, 0);
3121 { 2897 status += MXL_SetGPIO(fe, 1, 0);
3122 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2898 }
3123 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2899 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) {
3124 status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On 2900 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3125 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On 2901 status += MXL_SetGPIO(fe, 4, 1);
3126 } 2902 status += MXL_SetGPIO(fe, 3, 1);
3127 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) 2903 status += MXL_SetGPIO(fe, 1, 0);
3128 { 2904 }
3129 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 2905 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) {
3130 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2906 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3131 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off 2907 status += MXL_SetGPIO(fe, 4, 1);
3132 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On 2908 status += MXL_SetGPIO(fe, 3, 1);
3133 } 2909 status += MXL_SetGPIO(fe, 1, 0);
3134 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) 2910 }
3135 { 2911 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) {
3136 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2912 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3137 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2913 status += MXL_SetGPIO(fe, 4, 1);
3138 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off 2914 status += MXL_SetGPIO(fe, 3, 1);
3139 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On 2915 status += MXL_SetGPIO(fe, 1, 0);
3140 } 2916 }
3141 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) 2917 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) {
3142 { 2918 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3143 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2919 status += MXL_SetGPIO(fe, 4, 1);
3144 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2920 status += MXL_SetGPIO(fe, 3, 1);
3145 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off 2921 status += MXL_SetGPIO(fe, 1, 1);
3146 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On 2922 }
3147 } 2923 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) {
3148 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) 2924 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3149 { 2925 status += MXL_SetGPIO(fe, 4, 1);
3150 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2926 status += MXL_SetGPIO(fe, 3, 1);
3151 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2927 status += MXL_SetGPIO(fe, 1, 1);
3152 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off 2928 }
3153 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off 2929 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) {
3154 } 2930 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3155 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) 2931 status += MXL_SetGPIO(fe, 4, 1);
3156 { 2932 status += MXL_SetGPIO(fe, 3, 1);
3157 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 2933 status += MXL_SetGPIO(fe, 1, 1);
3158 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3159 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3160 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3161 }
3162 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
3163 {
3164 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3165 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3166 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3167 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
3168 } 2934 }
3169 } 2935 }
3170 2936
3171 if (state->TF_Type == MXL_TF_D) // Tracking Filter type D 2937 if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */
3172 { 2938
3173 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 2939 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3174 2940
3175 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) 2941 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3176 { 2942 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3177 2943 status += MXL_SetGPIO(fe, 4, 0);
3178 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 2944 status += MXL_SetGPIO(fe, 1, 1);
3179 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 2945 status += MXL_SetGPIO(fe, 3, 1);
3180 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2946 }
3181 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 2947 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3182 } 2948 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3183 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) 2949 status += MXL_SetGPIO(fe, 4, 0);
3184 { 2950 status += MXL_SetGPIO(fe, 1, 0);
3185 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 2951 status += MXL_SetGPIO(fe, 3, 1);
3186 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 2952 }
3187 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 2953 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3188 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 2954 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3189 } 2955 status += MXL_SetGPIO(fe, 4, 1);
3190 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) 2956 status += MXL_SetGPIO(fe, 1, 0);
3191 { 2957 status += MXL_SetGPIO(fe, 3, 1);
3192 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 2958 }
3193 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2959 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3194 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 2960 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3195 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 2961 status += MXL_SetGPIO(fe, 4, 1);
3196 } 2962 status += MXL_SetGPIO(fe, 1, 0);
3197 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) 2963 status += MXL_SetGPIO(fe, 3, 0);
3198 { 2964 }
3199 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 2965 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3200 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2966 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3201 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 2967 status += MXL_SetGPIO(fe, 4, 1);
3202 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 2968 status += MXL_SetGPIO(fe, 1, 1);
3203 } 2969 status += MXL_SetGPIO(fe, 3, 0);
3204 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) 2970 }
3205 { 2971 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3206 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 2972 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3207 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2973 status += MXL_SetGPIO(fe, 4, 1);
3208 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2974 status += MXL_SetGPIO(fe, 1, 1);
3209 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 2975 status += MXL_SetGPIO(fe, 3, 0);
3210 } 2976 }
3211 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) 2977 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3212 { 2978 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3213 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 2979 status += MXL_SetGPIO(fe, 4, 1);
3214 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 2980 status += MXL_SetGPIO(fe, 1, 1);
3215 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 2981 status += MXL_SetGPIO(fe, 3, 1);
3216 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3217 }
3218 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
3219 {
3220 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3221 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3222 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3223 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3224 } 2982 }
3225 } 2983 }
3226 2984
3227 2985 if (state->TF_Type == MXL_TF_D_L) {
3228 if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 2986
3229 { 2987 /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */
3230 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 2988 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
3231 2989
3232 // if UHF and terrestrial => Turn off Tracking Filter 2990 /* if UHF and terrestrial => Turn off Tracking Filter */
3233 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) 2991 if (state->RF_IN >= 471000000 &&
3234 { 2992 (state->RF_IN - 471000000)%6000000 != 0) {
3235 // Turn off all the banks 2993 /* Turn off all the banks */
3236 status += MXL_SetGPIO(fe, 3, 1) ; 2994 status += MXL_SetGPIO(fe, 3, 1);
3237 status += MXL_SetGPIO(fe, 1, 1) ; 2995 status += MXL_SetGPIO(fe, 1, 1);
3238 status += MXL_SetGPIO(fe, 4, 1) ; 2996 status += MXL_SetGPIO(fe, 4, 1);
3239 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; 2997 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3240 2998 status += MXL_ControlWrite(fe, AGC_IF, 10);
3241 status += MXL_ControlWrite(fe, AGC_IF, 10) ; 2999 } else {
3242 } 3000 /* if VHF or cable => Turn on Tracking Filter */
3243 3001 if (state->RF_IN >= 43000000 &&
3244 else // if VHF or cable => Turn on Tracking Filter 3002 state->RF_IN < 140000000) {
3245 { 3003
3246 if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) 3004 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3247 { 3005 status += MXL_SetGPIO(fe, 4, 1);
3248 3006 status += MXL_SetGPIO(fe, 1, 1);
3249 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 3007 status += MXL_SetGPIO(fe, 3, 0);
3250 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3251 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3252 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
3253 } 3008 }
3254 if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) 3009 if (state->RF_IN >= 140000000 &&
3255 { 3010 state->RF_IN < 240000000) {
3256 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 3011 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3257 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On 3012 status += MXL_SetGPIO(fe, 4, 1);
3258 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3013 status += MXL_SetGPIO(fe, 1, 0);
3259 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off 3014 status += MXL_SetGPIO(fe, 3, 0);
3260 } 3015 }
3261 if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) 3016 if (state->RF_IN >= 240000000 &&
3262 { 3017 state->RF_IN < 340000000) {
3263 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 3018 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3264 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off 3019 status += MXL_SetGPIO(fe, 4, 0);
3265 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On 3020 status += MXL_SetGPIO(fe, 1, 1);
3266 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off 3021 status += MXL_SetGPIO(fe, 3, 0);
3267 } 3022 }
3268 if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) 3023 if (state->RF_IN >= 340000000 &&
3269 { 3024 state->RF_IN < 430000000) {
3270 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off 3025 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3271 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off 3026 status += MXL_SetGPIO(fe, 4, 0);
3272 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3027 status += MXL_SetGPIO(fe, 1, 0);
3273 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On 3028 status += MXL_SetGPIO(fe, 3, 1);
3274 } 3029 }
3275 if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) 3030 if (state->RF_IN >= 430000000 &&
3276 { 3031 state->RF_IN < 470000000) {
3277 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off 3032 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3278 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3033 status += MXL_SetGPIO(fe, 4, 1);
3279 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off 3034 status += MXL_SetGPIO(fe, 1, 0);
3280 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On 3035 status += MXL_SetGPIO(fe, 3, 1);
3281 } 3036 }
3282 if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) 3037 if (state->RF_IN >= 470000000 &&
3283 { 3038 state->RF_IN < 570000000) {
3284 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 3039 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3285 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off 3040 status += MXL_SetGPIO(fe, 4, 0);
3286 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off 3041 status += MXL_SetGPIO(fe, 1, 0);
3287 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On 3042 status += MXL_SetGPIO(fe, 3, 1);
3288 } 3043 }
3289 if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) 3044 if (state->RF_IN >= 570000000 &&
3290 { 3045 state->RF_IN < 620000000) {
3291 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On 3046 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3292 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off 3047 status += MXL_SetGPIO(fe, 4, 0);
3293 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3048 status += MXL_SetGPIO(fe, 1, 1);
3294 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq 3049 status += MXL_SetGPIO(fe, 3, 1);
3295 } 3050 }
3296 if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) 3051 if (state->RF_IN >= 620000000 &&
3297 { 3052 state->RF_IN < 760000000) {
3298 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 3053 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3299 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off 3054 status += MXL_SetGPIO(fe, 4, 0);
3300 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3055 status += MXL_SetGPIO(fe, 1, 1);
3301 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3056 status += MXL_SetGPIO(fe, 3, 1);
3302 } 3057 }
3303 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) 3058 if (state->RF_IN >= 760000000 &&
3304 { 3059 state->RF_IN <= 900000000) {
3305 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On 3060 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3306 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3061 status += MXL_SetGPIO(fe, 4, 1);
3307 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3062 status += MXL_SetGPIO(fe, 1, 1);
3308 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3063 status += MXL_SetGPIO(fe, 3, 1);
3309 } 3064 }
3310 } 3065 }
3311 } 3066 }
3312 3067
3313 if (state->TF_Type == MXL_TF_E) // Tracking Filter type E 3068 if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ {
3314 { 3069
3315 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3070 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3316 3071
3317 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) 3072 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3318 { 3073 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3319 3074 status += MXL_SetGPIO(fe, 4, 0);
3320 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3075 status += MXL_SetGPIO(fe, 1, 1);
3321 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3076 status += MXL_SetGPIO(fe, 3, 1);
3322 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3077 }
3323 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3078 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3324 } 3079 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3325 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) 3080 status += MXL_SetGPIO(fe, 4, 0);
3326 { 3081 status += MXL_SetGPIO(fe, 1, 0);
3327 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3082 status += MXL_SetGPIO(fe, 3, 1);
3328 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3083 }
3329 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3084 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) {
3330 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3085 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3331 } 3086 status += MXL_SetGPIO(fe, 4, 1);
3332 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) 3087 status += MXL_SetGPIO(fe, 1, 0);
3333 { 3088 status += MXL_SetGPIO(fe, 3, 1);
3334 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3089 }
3335 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3090 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) {
3336 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3091 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3337 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3092 status += MXL_SetGPIO(fe, 4, 1);
3338 } 3093 status += MXL_SetGPIO(fe, 1, 0);
3339 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) 3094 status += MXL_SetGPIO(fe, 3, 0);
3340 { 3095 }
3341 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3096 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) {
3342 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3097 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3343 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3098 status += MXL_SetGPIO(fe, 4, 1);
3344 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3099 status += MXL_SetGPIO(fe, 1, 1);
3345 } 3100 status += MXL_SetGPIO(fe, 3, 0);
3346 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) 3101 }
3347 { 3102 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3348 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3103 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3349 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3104 status += MXL_SetGPIO(fe, 4, 1);
3350 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3105 status += MXL_SetGPIO(fe, 1, 1);
3351 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3106 status += MXL_SetGPIO(fe, 3, 0);
3352 } 3107 }
3353 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) 3108 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) {
3354 { 3109 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3355 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 3110 status += MXL_SetGPIO(fe, 4, 1);
3356 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3111 status += MXL_SetGPIO(fe, 1, 1);
3357 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3112 status += MXL_SetGPIO(fe, 3, 1);
3358 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3359 }
3360 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
3361 {
3362 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3363 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3364 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3365 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3366 } 3113 }
3367 } 3114 }
3368 3115
3369 if (state->TF_Type == MXL_TF_F) // Tracking Filter type F 3116 if (state->TF_Type == MXL_TF_F) {
3370 { 3117
3371 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3118 /* Tracking Filter type F */
3372 3119 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3373 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) 3120
3374 { 3121 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) {
3375 3122 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3376 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3123 status += MXL_SetGPIO(fe, 4, 0);
3377 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3124 status += MXL_SetGPIO(fe, 1, 1);
3378 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3125 status += MXL_SetGPIO(fe, 3, 1);
3379 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3126 }
3380 } 3127 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) {
3381 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) 3128 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3382 { 3129 status += MXL_SetGPIO(fe, 4, 0);
3383 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3130 status += MXL_SetGPIO(fe, 1, 0);
3384 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3131 status += MXL_SetGPIO(fe, 3, 1);
3385 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3132 }
3386 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3133 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) {
3387 } 3134 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3388 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) 3135 status += MXL_SetGPIO(fe, 4, 1);
3389 { 3136 status += MXL_SetGPIO(fe, 1, 0);
3390 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3137 status += MXL_SetGPIO(fe, 3, 1);
3391 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3138 }
3392 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3139 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) {
3393 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3140 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3394 } 3141 status += MXL_SetGPIO(fe, 4, 1);
3395 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) 3142 status += MXL_SetGPIO(fe, 1, 0);
3396 { 3143 status += MXL_SetGPIO(fe, 3, 0);
3397 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3144 }
3398 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3145 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) {
3399 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3146 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3400 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3147 status += MXL_SetGPIO(fe, 4, 1);
3401 } 3148 status += MXL_SetGPIO(fe, 1, 1);
3402 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) 3149 status += MXL_SetGPIO(fe, 3, 0);
3403 { 3150 }
3404 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3151 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) {
3405 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3152 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3406 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3153 status += MXL_SetGPIO(fe, 4, 1);
3407 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3154 status += MXL_SetGPIO(fe, 1, 1);
3408 } 3155 status += MXL_SetGPIO(fe, 3, 0);
3409 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) 3156 }
3410 { 3157 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) {
3411 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 3158 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3412 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3159 status += MXL_SetGPIO(fe, 4, 1);
3413 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3160 status += MXL_SetGPIO(fe, 1, 1);
3414 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3161 status += MXL_SetGPIO(fe, 3, 1);
3415 }
3416 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000)
3417 {
3418 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3419 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3420 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3421 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3422 } 3162 }
3423 } 3163 }
3424 3164
3425 if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 3165 if (state->TF_Type == MXL_TF_E_2) {
3426 { 3166
3427 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3167 /* Tracking Filter type E_2 */
3428 3168 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3429 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) 3169
3430 { 3170 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3431 3171 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3432 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3172 status += MXL_SetGPIO(fe, 4, 0);
3433 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3173 status += MXL_SetGPIO(fe, 1, 1);
3434 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3174 status += MXL_SetGPIO(fe, 3, 1);
3435 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3175 }
3436 } 3176 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3437 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) 3177 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3438 { 3178 status += MXL_SetGPIO(fe, 4, 0);
3439 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3179 status += MXL_SetGPIO(fe, 1, 0);
3440 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3180 status += MXL_SetGPIO(fe, 3, 1);
3441 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3181 }
3442 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3182 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3443 } 3183 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3444 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) 3184 status += MXL_SetGPIO(fe, 4, 1);
3445 { 3185 status += MXL_SetGPIO(fe, 1, 0);
3446 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3186 status += MXL_SetGPIO(fe, 3, 1);
3447 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3187 }
3448 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3188 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3449 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3189 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3450 } 3190 status += MXL_SetGPIO(fe, 4, 1);
3451 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) 3191 status += MXL_SetGPIO(fe, 1, 0);
3452 { 3192 status += MXL_SetGPIO(fe, 3, 0);
3453 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3193 }
3454 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3194 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3455 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3195 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3456 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3196 status += MXL_SetGPIO(fe, 4, 1);
3457 } 3197 status += MXL_SetGPIO(fe, 1, 1);
3458 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) 3198 status += MXL_SetGPIO(fe, 3, 0);
3459 { 3199 }
3460 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3200 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3461 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3201 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3462 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3202 status += MXL_SetGPIO(fe, 4, 1);
3463 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3203 status += MXL_SetGPIO(fe, 1, 1);
3464 } 3204 status += MXL_SetGPIO(fe, 3, 0);
3465 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) 3205 }
3466 { 3206 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3467 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 3207 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3468 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3208 status += MXL_SetGPIO(fe, 4, 1);
3469 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3209 status += MXL_SetGPIO(fe, 1, 1);
3470 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3210 status += MXL_SetGPIO(fe, 3, 1);
3471 }
3472 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
3473 {
3474 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3475 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3476 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3477 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3478 } 3211 }
3479 } 3212 }
3480 3213
3481 if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 3214 if (state->TF_Type == MXL_TF_G) {
3482 { 3215
3483 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3216 /* Tracking Filter type G add for v2.6.8 */
3484 3217 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3485 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) 3218
3486 { 3219 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) {
3487 3220
3488 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3221 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3489 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3222 status += MXL_SetGPIO(fe, 4, 0);
3490 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3223 status += MXL_SetGPIO(fe, 1, 1);
3491 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3224 status += MXL_SetGPIO(fe, 3, 1);
3492 } 3225 }
3493 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) 3226 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) {
3494 { 3227 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3495 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3228 status += MXL_SetGPIO(fe, 4, 0);
3496 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3229 status += MXL_SetGPIO(fe, 1, 0);
3497 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3230 status += MXL_SetGPIO(fe, 3, 1);
3498 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3231 }
3499 } 3232 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) {
3500 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) 3233 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3501 { 3234 status += MXL_SetGPIO(fe, 4, 1);
3502 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3235 status += MXL_SetGPIO(fe, 1, 0);
3503 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3236 status += MXL_SetGPIO(fe, 3, 1);
3504 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3237 }
3505 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3238 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3506 } 3239 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3507 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) 3240 status += MXL_SetGPIO(fe, 4, 1);
3508 { 3241 status += MXL_SetGPIO(fe, 1, 0);
3509 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3242 status += MXL_SetGPIO(fe, 3, 0);
3510 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3243 }
3511 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3244 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) {
3512 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3245 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3513 } 3246 status += MXL_SetGPIO(fe, 4, 1);
3514 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 3247 status += MXL_SetGPIO(fe, 1, 0);
3515 { 3248 status += MXL_SetGPIO(fe, 3, 1);
3516 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 3249 }
3517 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On 3250 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) {
3518 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off 3251 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3519 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3252 status += MXL_SetGPIO(fe, 4, 1);
3520 } 3253 status += MXL_SetGPIO(fe, 1, 1);
3521 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) 3254 status += MXL_SetGPIO(fe, 3, 0);
3522 { 3255 }
3523 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3256 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) {
3524 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3257 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3525 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3258 status += MXL_SetGPIO(fe, 4, 1);
3526 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3259 status += MXL_SetGPIO(fe, 1, 1);
3527 } 3260 status += MXL_SetGPIO(fe, 3, 0);
3528 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) 3261 }
3529 { 3262 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) {
3530 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 3263 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3531 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3264 status += MXL_SetGPIO(fe, 4, 1);
3532 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3265 status += MXL_SetGPIO(fe, 1, 1);
3533 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3266 status += MXL_SetGPIO(fe, 3, 1);
3534 }
3535 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000)
3536 {
3537 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3538 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3539 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3540 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3541 } 3267 }
3542 } 3268 }
3543 3269
3544 if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 3270 if (state->TF_Type == MXL_TF_E_NA) {
3545 { 3271
3546 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3272 /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */
3547 3273 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3548 // if UHF and terrestrial=> Turn off Tracking Filter 3274
3549 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) 3275 /* if UHF and terrestrial=> Turn off Tracking Filter */
3550 { 3276 if (state->RF_IN >= 471000000 &&
3551 // Turn off all the banks 3277 (state->RF_IN - 471000000)%6000000 != 0) {
3552 status += MXL_SetGPIO(fe, 3, 1) ; 3278
3553 status += MXL_SetGPIO(fe, 1, 1) ; 3279 /* Turn off all the banks */
3554 status += MXL_SetGPIO(fe, 4, 1) ; 3280 status += MXL_SetGPIO(fe, 3, 1);
3555 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; 3281 status += MXL_SetGPIO(fe, 1, 1);
3556 3282 status += MXL_SetGPIO(fe, 4, 1);
3557 //2.6.12 3283 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3558 //Turn on RSSI 3284
3559 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; 3285 /* 2.6.12 Turn on RSSI */
3560 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; 3286 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3561 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; 3287 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3562 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; 3288 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3563 3289 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3564 // RSSI reference point 3290
3565 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; 3291 /* RSSI reference point */
3566 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; 3292 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3567 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; 3293 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3568 3294 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3569 3295
3570 //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on 3296 /* following parameter is from analog OTA mode,
3571 3297 * can be change to seek better performance */
3572 //following parameter is from analog OTA mode, can be change to seek better performance 3298 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3573 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; 3299 } else {
3574 } 3300 /* if VHF or Cable => Turn on Tracking Filter */
3575 3301
3576 else //if VHF or Cable => Turn on Tracking Filter 3302 /* 2.6.12 Turn off RSSI */
3577 { 3303 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3578 //2.6.12 3304
3579 //Turn off RSSI 3305 /* change back from above condition */
3580 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; 3306 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3581 3307
3582 //change back from above condition 3308
3583 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; 3309 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) {
3584 3310
3585 3311 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3586 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) 3312 status += MXL_SetGPIO(fe, 4, 0);
3587 { 3313 status += MXL_SetGPIO(fe, 1, 1);
3588 3314 status += MXL_SetGPIO(fe, 3, 1);
3589 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3315 }
3590 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3316 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) {
3591 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3317 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3592 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3318 status += MXL_SetGPIO(fe, 4, 0);
3593 } 3319 status += MXL_SetGPIO(fe, 1, 0);
3594 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) 3320 status += MXL_SetGPIO(fe, 3, 1);
3595 { 3321 }
3596 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3322 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) {
3597 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On 3323 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3598 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3324 status += MXL_SetGPIO(fe, 4, 1);
3599 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3325 status += MXL_SetGPIO(fe, 1, 0);
3600 } 3326 status += MXL_SetGPIO(fe, 3, 1);
3601 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) 3327 }
3602 { 3328 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) {
3603 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3329 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3604 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3330 status += MXL_SetGPIO(fe, 4, 1);
3605 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3331 status += MXL_SetGPIO(fe, 1, 0);
3606 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off 3332 status += MXL_SetGPIO(fe, 3, 0);
3607 } 3333 }
3608 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) 3334 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) {
3609 { 3335 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3610 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3336 status += MXL_SetGPIO(fe, 4, 1);
3611 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3337 status += MXL_SetGPIO(fe, 1, 1);
3612 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On 3338 status += MXL_SetGPIO(fe, 3, 0);
3613 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3339 }
3614 } 3340 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) {
3615 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) 3341 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3616 { 3342 status += MXL_SetGPIO(fe, 4, 1);
3617 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off 3343 status += MXL_SetGPIO(fe, 1, 1);
3618 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off 3344 status += MXL_SetGPIO(fe, 3, 0);
3619 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off 3345 }
3620 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On 3346 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) {
3621 } 3347 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3622 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) 3348 status += MXL_SetGPIO(fe, 4, 1);
3623 { 3349 status += MXL_SetGPIO(fe, 1, 1);
3624 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On 3350 status += MXL_SetGPIO(fe, 3, 1);
3625 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3626 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3627 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
3628 }
3629 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
3630 {
3631 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3632 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3633 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3634 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
3635 } 3351 }
3636 } 3352 }
3637 } 3353 }
@@ -3679,72 +3395,24 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3679 return status; 3395 return status;
3680} 3396}
3681 3397
3682///////////////////////////////////////////////////////////////////////////////
3683// //
3684// Function: MXL_ControlWrite //
3685// //
3686// Description: Update control name value //
3687// //
3688// Globals: //
3689// NONE //
3690// //
3691// Functions used: //
3692// MXL_ControlWrite( Tuner, controlName, value, Group ) //
3693// //
3694// Inputs: //
3695// Tuner : Tuner structure //
3696// ControlName : Control name to be updated //
3697// value : Value to be written //
3698// //
3699// Outputs: //
3700// Tuner : Tuner structure defined at higher level //
3701// //
3702// Return: //
3703// 0 : Successful write //
3704// >0 : Value exceed maximum allowed for control number //
3705// //
3706///////////////////////////////////////////////////////////////////////////////
3707u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) 3398u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3708{ 3399{
3709 u16 status = 0; 3400 u16 status = 0;
3710 3401
3711 /* Will write ALL Matching Control Name */ 3402 /* Will write ALL Matching Control Name */
3712 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ 3403 /* Write Matching INIT Control */
3713 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ 3404 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3405 /* Write Matching CH Control */
3406 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3714#ifdef _MXL_INTERNAL 3407#ifdef _MXL_INTERNAL
3715 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ 3408 /* Write Matching MXL Control */
3409 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3716#endif 3410#endif
3717 return status; 3411 return status;
3718} 3412}
3719 3413
3720/////////////////////////////////////////////////////////////////////////////// 3414u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value,
3721// // 3415 u16 controlGroup)
3722// Function: MXL_ControlWrite //
3723// //
3724// Description: Update control name value //
3725// //
3726// Globals: //
3727// NONE //
3728// //
3729// Functions used: //
3730// strcmp //
3731// //
3732// Inputs: //
3733// Tuner_struct: structure defined at higher level //
3734// ControlName : Control Name //
3735// value : Value Assigned to Control Name //
3736// controlGroup : Control Register Group //
3737// //
3738// Outputs: //
3739// NONE //
3740// //
3741// Return: //
3742// 0 : Successful write //
3743// 1 : Value exceed maximum allowed for control name //
3744// 2 : Control name not found //
3745// //
3746///////////////////////////////////////////////////////////////////////////////
3747u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup)
3748{ 3416{
3749 struct mxl5005s_state *state = fe->tuner_priv; 3417 struct mxl5005s_state *state = fe->tuner_priv;
3750 u16 i, j, k; 3418 u16 i, j, k;
@@ -3763,13 +3431,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
3763 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); 3431 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3764 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), 3432 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3765 (u8)(state->Init_Ctrl[i].bit[j]), 3433 (u8)(state->Init_Ctrl[i].bit[j]),
3766 (u8)((value>>j) & 0x01) ); 3434 (u8)((value>>j) & 0x01));
3767 } 3435 }
3768 ctrlVal = 0; 3436 ctrlVal = 0;
3769 for (k = 0; k < state->Init_Ctrl[i].size; k++) 3437 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3770 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); 3438 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3771 } 3439 } else
3772 else
3773 return -1; 3440 return -1;
3774 } 3441 }
3775 } 3442 }
@@ -3778,7 +3445,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
3778 3445
3779 for (i = 0; i < state->CH_Ctrl_Num; i++) { 3446 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3780 3447
3781 if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { 3448 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3782 3449
3783 highLimit = 1 << state->CH_Ctrl[i].size; 3450 highLimit = 1 << state->CH_Ctrl[i].size;
3784 if (value < highLimit) { 3451 if (value < highLimit) {
@@ -3786,13 +3453,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
3786 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); 3453 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3787 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), 3454 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3788 (u8)(state->CH_Ctrl[i].bit[j]), 3455 (u8)(state->CH_Ctrl[i].bit[j]),
3789 (u8)((value>>j) & 0x01) ); 3456 (u8)((value>>j) & 0x01));
3790 } 3457 }
3791 ctrlVal = 0; 3458 ctrlVal = 0;
3792 for (k = 0; k < state->CH_Ctrl[i].size; k++) 3459 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3793 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); 3460 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3794 } 3461 } else
3795 else
3796 return -1; 3462 return -1;
3797 } 3463 }
3798 } 3464 }
@@ -3802,21 +3468,20 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
3802 3468
3803 for (i = 0; i < state->MXL_Ctrl_Num; i++) { 3469 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3804 3470
3805 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { 3471 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3806 3472
3807 highLimit = (1 << state->MXL_Ctrl[i].size) ; 3473 highLimit = (1 << state->MXL_Ctrl[i].size);
3808 if (value < highLimit) { 3474 if (value < highLimit) {
3809 for (j = 0; j < state->MXL_Ctrl[i].size; j++) { 3475 for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3810 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); 3476 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3811 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), 3477 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3812 (u8)(state->MXL_Ctrl[i].bit[j]), 3478 (u8)(state->MXL_Ctrl[i].bit[j]),
3813 (u8)((value>>j) & 0x01) ); 3479 (u8)((value>>j) & 0x01));
3814 } 3480 }
3815 ctrlVal = 0; 3481 ctrlVal = 0;
3816 for(k = 0; k < state->MXL_Ctrl[i].size; k++) 3482 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3817 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); 3483 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k);
3818 } 3484 } else
3819 else
3820 return -1; 3485 return -1;
3821 } 3486 }
3822 } 3487 }
@@ -3825,31 +3490,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
3825 return 0 ; /* successful return */ 3490 return 0 ; /* successful return */
3826} 3491}
3827 3492
3828///////////////////////////////////////////////////////////////////////////////
3829// //
3830// Function: MXL_RegWrite //
3831// //
3832// Description: Update tuner register value //
3833// //
3834// Globals: //
3835// NONE //
3836// //
3837// Functions used: //
3838// NONE //
3839// //
3840// Inputs: //
3841// Tuner_struct: structure defined at higher level //
3842// RegNum : Register address to be assigned a value //
3843// RegVal : Register value to write //
3844// //
3845// Outputs: //
3846// NONE //
3847// //
3848// Return: //
3849// 0 : Successful write //
3850// -1 : Invalid Register Address //
3851// //
3852///////////////////////////////////////////////////////////////////////////////
3853u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) 3493u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3854{ 3494{
3855 struct mxl5005s_state *state = fe->tuner_priv; 3495 struct mxl5005s_state *state = fe->tuner_priv;
@@ -3865,37 +3505,13 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3865 return 1; 3505 return 1;
3866} 3506}
3867 3507
3868///////////////////////////////////////////////////////////////////////////////
3869// //
3870// Function: MXL_RegRead //
3871// //
3872// Description: Retrieve tuner register value //
3873// //
3874// Globals: //
3875// NONE //
3876// //
3877// Functions used: //
3878// NONE //
3879// //
3880// Inputs: //
3881// Tuner_struct: structure defined at higher level //
3882// RegNum : Register address to be assigned a value //
3883// //
3884// Outputs: //
3885// RegVal : Retrieved register value //
3886// //
3887// Return: //
3888// 0 : Successful read //
3889// -1 : Invalid Register Address //
3890// //
3891///////////////////////////////////////////////////////////////////////////////
3892u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) 3508u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3893{ 3509{
3894 struct mxl5005s_state *state = fe->tuner_priv; 3510 struct mxl5005s_state *state = fe->tuner_priv;
3895 int i ; 3511 int i ;
3896 3512
3897 for (i = 0; i < 104; i++) { 3513 for (i = 0; i < 104; i++) {
3898 if (RegNum == state->TunerRegs[i].Reg_Num ) { 3514 if (RegNum == state->TunerRegs[i].Reg_Num) {
3899 *RegVal = (u8)(state->TunerRegs[i].Reg_Val); 3515 *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3900 return 0; 3516 return 0;
3901 } 3517 }
@@ -3904,27 +3520,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3904 return 1; 3520 return 1;
3905} 3521}
3906 3522
3907///////////////////////////////////////////////////////////////////////////////
3908// //
3909// Function: MXL_ControlRead //
3910// //
3911// Description: Retrieve the control value based on the control name //
3912// //
3913// Globals: //
3914// NONE //
3915// //
3916// Inputs: //
3917// Tuner_struct : structure defined at higher level //
3918// ControlName : Control Name //
3919// //
3920// Outputs: //
3921// value : returned control value //
3922// //
3923// Return: //
3924// 0 : Successful read //
3925// -1 : Invalid control name //
3926// //
3927///////////////////////////////////////////////////////////////////////////////
3928u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) 3523u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3929{ 3524{
3930 struct mxl5005s_state *state = fe->tuner_priv; 3525 struct mxl5005s_state *state = fe->tuner_priv;
@@ -3937,7 +3532,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3937 3532
3938 ctrlVal = 0; 3533 ctrlVal = 0;
3939 for (k = 0; k < state->Init_Ctrl[i].size; k++) 3534 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3940 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); 3535 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k);
3941 *value = ctrlVal; 3536 *value = ctrlVal;
3942 return 0; 3537 return 0;
3943 } 3538 }
@@ -3973,30 +3568,8 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3973 return 1; 3568 return 1;
3974} 3569}
3975 3570
3976/////////////////////////////////////////////////////////////////////////////// 3571u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum,
3977// // 3572 int *count)
3978// Function: MXL_ControlRegRead //
3979// //
3980// Description: Retrieve the register addresses and count related to a //
3981// a specific control name //
3982// //
3983// Globals: //
3984// NONE //
3985// //
3986// Inputs: //
3987// Tuner_struct : structure defined at higher level //
3988// ControlName : Control Name //
3989// //
3990// Outputs: //
3991// RegNum : returned register address array //
3992// count : returned register count related to a control //
3993// //
3994// Return: //
3995// 0 : Successful read //
3996// -1 : Invalid control name //
3997// //
3998///////////////////////////////////////////////////////////////////////////////
3999u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count)
4000{ 3573{
4001 struct mxl5005s_state *state = fe->tuner_priv; 3574 struct mxl5005s_state *state = fe->tuner_priv;
4002 u16 i, j, k ; 3575 u16 i, j, k ;
@@ -4004,7 +3577,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
4004 3577
4005 for (i = 0; i < state->Init_Ctrl_Num ; i++) { 3578 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
4006 3579
4007 if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { 3580 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
4008 3581
4009 Count = 1; 3582 Count = 1;
4010 RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); 3583 RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]);
@@ -4013,9 +3586,10 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
4013 3586
4014 for (j = 0; j < Count; j++) { 3587 for (j = 0; j < Count; j++) {
4015 3588
4016 if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { 3589 if (state->Init_Ctrl[i].addr[k] !=
3590 RegNum[j]) {
4017 3591
4018 Count ++; 3592 Count++;
4019 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); 3593 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]);
4020 3594
4021 } 3595 }
@@ -4028,18 +3602,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
4028 } 3602 }
4029 for (i = 0; i < state->CH_Ctrl_Num ; i++) { 3603 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
4030 3604
4031 if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { 3605 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
4032 3606
4033 Count = 1; 3607 Count = 1;
4034 RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); 3608 RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]);
4035 3609
4036 for (k = 1; k < state->CH_Ctrl[i].size; k++) { 3610 for (k = 1; k < state->CH_Ctrl[i].size; k++) {
4037 3611
4038 for (j= 0; j<Count; j++) { 3612 for (j = 0; j < Count; j++) {
4039 3613
4040 if (state->CH_Ctrl[i].addr[k] != RegNum[j]) { 3614 if (state->CH_Ctrl[i].addr[k] !=
3615 RegNum[j]) {
4041 3616
4042 Count ++; 3617 Count++;
4043 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); 3618 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]);
4044 3619
4045 } 3620 }
@@ -4052,18 +3627,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
4052#ifdef _MXL_INTERNAL 3627#ifdef _MXL_INTERNAL
4053 for (i = 0; i < state->MXL_Ctrl_Num ; i++) { 3628 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
4054 3629
4055 if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { 3630 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
4056 3631
4057 Count = 1; 3632 Count = 1;
4058 RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); 3633 RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]);
4059 3634
4060 for (k = 1; k < state->MXL_Ctrl[i].size; k++) { 3635 for (k = 1; k < state->MXL_Ctrl[i].size; k++) {
4061 3636
4062 for (j = 0; j<Count; j++) { 3637 for (j = 0; j < Count; j++) {
4063 3638
4064 if (state->MXL_Ctrl[i].addr[k] != RegNum[j]) { 3639 if (state->MXL_Ctrl[i].addr[k] !=
3640 RegNum[j]) {
4065 3641
4066 Count ++; 3642 Count++;
4067 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; 3643 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k];
4068 3644
4069 } 3645 }
@@ -4078,29 +3654,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
4078 return 1; 3654 return 1;
4079} 3655}
4080 3656
4081///////////////////////////////////////////////////////////////////////////////
4082// //
4083// Function: MXL_RegWriteBit //
4084// //
4085// Description: Write a register for specified register address, //
4086// register bit and register bit value //
4087// //
4088// Globals: //
4089// NONE //
4090// //
4091// Inputs: //
4092// Tuner_struct : structure defined at higher level //
4093// address : register address //
4094// bit : register bit number //
4095// bitVal : register bit value //
4096// //
4097// Outputs: //
4098// NONE //
4099// //
4100// Return: //
4101// NONE //
4102// //
4103///////////////////////////////////////////////////////////////////////////////
4104void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) 3657void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
4105{ 3658{
4106 struct mxl5005s_state *state = fe->tuner_priv; 3659 struct mxl5005s_state *state = fe->tuner_priv;
@@ -4125,38 +3678,14 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
4125 } 3678 }
4126} 3679}
4127 3680
4128///////////////////////////////////////////////////////////////////////////////
4129// //
4130// Function: MXL_Ceiling //
4131// //
4132// Description: Complete to closest increment of resolution //
4133// //
4134// Globals: //
4135// NONE //
4136// //
4137// Functions used: //
4138// NONE //
4139// //
4140// Inputs: //
4141// value : Input number to compute //
4142// resolution : Increment step //
4143// //
4144// Outputs: //
4145// NONE //
4146// //
4147// Return: //
4148// Computed value //
4149// //
4150///////////////////////////////////////////////////////////////////////////////
4151u32 MXL_Ceiling(u32 value, u32 resolution) 3681u32 MXL_Ceiling(u32 value, u32 resolution)
4152{ 3682{
4153 return (value/resolution + (value % resolution > 0 ? 1 : 0)); 3683 return (value/resolution + (value % resolution > 0 ? 1 : 0));
4154} 3684}
4155 3685
4156// 3686/* Retrieve the Initialzation Registers */
4157// Retrieve the Initialzation Registers 3687u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
4158// 3688 u8 *RegVal, int *count)
4159u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4160{ 3689{
4161 u16 status = 0; 3690 u16 status = 0;
4162 int i ; 3691 int i ;
@@ -4178,21 +3707,24 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c
4178 return status; 3707 return status;
4179} 3708}
4180 3709
4181u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 3710u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3711 int *count)
4182{ 3712{
4183 u16 status = 0; 3713 u16 status = 0;
4184 int i ; 3714 int i ;
4185 3715
4186//add 77, 166, 167, 168 register for 2.6.12 3716/* add 77, 166, 167, 168 register for 2.6.12 */
4187#ifdef _MXL_PRODUCTION 3717#ifdef _MXL_PRODUCTION
4188 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, 3718 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4189 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; 3719 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4190#else 3720#else
4191 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, 3721 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4192 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; 3722 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4193 //u8 RegAddr[171]; 3723 /*
4194 //for (i=0; i<=170; i++) 3724 u8 RegAddr[171];
4195 // RegAddr[i] = i; 3725 for (i = 0; i <= 170; i++)
3726 RegAddr[i] = i;
3727 */
4196#endif 3728#endif
4197 3729
4198 *count = sizeof(RegAddr) / sizeof(u8); 3730 *count = sizeof(RegAddr) / sizeof(u8);
@@ -4205,7 +3737,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou
4205 return status; 3737 return status;
4206} 3738}
4207 3739
4208u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 3740u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3741 int *count)
4209{ 3742{
4210 u16 status = 0; 3743 u16 status = 0;
4211 int i; 3744 int i;
@@ -4222,7 +3755,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i
4222 return status; 3755 return status;
4223} 3756}
4224 3757
4225u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 3758u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3759 int *count)
4226{ 3760{
4227 u16 status = 0; 3761 u16 status = 0;
4228 int i; 3762 int i;
@@ -4267,23 +3801,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4267 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 3801 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4268 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 3802 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4269 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 3803 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4270 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { 3804 if (state->Mode == 0 && state->IF_Mode == 1) {
3805 /* Analog Low IF Mode */
4271 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3806 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4272 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3807 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4273 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); 3808 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4274 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); 3809 status += MXL_ControlWrite(fe,
3810 CHCAL_FRAC_MOD_RF, 180224);
4275 } 3811 }
4276 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { 3812 if (state->Mode == 0 && state->IF_Mode == 0) {
3813 /* Analog Zero IF Mode */
4277 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3814 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4278 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3815 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4279 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); 3816 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4280 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); 3817 status += MXL_ControlWrite(fe,
3818 CHCAL_FRAC_MOD_RF, 222822);
4281 } 3819 }
4282 if (state->Mode == 1) /* Digital Mode */ { 3820 if (state->Mode == 1) /* Digital Mode */ {
4283 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3821 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4284 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3822 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4285 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); 3823 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4286 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); 3824 status += MXL_ControlWrite(fe,
3825 CHCAL_FRAC_MOD_RF, 229376);
4287 } 3826 }
4288 } 3827 }
4289 3828
@@ -4298,23 +3837,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4298 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3837 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4299 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3838 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4300 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); 3839 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4301 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { 3840 if (state->Mode == 0 && state->IF_Mode == 1) {
3841 /* Analog Low IF Mode */
4302 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3842 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4303 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3843 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4304 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3844 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4305 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); 3845 status += MXL_ControlWrite(fe,
3846 CHCAL_FRAC_MOD_RF, 206438);
4306 } 3847 }
4307 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { 3848 if (state->Mode == 0 && state->IF_Mode == 0) {
3849 /* Analog Zero IF Mode */
4308 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3850 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4309 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3851 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4310 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3852 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4311 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); 3853 status += MXL_ControlWrite(fe,
3854 CHCAL_FRAC_MOD_RF, 206438);
4312 } 3855 }
4313 if (state->Mode == 1) /* Digital Mode */ { 3856 if (state->Mode == 1) /* Digital Mode */ {
4314 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3857 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4315 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3858 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4316 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); 3859 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4317 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); 3860 status += MXL_ControlWrite(fe,
3861 CHCAL_FRAC_MOD_RF, 16384);
4318 } 3862 }
4319 } 3863 }
4320 3864
@@ -4329,23 +3873,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4329 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3873 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4330 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3874 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4331 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3875 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4332 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { 3876 if (state->Mode == 0 && state->IF_Mode == 1) {
3877 /* Analog Low IF Mode */
4333 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3878 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4334 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3879 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4335 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); 3880 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4336 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); 3881 status += MXL_ControlWrite(fe,
3882 CHCAL_FRAC_MOD_RF, 173670);
4337 } 3883 }
4338 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { 3884 if (state->Mode == 0 && state->IF_Mode == 0) {
3885 /* Analog Zero IF Mode */
4339 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3886 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4340 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3887 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4341 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); 3888 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4342 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); 3889 status += MXL_ControlWrite(fe,
3890 CHCAL_FRAC_MOD_RF, 173670);
4343 } 3891 }
4344 if (state->Mode == 1) /* Digital Mode */ { 3892 if (state->Mode == 1) /* Digital Mode */ {
4345 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3893 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4346 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3894 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4347 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3895 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4348 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); 3896 status += MXL_ControlWrite(fe,
3897 CHCAL_FRAC_MOD_RF, 245760);
4349 } 3898 }
4350 } 3899 }
4351 3900
@@ -4360,23 +3909,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4360 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3909 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4361 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3910 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4362 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3911 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4363 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { 3912 if (state->Mode == 0 && state->IF_Mode == 1) {
3913 /* Analog Low IF Mode */
4364 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3914 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4365 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3915 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4366 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3916 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4367 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); 3917 status += MXL_ControlWrite(fe,
3918 CHCAL_FRAC_MOD_RF, 206438);
4368 } 3919 }
4369 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { 3920 if (state->Mode == 0 && state->IF_Mode == 0) {
3921 /* Analog Zero IF Mode */
4370 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3922 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4371 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3923 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4372 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3924 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4373 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); 3925 status += MXL_ControlWrite(fe,
3926 CHCAL_FRAC_MOD_RF, 206438);
4374 } 3927 }
4375 if (state->Mode == 1) /* Digital Mode */ { 3928 if (state->Mode == 1) /* Digital Mode */ {
4376 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3929 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4377 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3930 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4378 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3931 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4379 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); 3932 status += MXL_ControlWrite(fe,
3933 CHCAL_FRAC_MOD_RF, 212992);
4380 } 3934 }
4381 } 3935 }
4382 3936
@@ -4440,7 +3994,7 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
4440 if (latch == 0) 3994 if (latch == 0)
4441 msg.len = 2; 3995 msg.len = 2;
4442 3996
4443 dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); 3997 dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr);
4444 3998
4445 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 3999 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
4446 printk(KERN_WARNING "mxl5005s I2C write failed\n"); 4000 printk(KERN_WARNING "mxl5005s I2C write failed\n");
@@ -4449,7 +4003,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
4449 return 0; 4003 return 0;
4450} 4004}
4451 4005
4452int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) 4006int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable,
4007 u8 len)
4453{ 4008{
4454 int ret = 0, i; 4009 int ret = 0, i;
4455 4010
@@ -4506,7 +4061,8 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth)
4506 return 0; 4061 return 0;
4507} 4062}
4508 4063
4509int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) 4064int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
4065 u32 bandwidth)
4510{ 4066{
4511 struct mxl5005s_state *state = fe->tuner_priv; 4067 struct mxl5005s_state *state = fe->tuner_priv;
4512 struct mxl5005s_config *c = state->config; 4068 struct mxl5005s_config *c = state->config;
@@ -4553,8 +4109,8 @@ static int mxl5005s_set_params(struct dvb_frontend *fe,
4553 case QAM_AUTO: 4109 case QAM_AUTO:
4554 req_mode = MXL_QAM; break; 4110 req_mode = MXL_QAM; break;
4555 } 4111 }
4556 } 4112 } else
4557 else req_mode = MXL_DVBT; 4113 req_mode = MXL_DVBT;
4558 4114
4559 /* Change tuner for new modulation type if reqd */ 4115 /* Change tuner for new modulation type if reqd */
4560 if (req_mode != state->current_mode) { 4116 if (req_mode != state->current_mode) {
@@ -4655,9 +4211,11 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4655 state->i2c = i2c; 4211 state->i2c = i2c;
4656 state->current_mode = MXL_QAM; 4212 state->current_mode = MXL_QAM;
4657 4213
4658 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); 4214 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n",
4215 config->i2c_address);
4659 4216
4660 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); 4217 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4218 sizeof(struct dvb_tuner_ops));
4661 4219
4662 fe->tuner_priv = state; 4220 fe->tuner_priv = state;
4663 return fe; 4221 return fe;
diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h
index 687cf146c2a0..0027d1e03f99 100644
--- a/drivers/media/common/tuners/mxl5005s.h
+++ b/drivers/media/common/tuners/mxl5005s.h
@@ -25,8 +25,8 @@
25 25
26#include <linux/dvb/frontend.h> 26#include <linux/dvb/frontend.h>
27 27
28struct mxl5005s_config 28struct mxl5005s_config {
29{ 29
30 /* 7 bit i2c address */ 30 /* 7 bit i2c address */
31 u8 i2c_address; 31 u8 i2c_address;
32 32
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 18:19:53 -0500