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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-21 01:46:49 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:19:38 -0500
commite1de3d18d4838db333f8278e812c053cb039740a (patch)
treee083aa82bff8e6fde3847dc2483bbb22b4011129 /drivers/media/common
parentd0dcc2da264c1a7b6333fc9f77298e5bea4d0944 (diff)
[media] mt2063: Rewrite read/write logic at the driver
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/common')
-rw-r--r--drivers/media/common/tuners/mt2063.c262
1 files changed, 73 insertions, 189 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index 534e970efaaa..0ae6c1544771 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -1,4 +1,3 @@
1
2#include <linux/init.h> 1#include <linux/init.h>
3#include <linux/kernel.h> 2#include <linux/kernel.h>
4#include <linux/module.h> 3#include <linux/module.h>
@@ -541,15 +540,15 @@ unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
541 return err; 540 return err;
542} 541}
543 542
544/*****************/ 543/*
545 544 * mt2063_write - Write data into the I2C bus
546//i2c operation 545 */
547static int mt2063_writeregs(struct mt2063_state *state, u8 reg1, 546static u32 mt2063_write(struct mt2063_state *state,
548 u8 *data, int len) 547 u8 reg, u8 *data, u32 len)
549{ 548{
549 struct dvb_frontend *fe = state->frontend;
550 int ret; 550 int ret;
551 u8 buf[60]; /* = { reg1, data }; */ 551 u8 buf[60];
552
553 struct i2c_msg msg = { 552 struct i2c_msg msg = {
554 .addr = state->config->tuner_address, 553 .addr = state->config->tuner_address,
555 .flags = 0, 554 .flags = 0,
@@ -557,11 +556,12 @@ static int mt2063_writeregs(struct mt2063_state *state, u8 reg1,
557 .len = len + 1 556 .len = len + 1
558 }; 557 };
559 558
560 msg.buf[0] = reg1; 559 msg.buf[0] = reg;
561 memcpy(msg.buf + 1, data, len); 560 memcpy(msg.buf + 1, data, len);
562 561
563 //printk("mt2063_writeregs state->i2c=%p\n", state->i2c); 562 fe->ops.i2c_gate_ctrl(fe, 1);
564 ret = i2c_transfer(state->i2c, &msg, 1); 563 ret = i2c_transfer(state->i2c, &msg, 1);
564 fe->ops.i2c_gate_ctrl(fe, 0);
565 565
566 if (ret < 0) 566 if (ret < 0)
567 printk("mt2063_writeregs error ret=%d\n", ret); 567 printk("mt2063_writeregs error ret=%d\n", ret);
@@ -569,156 +569,40 @@ static int mt2063_writeregs(struct mt2063_state *state, u8 reg1,
569 return ret; 569 return ret;
570} 570}
571 571
572static int mt2063_read_regs(struct mt2063_state *state, u8 reg1, u8 * b, u8 len) 572/*
573{ 573 * mt2063_read - Read data from the I2C bus
574 int ret; 574 */
575 u8 b0[] = { reg1 }; 575static u32 mt2063_read(struct mt2063_state *state,
576 struct i2c_msg msg[] = {
577 {
578 .addr = state->config->tuner_address,
579 .flags = I2C_M_RD,
580 .buf = b0,
581 .len = 1}, {
582 .addr = state->config->tuner_address,
583 .flags = I2C_M_RD,
584 .buf = b,
585 .len = len}
586 };
587
588 //printk("mt2063_read_regs state->i2c=%p\n", state->i2c);
589 ret = i2c_transfer(state->i2c, msg, 2);
590 if (ret < 0)
591 printk("mt2063_readregs error ret=%d\n", ret);
592
593 return ret;
594}
595
596//context of mt2063_userdef.c <Henry> ======================================
597//#################################################################
598//=================================================================
599/*****************************************************************************
600**
601** Name: MT_WriteSub
602**
603** Description: Write values to device using a two-wire serial bus.
604**
605** Parameters: hUserData - User-specific I/O parameter that was
606** passed to tuner's Open function.
607** addr - device serial bus address (value passed
608** as parameter to MTxxxx_Open)
609** subAddress - serial bus sub-address (Register Address)
610** pData - pointer to the Data to be written to the
611** device
612** cnt - number of bytes/registers to be written
613**
614** Returns: status:
615** MT_OK - No errors
616** MT_COMM_ERR - Serial bus communications error
617** user-defined
618**
619** Notes: This is a callback function that is called from the
620** the tuning algorithm. You MUST provide code for this
621** function to write data using the tuner's 2-wire serial
622** bus.
623**
624** The hUserData parameter is a user-specific argument.
625** If additional arguments are needed for the user's
626** serial bus read/write functions, this argument can be
627** used to supply the necessary information.
628** The hUserData parameter is initialized in the tuner's Open
629** function.
630**
631** Revision History:
632**
633** SCR Date Author Description
634** -------------------------------------------------------------------------
635** N/A 03-25-2004 DAD Original
636**
637*****************************************************************************/
638static u32 MT2063_WriteSub(struct mt2063_state *state,
639 u8 subAddress, u8 *pData, u32 cnt)
640{
641 u32 status = 0; /* Status to be returned */
642 struct dvb_frontend *fe = state->frontend;
643
644 /*
645 ** ToDo: Add code here to implement a serial-bus write
646 ** operation to the MTxxxx tuner. If successful,
647 ** return MT_OK.
648 */
649
650 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge
651
652 if (mt2063_writeregs(state, subAddress, pData, cnt) < 0) {
653 status = -EINVAL;
654 }
655 fe->ops.i2c_gate_ctrl(fe, 0); //I2C bypass drxk3926 close i2c bridge
656
657 return (status);
658}
659
660/*****************************************************************************
661**
662** Name: MT_ReadSub
663**
664** Description: Read values from device using a two-wire serial bus.
665**
666** Parameters: hUserData - User-specific I/O parameter that was
667** passed to tuner's Open function.
668** addr - device serial bus address (value passed
669** as parameter to MTxxxx_Open)
670** subAddress - serial bus sub-address (Register Address)
671** pData - pointer to the Data to be written to the
672** device
673** cnt - number of bytes/registers to be written
674**
675** Returns: status:
676** MT_OK - No errors
677** MT_COMM_ERR - Serial bus communications error
678** user-defined
679**
680** Notes: This is a callback function that is called from the
681** the tuning algorithm. You MUST provide code for this
682** function to read data using the tuner's 2-wire serial
683** bus.
684**
685** The hUserData parameter is a user-specific argument.
686** If additional arguments are needed for the user's
687** serial bus read/write functions, this argument can be
688** used to supply the necessary information.
689** The hUserData parameter is initialized in the tuner's Open
690** function.
691**
692** Revision History:
693**
694** SCR Date Author Description
695** -------------------------------------------------------------------------
696** N/A 03-25-2004 DAD Original
697**
698*****************************************************************************/
699static u32 MT2063_ReadSub(struct mt2063_state *state,
700 u8 subAddress, u8 *pData, u32 cnt) 576 u8 subAddress, u8 *pData, u32 cnt)
701{ 577{
702 u32 status = 0; /* Status to be returned */ 578 u32 status = 0; /* Status to be returned */
703 struct dvb_frontend *fe = state->frontend; 579 struct dvb_frontend *fe = state->frontend;
704 u32 i = 0; 580 u32 i = 0;
705 581
706 /* 582 fe->ops.i2c_gate_ctrl(fe, 1);
707 ** ToDo: Add code here to implement a serial-bus read
708 ** operation to the MTxxxx tuner. If successful,
709 ** return MT_OK.
710 */
711 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge
712 583
713 for (i = 0; i < cnt; i++) { 584 for (i = 0; i < cnt; i++) {
714 if (mt2063_read_regs(state, subAddress + i, pData + i, 1) < 0) { 585 int ret;
715 status = -EINVAL; 586 u8 b0[] = { subAddress + i };
587 struct i2c_msg msg[] = {
588 {
589 .addr = state->config->tuner_address,
590 .flags = I2C_M_RD,
591 .buf = b0,
592 .len = 1
593 }, {
594 .addr = state->config->tuner_address,
595 .flags = I2C_M_RD,
596 .buf = pData + 1,
597 .len = 1
598 }
599 };
600
601 ret = i2c_transfer(state->i2c, msg, 2);
602 if (ret < 0)
716 break; 603 break;
717 }
718 } 604 }
719 605 fe->ops.i2c_gate_ctrl(fe, 0);
720 fe->ops.i2c_gate_ctrl(fe, 0); //I2C bypass drxk3926 close i2c bridge
721
722 return (status); 606 return (status);
723} 607}
724 608
@@ -1670,7 +1554,7 @@ static u32 MT2063_GetLocked(struct mt2063_state *state)
1670 1554
1671 do { 1555 do {
1672 status |= 1556 status |=
1673 MT2063_ReadSub(state, 1557 mt2063_read(state,
1674 MT2063_REG_LO_STATUS, 1558 MT2063_REG_LO_STATUS,
1675 &state->reg[MT2063_REG_LO_STATUS], 1); 1559 &state->reg[MT2063_REG_LO_STATUS], 1);
1676 1560
@@ -1830,7 +1714,7 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
1830 { 1714 {
1831 /* read the actual tuner register values for LO1C_1 and LO1C_2 */ 1715 /* read the actual tuner register values for LO1C_1 and LO1C_2 */
1832 status |= 1716 status |=
1833 MT2063_ReadSub(state, 1717 mt2063_read(state,
1834 MT2063_REG_LO1C_1, 1718 MT2063_REG_LO1C_1,
1835 &state-> 1719 &state->
1836 reg[MT2063_REG_LO1C_1], 2); 1720 reg[MT2063_REG_LO1C_1], 2);
@@ -1884,7 +1768,7 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
1884 { 1768 {
1885 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */ 1769 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */
1886 status |= 1770 status |=
1887 MT2063_ReadSub(state, 1771 mt2063_read(state,
1888 MT2063_REG_LO2C_1, 1772 MT2063_REG_LO2C_1,
1889 &state-> 1773 &state->
1890 reg[MT2063_REG_LO2C_1], 3); 1774 reg[MT2063_REG_LO2C_1], 3);
@@ -1983,7 +1867,7 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
1983 /* Initiate ADC output to reg 0x0A */ 1867 /* Initiate ADC output to reg 0x0A */
1984 if (reg != orig) 1868 if (reg != orig)
1985 status |= 1869 status |=
1986 MT2063_WriteSub(state, 1870 mt2063_write(state,
1987 MT2063_REG_BYP_CTRL, 1871 MT2063_REG_BYP_CTRL,
1988 &reg, 1); 1872 &reg, 1);
1989 1873
@@ -1992,7 +1876,7 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
1992 1876
1993 for (i = 0; i < 8; i++) { 1877 for (i = 0; i < 8; i++) {
1994 status |= 1878 status |=
1995 MT2063_ReadSub(state, 1879 mt2063_read(state,
1996 MT2063_REG_ADC_OUT, 1880 MT2063_REG_ADC_OUT,
1997 &state-> 1881 &state->
1998 reg 1882 reg
@@ -2015,7 +1899,7 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
2015 /* Restore value of Register BYP_CTRL */ 1899 /* Restore value of Register BYP_CTRL */
2016 if (reg != orig) 1900 if (reg != orig)
2017 status |= 1901 status |=
2018 MT2063_WriteSub(state, 1902 mt2063_write(state,
2019 MT2063_REG_BYP_CTRL, 1903 MT2063_REG_BYP_CTRL,
2020 &orig, 1); 1904 &orig, 1);
2021 } 1905 }
@@ -2185,7 +2069,7 @@ static u32 MT2063_GetReg(struct mt2063_state *state, u8 reg, u8 * val)
2185 if (reg >= MT2063_REG_END_REGS) 2069 if (reg >= MT2063_REG_END_REGS)
2186 return -ERANGE; 2070 return -ERANGE;
2187 2071
2188 status = MT2063_ReadSub(state, reg, &state->reg[reg], 1); 2072 status = mt2063_read(state, reg, &state->reg[reg], 1);
2189 2073
2190 return (status); 2074 return (status);
2191} 2075}
@@ -2490,7 +2374,7 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2490 }; 2374 };
2491 2375
2492 /* Read the Part/Rev code from the tuner */ 2376 /* Read the Part/Rev code from the tuner */
2493 status = MT2063_ReadSub(state, MT2063_REG_PART_REV, state->reg, 1); 2377 status = mt2063_read(state, MT2063_REG_PART_REV, state->reg, 1);
2494 if (status < 0) 2378 if (status < 0)
2495 return status; 2379 return status;
2496 2380
@@ -2501,7 +2385,7 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2501 return -ENODEV; /* Wrong tuner Part/Rev code */ 2385 return -ENODEV; /* Wrong tuner Part/Rev code */
2502 2386
2503 /* Check the 2nd byte of the Part/Rev code from the tuner */ 2387 /* Check the 2nd byte of the Part/Rev code from the tuner */
2504 status = MT2063_ReadSub(state, 2388 status = mt2063_read(state,
2505 MT2063_REG_RSVD_3B, 2389 MT2063_REG_RSVD_3B,
2506 &state->reg[MT2063_REG_RSVD_3B], 1); 2390 &state->reg[MT2063_REG_RSVD_3B], 1);
2507 2391
@@ -2510,7 +2394,7 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2510 return -ENODEV; /* Wrong tuner Part/Rev code */ 2394 return -ENODEV; /* Wrong tuner Part/Rev code */
2511 2395
2512 /* Reset the tuner */ 2396 /* Reset the tuner */
2513 status = MT2063_WriteSub(state, MT2063_REG_LO2CQ_3, &all_resets, 1); 2397 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
2514 if (status < 0) 2398 if (status < 0)
2515 return status; 2399 return status;
2516 2400
@@ -2537,7 +2421,7 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2537 while (status >= 0 && *def) { 2421 while (status >= 0 && *def) {
2538 u8 reg = *def++; 2422 u8 reg = *def++;
2539 u8 val = *def++; 2423 u8 val = *def++;
2540 status = MT2063_WriteSub(state, reg, &val, 1); 2424 status = mt2063_write(state, reg, &val, 1);
2541 } 2425 }
2542 if (status < 0) 2426 if (status < 0)
2543 return status; 2427 return status;
@@ -2547,7 +2431,7 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2547 maxReads = 10; 2431 maxReads = 10;
2548 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) { 2432 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
2549 msleep(2); 2433 msleep(2);
2550 status = MT2063_ReadSub(state, 2434 status = mt2063_read(state,
2551 MT2063_REG_XO_STATUS, 2435 MT2063_REG_XO_STATUS,
2552 &state-> 2436 &state->
2553 reg[MT2063_REG_XO_STATUS], 1); 2437 reg[MT2063_REG_XO_STATUS], 1);
@@ -2557,14 +2441,14 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2557 if (FCRUN != 0) 2441 if (FCRUN != 0)
2558 return -ENODEV; 2442 return -ENODEV;
2559 2443
2560 status = MT2063_ReadSub(state, 2444 status = mt2063_read(state,
2561 MT2063_REG_FIFFC, 2445 MT2063_REG_FIFFC,
2562 &state->reg[MT2063_REG_FIFFC], 1); 2446 &state->reg[MT2063_REG_FIFFC], 1);
2563 if (status < 0) 2447 if (status < 0)
2564 return status; 2448 return status;
2565 2449
2566 /* Read back all the registers from the tuner */ 2450 /* Read back all the registers from the tuner */
2567 status = MT2063_ReadSub(state, 2451 status = mt2063_read(state,
2568 MT2063_REG_PART_REV, 2452 MT2063_REG_PART_REV,
2569 state->reg, MT2063_REG_END_REGS); 2453 state->reg, MT2063_REG_END_REGS);
2570 if (status < 0) 2454 if (status < 0)
@@ -2633,13 +2517,13 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2633 */ 2517 */
2634 2518
2635 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; 2519 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
2636 status = MT2063_WriteSub(state, 2520 status = mt2063_write(state,
2637 MT2063_REG_CTUNE_CTRL, 2521 MT2063_REG_CTUNE_CTRL,
2638 &state->reg[MT2063_REG_CTUNE_CTRL], 1); 2522 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2639 if (status < 0) 2523 if (status < 0)
2640 return status; 2524 return status;
2641 /* Read the ClearTune filter calibration value */ 2525 /* Read the ClearTune filter calibration value */
2642 status = MT2063_ReadSub(state, 2526 status = mt2063_read(state,
2643 MT2063_REG_FIFFC, 2527 MT2063_REG_FIFFC,
2644 &state->reg[MT2063_REG_FIFFC], 1); 2528 &state->reg[MT2063_REG_FIFFC], 1);
2645 if (status < 0) 2529 if (status < 0)
@@ -2648,7 +2532,7 @@ static u32 MT2063_ReInit(struct mt2063_state *state)
2648 fcu_osc = state->reg[MT2063_REG_FIFFC]; 2532 fcu_osc = state->reg[MT2063_REG_FIFFC];
2649 2533
2650 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00; 2534 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
2651 status = MT2063_WriteSub(state, 2535 status = mt2063_write(state,
2652 MT2063_REG_CTUNE_CTRL, 2536 MT2063_REG_CTUNE_CTRL,
2653 &state->reg[MT2063_REG_CTUNE_CTRL], 1); 2537 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2654 if (status < 0) 2538 if (status < 0)
@@ -2781,11 +2665,11 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2781 2665
2782 /* Buffer the queue for restoration later and get actual LO2 values. */ 2666 /* Buffer the queue for restoration later and get actual LO2 values. */
2783 status |= 2667 status |=
2784 MT2063_ReadSub(state, 2668 mt2063_read(state,
2785 MT2063_REG_LO2CQ_1, 2669 MT2063_REG_LO2CQ_1,
2786 &(tempLO2CQ[0]), 3); 2670 &(tempLO2CQ[0]), 3);
2787 status |= 2671 status |=
2788 MT2063_ReadSub(state, 2672 mt2063_read(state,
2789 MT2063_REG_LO2C_1, 2673 MT2063_REG_LO2C_1,
2790 &(tempLO2C[0]), 3); 2674 &(tempLO2C[0]), 3);
2791 2675
@@ -2799,7 +2683,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2799 (tempLO2CQ[2] != tempLO2C[2])) { 2683 (tempLO2CQ[2] != tempLO2C[2])) {
2800 /* put actual LO2 value into queue (with 0 in one-shot bits) */ 2684 /* put actual LO2 value into queue (with 0 in one-shot bits) */
2801 status |= 2685 status |=
2802 MT2063_WriteSub(state, 2686 mt2063_write(state,
2803 MT2063_REG_LO2CQ_1, 2687 MT2063_REG_LO2CQ_1,
2804 &(tempLO2C[0]), 3); 2688 &(tempLO2C[0]), 3);
2805 2689
@@ -2826,7 +2710,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2826 state->reg[MT2063_REG_LO1CQ_2] = 2710 state->reg[MT2063_REG_LO1CQ_2] =
2827 (u8) (FracN); 2711 (u8) (FracN);
2828 status |= 2712 status |=
2829 MT2063_WriteSub(state, 2713 mt2063_write(state,
2830 MT2063_REG_LO1CQ_1, 2714 MT2063_REG_LO1CQ_1,
2831 &state-> 2715 &state->
2832 reg[MT2063_REG_LO1CQ_1], 2); 2716 reg[MT2063_REG_LO1CQ_1], 2);
@@ -2834,7 +2718,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2834 /* set the one-shot bit to load the pair of LO values */ 2718 /* set the one-shot bit to load the pair of LO values */
2835 tmpOneShot = tempLO2CQ[2] | 0xE0; 2719 tmpOneShot = tempLO2CQ[2] | 0xE0;
2836 status |= 2720 status |=
2837 MT2063_WriteSub(state, 2721 mt2063_write(state,
2838 MT2063_REG_LO2CQ_3, 2722 MT2063_REG_LO2CQ_3,
2839 &tmpOneShot, 1); 2723 &tmpOneShot, 1);
2840 2724
@@ -2842,7 +2726,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2842 if (restore) { 2726 if (restore) {
2843 /* put actual LO2 value into queue (0 in one-shot bits) */ 2727 /* put actual LO2 value into queue (0 in one-shot bits) */
2844 status |= 2728 status |=
2845 MT2063_WriteSub(state, 2729 mt2063_write(state,
2846 MT2063_REG_LO2CQ_1, 2730 MT2063_REG_LO2CQ_1,
2847 &(tempLO2CQ[0]), 3); 2731 &(tempLO2CQ[0]), 3);
2848 2732
@@ -2895,11 +2779,11 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2895 2779
2896 /* Buffer the queue for restoration later and get actual LO2 values. */ 2780 /* Buffer the queue for restoration later and get actual LO2 values. */
2897 status |= 2781 status |=
2898 MT2063_ReadSub(state, 2782 mt2063_read(state,
2899 MT2063_REG_LO1CQ_1, 2783 MT2063_REG_LO1CQ_1,
2900 &(tempLO1CQ[0]), 2); 2784 &(tempLO1CQ[0]), 2);
2901 status |= 2785 status |=
2902 MT2063_ReadSub(state, 2786 mt2063_read(state,
2903 MT2063_REG_LO1C_1, 2787 MT2063_REG_LO1C_1,
2904 &(tempLO1C[0]), 2); 2788 &(tempLO1C[0]), 2);
2905 2789
@@ -2908,7 +2792,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2908 || (tempLO1CQ[1] != tempLO1C[1])) { 2792 || (tempLO1CQ[1] != tempLO1C[1])) {
2909 /* put actual LO1 value into queue */ 2793 /* put actual LO1 value into queue */
2910 status |= 2794 status |=
2911 MT2063_WriteSub(state, 2795 mt2063_write(state,
2912 MT2063_REG_LO1CQ_1, 2796 MT2063_REG_LO1CQ_1,
2913 &(tempLO1C[0]), 2); 2797 &(tempLO1C[0]), 2);
2914 2798
@@ -2934,7 +2818,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2934 state->reg[MT2063_REG_LO2CQ_3] = 2818 state->reg[MT2063_REG_LO2CQ_3] =
2935 (u8) ((FracN2 & 0x0F)); 2819 (u8) ((FracN2 & 0x0F));
2936 status |= 2820 status |=
2937 MT2063_WriteSub(state, 2821 mt2063_write(state,
2938 MT2063_REG_LO1CQ_1, 2822 MT2063_REG_LO1CQ_1,
2939 &state-> 2823 &state->
2940 reg[MT2063_REG_LO1CQ_1], 3); 2824 reg[MT2063_REG_LO1CQ_1], 3);
@@ -2943,7 +2827,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2943 tmpOneShot = 2827 tmpOneShot =
2944 state->reg[MT2063_REG_LO2CQ_3] | 0xE0; 2828 state->reg[MT2063_REG_LO2CQ_3] | 0xE0;
2945 status |= 2829 status |=
2946 MT2063_WriteSub(state, 2830 mt2063_write(state,
2947 MT2063_REG_LO2CQ_3, 2831 MT2063_REG_LO2CQ_3,
2948 &tmpOneShot, 1); 2832 &tmpOneShot, 1);
2949 2833
@@ -2951,7 +2835,7 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
2951 if (restore) { 2835 if (restore) {
2952 /* put previous LO1 queue value back into queue */ 2836 /* put previous LO1 queue value back into queue */
2953 status |= 2837 status |=
2954 MT2063_WriteSub(state, 2838 mt2063_write(state,
2955 MT2063_REG_LO1CQ_1, 2839 MT2063_REG_LO1CQ_1,
2956 &(tempLO1CQ[0]), 2); 2840 &(tempLO1CQ[0]), 2);
2957 2841
@@ -3355,14 +3239,14 @@ static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state, enum MT2063_Mas
3355 if ((Bits & 0xFF00) != 0) { 3239 if ((Bits & 0xFF00) != 0) {
3356 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); 3240 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
3357 status |= 3241 status |=
3358 MT2063_WriteSub(state, 3242 mt2063_write(state,
3359 MT2063_REG_PWR_2, 3243 MT2063_REG_PWR_2,
3360 &state->reg[MT2063_REG_PWR_2], 1); 3244 &state->reg[MT2063_REG_PWR_2], 1);
3361 } 3245 }
3362 if ((Bits & 0xFF) != 0) { 3246 if ((Bits & 0xFF) != 0) {
3363 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); 3247 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
3364 status |= 3248 status |=
3365 MT2063_WriteSub(state, 3249 mt2063_write(state,
3366 MT2063_REG_PWR_1, 3250 MT2063_REG_PWR_1,
3367 &state->reg[MT2063_REG_PWR_1], 1); 3251 &state->reg[MT2063_REG_PWR_1], 1);
3368 } 3252 }
@@ -3408,7 +3292,7 @@ static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
3408 state->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */ 3292 state->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */
3409 3293
3410 status |= 3294 status |=
3411 MT2063_WriteSub(state, 3295 mt2063_write(state,
3412 MT2063_REG_PWR_1, 3296 MT2063_REG_PWR_1,
3413 &state->reg[MT2063_REG_PWR_1], 1); 3297 &state->reg[MT2063_REG_PWR_1], 1);
3414 3298
@@ -3416,14 +3300,14 @@ static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
3416 state->reg[MT2063_REG_BYP_CTRL] = 3300 state->reg[MT2063_REG_BYP_CTRL] =
3417 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; 3301 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
3418 status |= 3302 status |=
3419 MT2063_WriteSub(state, 3303 mt2063_write(state,
3420 MT2063_REG_BYP_CTRL, 3304 MT2063_REG_BYP_CTRL,
3421 &state->reg[MT2063_REG_BYP_CTRL], 3305 &state->reg[MT2063_REG_BYP_CTRL],
3422 1); 3306 1);
3423 state->reg[MT2063_REG_BYP_CTRL] = 3307 state->reg[MT2063_REG_BYP_CTRL] =
3424 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F); 3308 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F);
3425 status |= 3309 status |=
3426 MT2063_WriteSub(state, 3310 mt2063_write(state,
3427 MT2063_REG_BYP_CTRL, 3311 MT2063_REG_BYP_CTRL,
3428 &state->reg[MT2063_REG_BYP_CTRL], 3312 &state->reg[MT2063_REG_BYP_CTRL],
3429 1); 3313 1);
@@ -3467,7 +3351,7 @@ static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val)
3467 if (reg >= MT2063_REG_END_REGS) 3351 if (reg >= MT2063_REG_END_REGS)
3468 status |= -ERANGE; 3352 status |= -ERANGE;
3469 3353
3470 status = MT2063_WriteSub(state, reg, &val, 3354 status = mt2063_write(state, reg, &val,
3471 1); 3355 1);
3472 if (status >= 0) 3356 if (status >= 0)
3473 state->reg[reg] = val; 3357 state->reg[reg] = val;
@@ -3749,7 +3633,7 @@ static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
3749 */ 3633 */
3750 if (status >= 0) { 3634 if (status >= 0) {
3751 status |= 3635 status |=
3752 MT2063_ReadSub(state, 3636 mt2063_read(state,
3753 MT2063_REG_FIFFC, 3637 MT2063_REG_FIFFC,
3754 &state->reg[MT2063_REG_FIFFC], 1); 3638 &state->reg[MT2063_REG_FIFFC], 1);
3755 fiffc = state->reg[MT2063_REG_FIFFC]; 3639 fiffc = state->reg[MT2063_REG_FIFFC];
@@ -3852,10 +3736,10 @@ static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
3852 ** IMPORTANT: There is a required order for writing 3736 ** IMPORTANT: There is a required order for writing
3853 ** (0x05 must follow all the others). 3737 ** (0x05 must follow all the others).
3854 */ 3738 */
3855 status |= MT2063_WriteSub(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */ 3739 status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
3856 if (state->tuner_id == MT2063_B0) { 3740 if (state->tuner_id == MT2063_B0) {
3857 /* Re-write the one-shot bits to trigger the tune operation */ 3741 /* Re-write the one-shot bits to trigger the tune operation */
3858 status |= MT2063_WriteSub(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ 3742 status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
3859 } 3743 }
3860 /* Write out the FIFF offset only if it's changing */ 3744 /* Write out the FIFF offset only if it's changing */
3861 if (state->reg[MT2063_REG_FIFF_OFFSET] != 3745 if (state->reg[MT2063_REG_FIFF_OFFSET] !=
@@ -3863,7 +3747,7 @@ static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
3863 state->reg[MT2063_REG_FIFF_OFFSET] = 3747 state->reg[MT2063_REG_FIFF_OFFSET] =
3864 (u8) fiffof; 3748 (u8) fiffof;
3865 status |= 3749 status |=
3866 MT2063_WriteSub(state, 3750 mt2063_write(state,
3867 MT2063_REG_FIFF_OFFSET, 3751 MT2063_REG_FIFF_OFFSET,
3868 &state-> 3752 &state->
3869 reg[MT2063_REG_FIFF_OFFSET], 3753 reg[MT2063_REG_FIFF_OFFSET],
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 01:22:40 -0500