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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-21 01:24:18 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:19:11 -0500
commit51f0f7b3edac87a1b020dc6a58aaf3624a4da40b (patch)
treea6faa572360b55eea97f0fdabe95333e0760a345 /drivers/media/common
parent29a0a4fec580e55959b4fbc1f6b2ac0c1ef4239d (diff)
[media] mt2063: Merge the two state structures into one
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/common')
-rw-r--r--drivers/media/common/tuners/mt2063.c1021
1 files changed, 454 insertions, 567 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index 30c72c0423b1..66633fa99e82 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -372,20 +372,6 @@ enum MT2063_Register_Offsets {
372 MT2063_REG_END_REGS 372 MT2063_REG_END_REGS
373}; 373};
374 374
375struct MT2063_Info_t {
376 void *handle;
377 void *hUserData;
378 u32 address;
379 u32 tuner_id;
380 struct MT2063_AvoidSpursData_t AS_Data;
381 u32 f_IF1_actual;
382 u32 rcvr_mode;
383 u32 ctfilt_sw;
384 u32 CTFiltMax[31];
385 u32 num_regs;
386 u8 reg[MT2063_REG_END_REGS];
387};
388
389enum MTTune_atv_standard { 375enum MTTune_atv_standard {
390 MTTUNEA_UNKNOWN = 0, 376 MTTUNEA_UNKNOWN = 0,
391 MTTUNEA_PAL_B, 377 MTTUNEA_PAL_B,
@@ -408,7 +394,6 @@ struct mt2063_state {
408 struct dvb_tuner_ops ops; 394 struct dvb_tuner_ops ops;
409 struct dvb_frontend *frontend; 395 struct dvb_frontend *frontend;
410 struct tuner_state status; 396 struct tuner_state status;
411 struct MT2063_Info_t *MT2063_ht;
412 bool MT2063_init; 397 bool MT2063_init;
413 398
414 enum MTTune_atv_standard tv_type; 399 enum MTTune_atv_standard tv_type;
@@ -416,37 +401,44 @@ struct mt2063_state {
416 u32 srate; 401 u32 srate;
417 u32 bandwidth; 402 u32 bandwidth;
418 u32 reference; 403 u32 reference;
404
405 u32 tuner_id;
406 struct MT2063_AvoidSpursData_t AS_Data;
407 u32 f_IF1_actual;
408 u32 rcvr_mode;
409 u32 ctfilt_sw;
410 u32 CTFiltMax[31];
411 u32 num_regs;
412 u8 reg[MT2063_REG_END_REGS];
419}; 413};
420 414
421/* Prototypes */ 415/* Prototypes */
422static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info, 416static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
423 u32 f_min, u32 f_max); 417 u32 f_min, u32 f_max);
424static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo); 418static u32 MT2063_ReInit(struct mt2063_state *pInfo);
425static u32 MT2063_Close(struct MT2063_Info_t *pInfo); 419static u32 MT2063_Close(struct mt2063_state *pInfo);
426static u32 MT2063_GetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 * val); 420static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val);
427static u32 MT2063_GetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, u32 * pValue); 421static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param, u32 * pValue);
428static u32 MT2063_SetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 val); 422static u32 MT2063_SetReg(struct mt2063_state *pInfo, u8 reg, u8 val);
429static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, 423static u32 MT2063_SetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
430 enum MT2063_DNC_Output_Enable nValue); 424 enum MT2063_DNC_Output_Enable nValue);
431 425
432/*****************/ 426/*****************/
433/* From drivers/media/common/tuners/mt2063_cfg.h */ 427/* From drivers/media/common/tuners/mt2063_cfg.h */
434 428
435unsigned int mt2063_setTune(struct dvb_frontend *fe, u32 f_in, 429unsigned int mt2063_setTune(struct dvb_frontend *fe, u32 f_in,
436 u32 bw_in, 430 u32 bw_in,
437 enum MTTune_atv_standard tv_type) 431 enum MTTune_atv_standard tv_type)
438{ 432{
439 //return (int)MT_Tune_atv(h, f_in, bw_in, tv_type);
440
441 struct dvb_frontend_ops *frontend_ops = NULL; 433 struct dvb_frontend_ops *frontend_ops = NULL;
442 struct dvb_tuner_ops *tuner_ops = NULL; 434 struct dvb_tuner_ops *tuner_ops = NULL;
443 struct tuner_state t_state; 435 struct tuner_state t_state;
444 struct mt2063_state *mt2063State = fe->tuner_priv; 436 struct mt2063_state *state = fe->tuner_priv;
445 int err = 0; 437 int err = 0;
446 438
447 t_state.frequency = f_in; 439 t_state.frequency = f_in;
448 t_state.bandwidth = bw_in; 440 t_state.bandwidth = bw_in;
449 mt2063State->tv_type = tv_type; 441 state->tv_type = tv_type;
450 if (&fe->ops) 442 if (&fe->ops)
451 frontend_ops = &fe->ops; 443 frontend_ops = &fe->ops;
452 if (&frontend_ops->tuner_ops) 444 if (&frontend_ops->tuner_ops)
@@ -558,7 +550,7 @@ unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
558 550
559//i2c operation 551//i2c operation
560static int mt2063_writeregs(struct mt2063_state *state, u8 reg1, 552static int mt2063_writeregs(struct mt2063_state *state, u8 reg1,
561 u8 * data, int len) 553 u8 *data, int len)
562{ 554{
563 int ret; 555 int ret;
564 u8 buf[60]; /* = { reg1, data }; */ 556 u8 buf[60]; /* = { reg1, data }; */
@@ -648,19 +640,17 @@ static int mt2063_read_regs(struct mt2063_state *state, u8 reg1, u8 * b, u8 len)
648** N/A 03-25-2004 DAD Original 640** N/A 03-25-2004 DAD Original
649** 641**
650*****************************************************************************/ 642*****************************************************************************/
651static u32 MT2063_WriteSub(void *hUserData, 643static u32 MT2063_WriteSub(struct mt2063_state *state,
652 u32 addr, 644 u8 subAddress, u8 *pData, u32 cnt)
653 u8 subAddress, u8 * pData, u32 cnt)
654{ 645{
655 u32 status = 0; /* Status to be returned */ 646 u32 status = 0; /* Status to be returned */
656 struct dvb_frontend *fe = hUserData; 647 struct dvb_frontend *fe = state->frontend;
657 struct mt2063_state *state = fe->tuner_priv; 648
658 /* 649 /*
659 ** ToDo: Add code here to implement a serial-bus write 650 ** ToDo: Add code here to implement a serial-bus write
660 ** operation to the MTxxxx tuner. If successful, 651 ** operation to the MTxxxx tuner. If successful,
661 ** return MT_OK. 652 ** return MT_OK.
662 */ 653 */
663/* return status; */
664 654
665 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge 655 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge
666 656
@@ -711,20 +701,18 @@ static u32 MT2063_WriteSub(void *hUserData,
711** N/A 03-25-2004 DAD Original 701** N/A 03-25-2004 DAD Original
712** 702**
713*****************************************************************************/ 703*****************************************************************************/
714static u32 MT2063_ReadSub(void *hUserData, 704static u32 MT2063_ReadSub(struct mt2063_state *state,
715 u32 addr, 705 u8 subAddress, u8 *pData, u32 cnt)
716 u8 subAddress, u8 * pData, u32 cnt)
717{ 706{
707 u32 status = 0; /* Status to be returned */
708 struct dvb_frontend *fe = state->frontend;
709 u32 i = 0;
710
718 /* 711 /*
719 ** ToDo: Add code here to implement a serial-bus read 712 ** ToDo: Add code here to implement a serial-bus read
720 ** operation to the MTxxxx tuner. If successful, 713 ** operation to the MTxxxx tuner. If successful,
721 ** return MT_OK. 714 ** return MT_OK.
722 */ 715 */
723/* return status; */
724 u32 status = 0; /* Status to be returned */
725 struct dvb_frontend *fe = hUserData;
726 struct mt2063_state *state = fe->tuner_priv;
727 u32 i = 0;
728 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge 716 fe->ops.i2c_gate_ctrl(fe, 1); //I2C bypass drxk3926 close i2c bridge
729 717
730 for (i = 0; i < cnt; i++) { 718 for (i = 0; i < cnt; i++) {
@@ -1911,63 +1899,32 @@ static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num,
1911** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 1899** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
1912** 1900**
1913******************************************************************************/ 1901******************************************************************************/
1914static u32 MT2063_Open(u32 MT2063_Addr, struct MT2063_Info_t **hMT2063, void *hUserData) 1902static u32 MT2063_Open(struct dvb_frontend *fe)
1915{ 1903{
1916 u32 status = 0; /* Status to be returned. */ 1904 u32 status; /* Status to be returned. */
1917 struct MT2063_Info_t *pInfo = NULL;
1918 struct dvb_frontend *fe = (struct dvb_frontend *)hUserData;
1919 struct mt2063_state *state = fe->tuner_priv; 1905 struct mt2063_state *state = fe->tuner_priv;
1920 1906
1921 /* Check the argument before using */
1922 if (hMT2063 == NULL) {
1923 return -ENODEV;
1924 }
1925
1926 /* Default tuner handle to NULL. If successful, it will be reassigned */ 1907 /* Default tuner handle to NULL. If successful, it will be reassigned */
1927 1908
1928 if (state->MT2063_init == false) { 1909 if (state->MT2063_init == false)
1929 pInfo = kzalloc(sizeof(struct MT2063_Info_t), GFP_KERNEL); 1910 state->rcvr_mode = MT2063_CABLE_QAM;
1930 if (pInfo == NULL) {
1931 return -ENOMEM;
1932 }
1933 pInfo->handle = NULL;
1934 pInfo->address = MAX_UDATA;
1935 pInfo->rcvr_mode = MT2063_CABLE_QAM;
1936 pInfo->hUserData = NULL;
1937 } else {
1938 pInfo = *hMT2063;
1939 }
1940 1911
1912 status = MT2063_RegisterTuner(&state->AS_Data);
1941 if (status >= 0) { 1913 if (status >= 0) {
1942 status |= MT2063_RegisterTuner(&pInfo->AS_Data); 1914 state->rcvr_mode = MT2063_CABLE_QAM;
1943 } 1915 status = MT2063_ReInit(state);
1944
1945 if (status >= 0) {
1946 pInfo->handle = (void *) pInfo;
1947
1948 pInfo->hUserData = hUserData;
1949 pInfo->address = MT2063_Addr;
1950 pInfo->rcvr_mode = MT2063_CABLE_QAM;
1951 status |= MT2063_ReInit((void *) pInfo);
1952 } 1916 }
1953 1917
1954 if (status < 0) 1918 if (status < 0)
1955 /* MT2063_Close handles the un-registration of the tuner */ 1919 /* MT2063_Close handles the un-registration of the tuner */
1956 MT2063_Close((void *) pInfo); 1920 MT2063_Close(state);
1957 else { 1921 else {
1958 state->MT2063_init = true; 1922 state->MT2063_init = true;
1959 *hMT2063 = pInfo->handle;
1960
1961 } 1923 }
1962 1924
1963 return (status); 1925 return (status);
1964} 1926}
1965 1927
1966static u32 MT2063_IsValidHandle(struct MT2063_Info_t *handle)
1967{
1968 return ((handle != NULL) && (handle->handle == handle)) ? 1 : 0;
1969}
1970
1971/****************************************************************************** 1928/******************************************************************************
1972** 1929**
1973** Name: MT2063_Close 1930** Name: MT2063_Close
@@ -1989,19 +1946,11 @@ static u32 MT2063_IsValidHandle(struct MT2063_Info_t *handle)
1989** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 1946** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
1990** 1947**
1991******************************************************************************/ 1948******************************************************************************/
1992static u32 MT2063_Close(struct MT2063_Info_t *pInfo) 1949static u32 MT2063_Close(struct mt2063_state *state)
1993{ 1950{
1994 if (!MT2063_IsValidHandle(pInfo))
1995 return -ENODEV;
1996
1997 /* Unregister tuner with SpurAvoidance routines (if needed) */ 1951 /* Unregister tuner with SpurAvoidance routines (if needed) */
1998 MT2063_UnRegisterTuner(&pInfo->AS_Data); 1952 MT2063_UnRegisterTuner(&state->AS_Data);
1999 /* Now remove the tuner from our own list of tuners */ 1953 /* Now remove the tuner from our own list of tuners */
2000 pInfo->handle = NULL;
2001 pInfo->address = MAX_UDATA;
2002 pInfo->hUserData = NULL;
2003 //kfree(pInfo);
2004 //pInfo = NULL;
2005 1954
2006 return 0; 1955 return 0;
2007} 1956}
@@ -2031,7 +1980,7 @@ static u32 MT2063_Close(struct MT2063_Info_t *pInfo)
2031** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 1980** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2032** 1981**
2033****************************************************************************/ 1982****************************************************************************/
2034static u32 MT2063_GetLocked(struct MT2063_Info_t *pInfo) 1983static u32 MT2063_GetLocked(struct mt2063_state *pInfo)
2035{ 1984{
2036 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */ 1985 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */
2037 const u32 nPollRate = 2; /* poll status bits every 2 ms */ 1986 const u32 nPollRate = 2; /* poll status bits every 2 ms */
@@ -2041,16 +1990,13 @@ static u32 MT2063_GetLocked(struct MT2063_Info_t *pInfo)
2041 u32 status = 0; /* Status to be returned */ 1990 u32 status = 0; /* Status to be returned */
2042 u32 nDelays = 0; 1991 u32 nDelays = 0;
2043 1992
2044 if (MT2063_IsValidHandle(pInfo) == 0)
2045 return -ENODEV;
2046
2047 /* LO2 Lock bit was in a different place for B0 version */ 1993 /* LO2 Lock bit was in a different place for B0 version */
2048 if (pInfo->tuner_id == MT2063_B0) 1994 if (pInfo->tuner_id == MT2063_B0)
2049 LO2LK = 0x40; 1995 LO2LK = 0x40;
2050 1996
2051 do { 1997 do {
2052 status |= 1998 status |=
2053 MT2063_ReadSub(pInfo->hUserData, pInfo->address, 1999 MT2063_ReadSub(pInfo,
2054 MT2063_REG_LO_STATUS, 2000 MT2063_REG_LO_STATUS,
2055 &pInfo->reg[MT2063_REG_LO_STATUS], 1); 2001 &pInfo->reg[MT2063_REG_LO_STATUS], 1);
2056 2002
@@ -2165,7 +2111,7 @@ static u32 MT2063_GetLocked(struct MT2063_Info_t *pInfo)
2165** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 2111** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2166** 2112**
2167****************************************************************************/ 2113****************************************************************************/
2168static u32 MT2063_GetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param, u32 *pValue) 2114static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param, u32 *pValue)
2169{ 2115{
2170 u32 status = 0; /* Status to be returned */ 2116 u32 status = 0; /* Status to be returned */
2171 u32 Div; 2117 u32 Div;
@@ -2174,366 +2120,355 @@ static u32 MT2063_GetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param,
2174 if (pValue == NULL) 2120 if (pValue == NULL)
2175 return -EINVAL; 2121 return -EINVAL;
2176 2122
2177 /* Verify that the handle passed points to a valid tuner */ 2123 switch (param) {
2178 if (MT2063_IsValidHandle(pInfo) == 0) 2124 /* Serial Bus address of this tuner */
2179 return -ENODEV; 2125 case MT2063_IC_ADDR:
2126 *pValue = pInfo->config->tuner_address;
2127 break;
2128
2129 /* Max # of MT2063's allowed to be open */
2130 case MT2063_MAX_OPEN:
2131 *pValue = nMT2063MaxTuners;
2132 break;
2133
2134 /* # of MT2063's open */
2135 case MT2063_NUM_OPEN:
2136 *pValue = nMT2063OpenTuners;
2137 break;
2138
2139 /* crystal frequency */
2140 case MT2063_SRO_FREQ:
2141 *pValue = pInfo->AS_Data.f_ref;
2142 break;
2143
2144 /* minimum tuning step size */
2145 case MT2063_STEPSIZE:
2146 *pValue = pInfo->AS_Data.f_LO2_Step;
2147 break;
2148
2149 /* input center frequency */
2150 case MT2063_INPUT_FREQ:
2151 *pValue = pInfo->AS_Data.f_in;
2152 break;
2153
2154 /* LO1 Frequency */
2155 case MT2063_LO1_FREQ:
2156 {
2157 /* read the actual tuner register values for LO1C_1 and LO1C_2 */
2158 status |=
2159 MT2063_ReadSub(pInfo,
2160 MT2063_REG_LO1C_1,
2161 &pInfo->
2162 reg[MT2063_REG_LO1C_1], 2);
2163 Div = pInfo->reg[MT2063_REG_LO1C_1];
2164 Num = pInfo->reg[MT2063_REG_LO1C_2] & 0x3F;
2165 pInfo->AS_Data.f_LO1 =
2166 (pInfo->AS_Data.f_ref * Div) +
2167 MT2063_fLO_FractionalTerm(pInfo->AS_Data.
2168 f_ref, Num, 64);
2169 }
2170 *pValue = pInfo->AS_Data.f_LO1;
2171 break;
2172
2173 /* LO1 minimum step size */
2174 case MT2063_LO1_STEPSIZE:
2175 *pValue = pInfo->AS_Data.f_LO1_Step;
2176 break;
2177
2178 /* LO1 FracN keep-out region */
2179 case MT2063_LO1_FRACN_AVOID_PARAM:
2180 *pValue = pInfo->AS_Data.f_LO1_FracN_Avoid;
2181 break;
2182
2183 /* Current 1st IF in use */
2184 case MT2063_IF1_ACTUAL:
2185 *pValue = pInfo->f_IF1_actual;
2186 break;
2187
2188 /* Requested 1st IF */
2189 case MT2063_IF1_REQUEST:
2190 *pValue = pInfo->AS_Data.f_if1_Request;
2191 break;
2192
2193 /* Center of 1st IF SAW filter */
2194 case MT2063_IF1_CENTER:
2195 *pValue = pInfo->AS_Data.f_if1_Center;
2196 break;
2197
2198 /* Bandwidth of 1st IF SAW filter */
2199 case MT2063_IF1_BW:
2200 *pValue = pInfo->AS_Data.f_if1_bw;
2201 break;
2202
2203 /* zero-IF bandwidth */
2204 case MT2063_ZIF_BW:
2205 *pValue = pInfo->AS_Data.f_zif_bw;
2206 break;
2207
2208 /* LO2 Frequency */
2209 case MT2063_LO2_FREQ:
2210 {
2211 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */
2212 status |=
2213 MT2063_ReadSub(pInfo,
2214 MT2063_REG_LO2C_1,
2215 &pInfo->
2216 reg[MT2063_REG_LO2C_1], 3);
2217 Div =
2218 (pInfo->reg[MT2063_REG_LO2C_1] & 0xFE) >> 1;
2219 Num =
2220 ((pInfo->
2221 reg[MT2063_REG_LO2C_1] & 0x01) << 12) |
2222 (pInfo->
2223 reg[MT2063_REG_LO2C_2] << 4) | (pInfo->
2224 reg
2225 [MT2063_REG_LO2C_3]
2226 & 0x00F);
2227 pInfo->AS_Data.f_LO2 =
2228 (pInfo->AS_Data.f_ref * Div) +
2229 MT2063_fLO_FractionalTerm(pInfo->AS_Data.
2230 f_ref, Num, 8191);
2231 }
2232 *pValue = pInfo->AS_Data.f_LO2;
2233 break;
2234
2235 /* LO2 minimum step size */
2236 case MT2063_LO2_STEPSIZE:
2237 *pValue = pInfo->AS_Data.f_LO2_Step;
2238 break;
2239
2240 /* LO2 FracN keep-out region */
2241 case MT2063_LO2_FRACN_AVOID:
2242 *pValue = pInfo->AS_Data.f_LO2_FracN_Avoid;
2243 break;
2244
2245 /* output center frequency */
2246 case MT2063_OUTPUT_FREQ:
2247 *pValue = pInfo->AS_Data.f_out;
2248 break;
2249
2250 /* output bandwidth */
2251 case MT2063_OUTPUT_BW:
2252 *pValue = pInfo->AS_Data.f_out_bw - 750000;
2253 break;
2254
2255 /* min inter-tuner LO separation */
2256 case MT2063_LO_SEPARATION:
2257 *pValue = pInfo->AS_Data.f_min_LO_Separation;
2258 break;
2259
2260 /* ID of avoid-spurs algorithm in use */
2261 case MT2063_AS_ALG:
2262 *pValue = pInfo->AS_Data.nAS_Algorithm;
2263 break;
2264
2265 /* max # of intra-tuner harmonics */
2266 case MT2063_MAX_HARM1:
2267 *pValue = pInfo->AS_Data.maxH1;
2268 break;
2269
2270 /* max # of inter-tuner harmonics */
2271 case MT2063_MAX_HARM2:
2272 *pValue = pInfo->AS_Data.maxH2;
2273 break;
2274
2275 /* # of 1st IF exclusion zones */
2276 case MT2063_EXCL_ZONES:
2277 *pValue = pInfo->AS_Data.nZones;
2278 break;
2279
2280 /* # of spurs found/avoided */
2281 case MT2063_NUM_SPURS:
2282 *pValue = pInfo->AS_Data.nSpursFound;
2283 break;
2284
2285 /* >0 spurs avoided */
2286 case MT2063_SPUR_AVOIDED:
2287 *pValue = pInfo->AS_Data.bSpurAvoided;
2288 break;
2289
2290 /* >0 spurs in output (mathematically) */
2291 case MT2063_SPUR_PRESENT:
2292 *pValue = pInfo->AS_Data.bSpurPresent;
2293 break;
2294
2295 /* Predefined receiver setup combination */
2296 case MT2063_RCVR_MODE:
2297 *pValue = pInfo->rcvr_mode;
2298 break;
2299
2300 case MT2063_PD1:
2301 case MT2063_PD2: {
2302 u8 mask = (param == MT2063_PD1 ? 0x01 : 0x03); /* PD1 vs PD2 */
2303 u8 orig = (pInfo->reg[MT2063_REG_BYP_CTRL]);
2304 u8 reg = (orig & 0xF1) | mask; /* Only set 3 bits (not 5) */
2305 int i;
2306
2307 *pValue = 0;
2308
2309 /* Initiate ADC output to reg 0x0A */
2310 if (reg != orig)
2311 status |=
2312 MT2063_WriteSub(pInfo,
2313 MT2063_REG_BYP_CTRL,
2314 &reg, 1);
2315
2316 if (status < 0)
2317 return (status);
2318
2319 for (i = 0; i < 8; i++) {
2320 status |=
2321 MT2063_ReadSub(pInfo,
2322 MT2063_REG_ADC_OUT,
2323 &pInfo->
2324 reg
2325 [MT2063_REG_ADC_OUT],
2326 1);
2327
2328 if (status >= 0)
2329 *pValue +=
2330 pInfo->
2331 reg[MT2063_REG_ADC_OUT];
2332 else {
2333 if (i)
2334 *pValue /= i;
2335 return (status);
2336 }
2337 }
2338 *pValue /= 8; /* divide by number of reads */
2339 *pValue >>= 2; /* only want 6 MSB's out of 8 */
2340
2341 /* Restore value of Register BYP_CTRL */
2342 if (reg != orig)
2343 status |=
2344 MT2063_WriteSub(pInfo,
2345 MT2063_REG_BYP_CTRL,
2346 &orig, 1);
2347 }
2348 break;
2349
2350 /* Get LNA attenuator code */
2351 case MT2063_ACLNA:
2352 {
2353 u8 val;
2354 status |=
2355 MT2063_GetReg(pInfo, MT2063_REG_XO_STATUS,
2356 &val);
2357 *pValue = val & 0x1f;
2358 }
2359 break;
2360
2361 /* Get RF attenuator code */
2362 case MT2063_ACRF:
2363 {
2364 u8 val;
2365 status |=
2366 MT2063_GetReg(pInfo, MT2063_REG_RF_STATUS,
2367 &val);
2368 *pValue = val & 0x1f;
2369 }
2370 break;
2180 2371
2181 switch (param) { 2372 /* Get FIF attenuator code */
2182 /* Serial Bus address of this tuner */ 2373 case MT2063_ACFIF:
2183 case MT2063_IC_ADDR: 2374 {
2184 *pValue = pInfo->address; 2375 u8 val;
2185 break; 2376 status |=
2186 2377 MT2063_GetReg(pInfo, MT2063_REG_FIF_STATUS,
2187 /* Max # of MT2063's allowed to be open */ 2378 &val);
2188 case MT2063_MAX_OPEN: 2379 *pValue = val & 0x1f;
2189 *pValue = nMT2063MaxTuners; 2380 }
2190 break; 2381 break;
2191 2382
2192 /* # of MT2063's open */ 2383 /* Get LNA attenuator limit */
2193 case MT2063_NUM_OPEN: 2384 case MT2063_ACLNA_MAX:
2194 *pValue = nMT2063OpenTuners; 2385 {
2195 break; 2386 u8 val;
2196 2387 status |=
2197 /* crystal frequency */ 2388 MT2063_GetReg(pInfo, MT2063_REG_LNA_OV,
2198 case MT2063_SRO_FREQ: 2389 &val);
2199 *pValue = pInfo->AS_Data.f_ref; 2390 *pValue = val & 0x1f;
2200 break; 2391 }
2201 2392 break;
2202 /* minimum tuning step size */ 2393
2203 case MT2063_STEPSIZE: 2394 /* Get RF attenuator limit */
2204 *pValue = pInfo->AS_Data.f_LO2_Step; 2395 case MT2063_ACRF_MAX:
2205 break; 2396 {
2206 2397 u8 val;
2207 /* input center frequency */ 2398 status |=
2208 case MT2063_INPUT_FREQ: 2399 MT2063_GetReg(pInfo, MT2063_REG_RF_OV,
2209 *pValue = pInfo->AS_Data.f_in; 2400 &val);
2210 break; 2401 *pValue = val & 0x1f;
2211 2402 }
2212 /* LO1 Frequency */ 2403 break;
2213 case MT2063_LO1_FREQ: 2404
2214 { 2405 /* Get FIF attenuator limit */
2215 /* read the actual tuner register values for LO1C_1 and LO1C_2 */ 2406 case MT2063_ACFIF_MAX:
2216 status |= 2407 {
2217 MT2063_ReadSub(pInfo->hUserData, 2408 u8 val;
2218 pInfo->address, 2409 status |=
2219 MT2063_REG_LO1C_1, 2410 MT2063_GetReg(pInfo, MT2063_REG_FIF_OV,
2220 &pInfo-> 2411 &val);
2221 reg[MT2063_REG_LO1C_1], 2); 2412 *pValue = val & 0x1f;
2222 Div = pInfo->reg[MT2063_REG_LO1C_1]; 2413 }
2223 Num = pInfo->reg[MT2063_REG_LO1C_2] & 0x3F; 2414 break;
2224 pInfo->AS_Data.f_LO1 = 2415
2225 (pInfo->AS_Data.f_ref * Div) + 2416 /* Get current used DNC output */
2226 MT2063_fLO_FractionalTerm(pInfo->AS_Data. 2417 case MT2063_DNC_OUTPUT_ENABLE:
2227 f_ref, Num, 64); 2418 {
2228 } 2419 if ((pInfo->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
2229 *pValue = pInfo->AS_Data.f_LO1; 2420 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2230 break; 2421 *pValue =
2231 2422 (u32) MT2063_DNC_NONE;
2232 /* LO1 minimum step size */ 2423 else
2233 case MT2063_LO1_STEPSIZE: 2424 *pValue =
2234 *pValue = pInfo->AS_Data.f_LO1_Step; 2425 (u32) MT2063_DNC_2;
2235 break; 2426 } else { /* DNC1 is on */
2236 2427
2237 /* LO1 FracN keep-out region */ 2428 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2238 case MT2063_LO1_FRACN_AVOID_PARAM: 2429 *pValue =
2239 *pValue = pInfo->AS_Data.f_LO1_FracN_Avoid; 2430 (u32) MT2063_DNC_1;
2240 break; 2431 else
2241 2432 *pValue =
2242 /* Current 1st IF in use */ 2433 (u32) MT2063_DNC_BOTH;
2243 case MT2063_IF1_ACTUAL: 2434 }
2244 *pValue = pInfo->f_IF1_actual; 2435 }
2245 break; 2436 break;
2246 2437
2247 /* Requested 1st IF */ 2438 /* Get VGA Gain Code */
2248 case MT2063_IF1_REQUEST: 2439 case MT2063_VGAGC:
2249 *pValue = pInfo->AS_Data.f_if1_Request; 2440 *pValue = ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2);
2250 break; 2441 break;
2251 2442
2252 /* Center of 1st IF SAW filter */ 2443 /* Get VGA bias current */
2253 case MT2063_IF1_CENTER: 2444 case MT2063_VGAOI:
2254 *pValue = pInfo->AS_Data.f_if1_Center; 2445 *pValue = (pInfo->reg[MT2063_REG_RSVD_31] & 0x07);
2255 break; 2446 break;
2256 2447
2257 /* Bandwidth of 1st IF SAW filter */ 2448 /* Get TAGC setting */
2258 case MT2063_IF1_BW: 2449 case MT2063_TAGC:
2259 *pValue = pInfo->AS_Data.f_if1_bw; 2450 *pValue = (pInfo->reg[MT2063_REG_RSVD_1E] & 0x03);
2260 break; 2451 break;
2261 2452
2262 /* zero-IF bandwidth */ 2453 /* Get AMP Gain Code */
2263 case MT2063_ZIF_BW: 2454 case MT2063_AMPGC:
2264 *pValue = pInfo->AS_Data.f_zif_bw; 2455 *pValue = (pInfo->reg[MT2063_REG_TEMP_SEL] & 0x03);
2265 break; 2456 break;
2266 2457
2267 /* LO2 Frequency */ 2458 /* Avoid DECT Frequencies */
2268 case MT2063_LO2_FREQ: 2459 case MT2063_AVOID_DECT:
2269 { 2460 *pValue = pInfo->AS_Data.avoidDECT;
2270 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */ 2461 break;
2271 status |= 2462
2272 MT2063_ReadSub(pInfo->hUserData, 2463 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
2273 pInfo->address, 2464 case MT2063_CTFILT_SW:
2274 MT2063_REG_LO2C_1, 2465 *pValue = pInfo->ctfilt_sw;
2275 &pInfo-> 2466 break;
2276 reg[MT2063_REG_LO2C_1], 3); 2467
2277 Div = 2468 case MT2063_EOP:
2278 (pInfo->reg[MT2063_REG_LO2C_1] & 0xFE) >> 1; 2469 default:
2279 Num = 2470 status |= -ERANGE;
2280 ((pInfo-> 2471 }
2281 reg[MT2063_REG_LO2C_1] & 0x01) << 12) |
2282 (pInfo->
2283 reg[MT2063_REG_LO2C_2] << 4) | (pInfo->
2284 reg
2285 [MT2063_REG_LO2C_3]
2286 & 0x00F);
2287 pInfo->AS_Data.f_LO2 =
2288 (pInfo->AS_Data.f_ref * Div) +
2289 MT2063_fLO_FractionalTerm(pInfo->AS_Data.
2290 f_ref, Num, 8191);
2291 }
2292 *pValue = pInfo->AS_Data.f_LO2;
2293 break;
2294
2295 /* LO2 minimum step size */
2296 case MT2063_LO2_STEPSIZE:
2297 *pValue = pInfo->AS_Data.f_LO2_Step;
2298 break;
2299
2300 /* LO2 FracN keep-out region */
2301 case MT2063_LO2_FRACN_AVOID:
2302 *pValue = pInfo->AS_Data.f_LO2_FracN_Avoid;
2303 break;
2304
2305 /* output center frequency */
2306 case MT2063_OUTPUT_FREQ:
2307 *pValue = pInfo->AS_Data.f_out;
2308 break;
2309
2310 /* output bandwidth */
2311 case MT2063_OUTPUT_BW:
2312 *pValue = pInfo->AS_Data.f_out_bw - 750000;
2313 break;
2314
2315 /* min inter-tuner LO separation */
2316 case MT2063_LO_SEPARATION:
2317 *pValue = pInfo->AS_Data.f_min_LO_Separation;
2318 break;
2319
2320 /* ID of avoid-spurs algorithm in use */
2321 case MT2063_AS_ALG:
2322 *pValue = pInfo->AS_Data.nAS_Algorithm;
2323 break;
2324
2325 /* max # of intra-tuner harmonics */
2326 case MT2063_MAX_HARM1:
2327 *pValue = pInfo->AS_Data.maxH1;
2328 break;
2329
2330 /* max # of inter-tuner harmonics */
2331 case MT2063_MAX_HARM2:
2332 *pValue = pInfo->AS_Data.maxH2;
2333 break;
2334
2335 /* # of 1st IF exclusion zones */
2336 case MT2063_EXCL_ZONES:
2337 *pValue = pInfo->AS_Data.nZones;
2338 break;
2339
2340 /* # of spurs found/avoided */
2341 case MT2063_NUM_SPURS:
2342 *pValue = pInfo->AS_Data.nSpursFound;
2343 break;
2344
2345 /* >0 spurs avoided */
2346 case MT2063_SPUR_AVOIDED:
2347 *pValue = pInfo->AS_Data.bSpurAvoided;
2348 break;
2349
2350 /* >0 spurs in output (mathematically) */
2351 case MT2063_SPUR_PRESENT:
2352 *pValue = pInfo->AS_Data.bSpurPresent;
2353 break;
2354
2355 /* Predefined receiver setup combination */
2356 case MT2063_RCVR_MODE:
2357 *pValue = pInfo->rcvr_mode;
2358 break;
2359
2360 case MT2063_PD1:
2361 case MT2063_PD2:
2362 {
2363 u8 mask = (param == MT2063_PD1 ? 0x01 : 0x03); /* PD1 vs PD2 */
2364 u8 orig = (pInfo->reg[MT2063_REG_BYP_CTRL]);
2365 u8 reg = (orig & 0xF1) | mask; /* Only set 3 bits (not 5) */
2366 int i;
2367
2368 *pValue = 0;
2369
2370 /* Initiate ADC output to reg 0x0A */
2371 if (reg != orig)
2372 status |=
2373 MT2063_WriteSub(pInfo->hUserData,
2374 pInfo->address,
2375 MT2063_REG_BYP_CTRL,
2376 &reg, 1);
2377
2378 if (status < 0)
2379 return (status);
2380
2381 for (i = 0; i < 8; i++) {
2382 status |=
2383 MT2063_ReadSub(pInfo->hUserData,
2384 pInfo->address,
2385 MT2063_REG_ADC_OUT,
2386 &pInfo->
2387 reg
2388 [MT2063_REG_ADC_OUT],
2389 1);
2390
2391 if (status >= 0)
2392 *pValue +=
2393 pInfo->
2394 reg[MT2063_REG_ADC_OUT];
2395 else {
2396 if (i)
2397 *pValue /= i;
2398 return (status);
2399 }
2400 }
2401 *pValue /= 8; /* divide by number of reads */
2402 *pValue >>= 2; /* only want 6 MSB's out of 8 */
2403
2404 /* Restore value of Register BYP_CTRL */
2405 if (reg != orig)
2406 status |=
2407 MT2063_WriteSub(pInfo->hUserData,
2408 pInfo->address,
2409 MT2063_REG_BYP_CTRL,
2410 &orig, 1);
2411 }
2412 break;
2413
2414 /* Get LNA attenuator code */
2415 case MT2063_ACLNA:
2416 {
2417 u8 val;
2418 status |=
2419 MT2063_GetReg(pInfo, MT2063_REG_XO_STATUS,
2420 &val);
2421 *pValue = val & 0x1f;
2422 }
2423 break;
2424
2425 /* Get RF attenuator code */
2426 case MT2063_ACRF:
2427 {
2428 u8 val;
2429 status |=
2430 MT2063_GetReg(pInfo, MT2063_REG_RF_STATUS,
2431 &val);
2432 *pValue = val & 0x1f;
2433 }
2434 break;
2435
2436 /* Get FIF attenuator code */
2437 case MT2063_ACFIF:
2438 {
2439 u8 val;
2440 status |=
2441 MT2063_GetReg(pInfo, MT2063_REG_FIF_STATUS,
2442 &val);
2443 *pValue = val & 0x1f;
2444 }
2445 break;
2446
2447 /* Get LNA attenuator limit */
2448 case MT2063_ACLNA_MAX:
2449 {
2450 u8 val;
2451 status |=
2452 MT2063_GetReg(pInfo, MT2063_REG_LNA_OV,
2453 &val);
2454 *pValue = val & 0x1f;
2455 }
2456 break;
2457
2458 /* Get RF attenuator limit */
2459 case MT2063_ACRF_MAX:
2460 {
2461 u8 val;
2462 status |=
2463 MT2063_GetReg(pInfo, MT2063_REG_RF_OV,
2464 &val);
2465 *pValue = val & 0x1f;
2466 }
2467 break;
2468
2469 /* Get FIF attenuator limit */
2470 case MT2063_ACFIF_MAX:
2471 {
2472 u8 val;
2473 status |=
2474 MT2063_GetReg(pInfo, MT2063_REG_FIF_OV,
2475 &val);
2476 *pValue = val & 0x1f;
2477 }
2478 break;
2479
2480 /* Get current used DNC output */
2481 case MT2063_DNC_OUTPUT_ENABLE:
2482 {
2483 if ((pInfo->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
2484 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2485 *pValue =
2486 (u32) MT2063_DNC_NONE;
2487 else
2488 *pValue =
2489 (u32) MT2063_DNC_2;
2490 } else { /* DNC1 is on */
2491
2492 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2493 *pValue =
2494 (u32) MT2063_DNC_1;
2495 else
2496 *pValue =
2497 (u32) MT2063_DNC_BOTH;
2498 }
2499 }
2500 break;
2501
2502 /* Get VGA Gain Code */
2503 case MT2063_VGAGC:
2504 *pValue =
2505 ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2);
2506 break;
2507
2508 /* Get VGA bias current */
2509 case MT2063_VGAOI:
2510 *pValue = (pInfo->reg[MT2063_REG_RSVD_31] & 0x07);
2511 break;
2512
2513 /* Get TAGC setting */
2514 case MT2063_TAGC:
2515 *pValue = (pInfo->reg[MT2063_REG_RSVD_1E] & 0x03);
2516 break;
2517
2518 /* Get AMP Gain Code */
2519 case MT2063_AMPGC:
2520 *pValue = (pInfo->reg[MT2063_REG_TEMP_SEL] & 0x03);
2521 break;
2522
2523 /* Avoid DECT Frequencies */
2524 case MT2063_AVOID_DECT:
2525 *pValue = pInfo->AS_Data.avoidDECT;
2526 break;
2527
2528 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
2529 case MT2063_CTFILT_SW:
2530 *pValue = pInfo->ctfilt_sw;
2531 break;
2532
2533 case MT2063_EOP:
2534 default:
2535 status |= -ERANGE;
2536 }
2537 return (status); 2472 return (status);
2538} 2473}
2539 2474
@@ -2566,22 +2501,17 @@ static u32 MT2063_GetParam(struct MT2063_Info_t *pInfo, enum MT2063_Param param,
2566** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 2501** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2567** 2502**
2568****************************************************************************/ 2503****************************************************************************/
2569static u32 MT2063_GetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 * val) 2504static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val)
2570{ 2505{
2571 u32 status = 0; /* Status to be returned */ 2506 u32 status = 0; /* Status to be returned */
2572 2507
2573 /* Verify that the handle passed points to a valid tuner */
2574 if (MT2063_IsValidHandle(pInfo) == 0)
2575 return -ENODEV;
2576
2577 if (val == NULL) 2508 if (val == NULL)
2578 return -EINVAL; 2509 return -EINVAL;
2579 2510
2580 if (reg >= MT2063_REG_END_REGS) 2511 if (reg >= MT2063_REG_END_REGS)
2581 return -ERANGE; 2512 return -ERANGE;
2582 2513
2583 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address, reg, 2514 status = MT2063_ReadSub(pInfo, reg, &pInfo->reg[reg], 1);
2584 &pInfo->reg[reg], 1);
2585 2515
2586 return (status); 2516 return (status);
2587} 2517}
@@ -2623,7 +2553,7 @@ static u32 MT2063_GetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 * val)
2623** PD2 Target | 40 | 33 | 42 | 42 | 33 | 42 2553** PD2 Target | 40 | 33 | 42 | 42 | 33 | 42
2624** 2554**
2625** 2555**
2626** Parameters: pInfo - ptr to MT2063_Info_t structure 2556** Parameters: pInfo - ptr to mt2063_state structure
2627** Mode - desired reciever mode 2557** Mode - desired reciever mode
2628** 2558**
2629** Usage: status = MT2063_SetReceiverMode(hMT2063, Mode); 2559** Usage: status = MT2063_SetReceiverMode(hMT2063, Mode);
@@ -2669,7 +2599,7 @@ static u32 MT2063_GetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 * val)
2669** removed GCUAUTO / BYPATNDN/UP 2599** removed GCUAUTO / BYPATNDN/UP
2670** 2600**
2671******************************************************************************/ 2601******************************************************************************/
2672static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo, 2602static u32 MT2063_SetReceiverMode(struct mt2063_state *pInfo,
2673 enum MT2063_RCVR_MODES Mode) 2603 enum MT2063_RCVR_MODES Mode)
2674{ 2604{
2675 u32 status = 0; /* Status to be returned */ 2605 u32 status = 0; /* Status to be returned */
@@ -2818,7 +2748,7 @@ static u32 MT2063_SetReceiverMode(struct MT2063_Info_t *pInfo,
2818** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 2748** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2819** 2749**
2820******************************************************************************/ 2750******************************************************************************/
2821static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo) 2751static u32 MT2063_ReInit(struct mt2063_state *pInfo)
2822{ 2752{
2823 u8 all_resets = 0xF0; /* reset/load bits */ 2753 u8 all_resets = 0xF0; /* reset/load bits */
2824 u32 status = 0; /* Status to be returned */ 2754 u32 status = 0; /* Status to be returned */
@@ -2885,13 +2815,8 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2885 0x00 2815 0x00
2886 }; 2816 };
2887 2817
2888 /* Verify that the handle passed points to a valid tuner */
2889 if (MT2063_IsValidHandle(pInfo) == 0)
2890 return -ENODEV;
2891
2892 /* Read the Part/Rev code from the tuner */ 2818 /* Read the Part/Rev code from the tuner */
2893 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address, 2819 status = MT2063_ReadSub(pInfo, MT2063_REG_PART_REV, pInfo->reg, 1);
2894 MT2063_REG_PART_REV, pInfo->reg, 1);
2895 if (status < 0) 2820 if (status < 0)
2896 return status; 2821 return status;
2897 2822
@@ -2902,7 +2827,7 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2902 return -ENODEV; /* Wrong tuner Part/Rev code */ 2827 return -ENODEV; /* Wrong tuner Part/Rev code */
2903 2828
2904 /* Check the 2nd byte of the Part/Rev code from the tuner */ 2829 /* Check the 2nd byte of the Part/Rev code from the tuner */
2905 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address, 2830 status = MT2063_ReadSub(pInfo,
2906 MT2063_REG_RSVD_3B, 2831 MT2063_REG_RSVD_3B,
2907 &pInfo->reg[MT2063_REG_RSVD_3B], 1); 2832 &pInfo->reg[MT2063_REG_RSVD_3B], 1);
2908 2833
@@ -2911,9 +2836,7 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2911 return -ENODEV; /* Wrong tuner Part/Rev code */ 2836 return -ENODEV; /* Wrong tuner Part/Rev code */
2912 2837
2913 /* Reset the tuner */ 2838 /* Reset the tuner */
2914 status = MT2063_WriteSub(pInfo->hUserData, 2839 status = MT2063_WriteSub(pInfo, MT2063_REG_LO2CQ_3, &all_resets, 1);
2915 pInfo->address,
2916 MT2063_REG_LO2CQ_3, &all_resets, 1);
2917 if (status < 0) 2840 if (status < 0)
2918 return status; 2841 return status;
2919 2842
@@ -2940,8 +2863,7 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2940 while (status >= 0 && *def) { 2863 while (status >= 0 && *def) {
2941 u8 reg = *def++; 2864 u8 reg = *def++;
2942 u8 val = *def++; 2865 u8 val = *def++;
2943 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address, reg, 2866 status = MT2063_WriteSub(pInfo, reg, &val, 1);
2944 &val, 1);
2945 } 2867 }
2946 if (status < 0) 2868 if (status < 0)
2947 return status; 2869 return status;
@@ -2951,8 +2873,7 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2951 maxReads = 10; 2873 maxReads = 10;
2952 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) { 2874 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
2953 msleep(2); 2875 msleep(2);
2954 status = MT2063_ReadSub(pInfo->hUserData, 2876 status = MT2063_ReadSub(pInfo,
2955 pInfo->address,
2956 MT2063_REG_XO_STATUS, 2877 MT2063_REG_XO_STATUS,
2957 &pInfo-> 2878 &pInfo->
2958 reg[MT2063_REG_XO_STATUS], 1); 2879 reg[MT2063_REG_XO_STATUS], 1);
@@ -2962,15 +2883,14 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
2962 if (FCRUN != 0) 2883 if (FCRUN != 0)
2963 return -ENODEV; 2884 return -ENODEV;
2964 2885
2965 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address, 2886 status = MT2063_ReadSub(pInfo,
2966 MT2063_REG_FIFFC, 2887 MT2063_REG_FIFFC,
2967 &pInfo->reg[MT2063_REG_FIFFC], 1); 2888 &pInfo->reg[MT2063_REG_FIFFC], 1);
2968 if (status < 0) 2889 if (status < 0)
2969 return status; 2890 return status;
2970 2891
2971 /* Read back all the registers from the tuner */ 2892 /* Read back all the registers from the tuner */
2972 status = MT2063_ReadSub(pInfo->hUserData, 2893 status = MT2063_ReadSub(pInfo,
2973 pInfo->address,
2974 MT2063_REG_PART_REV, 2894 MT2063_REG_PART_REV,
2975 pInfo->reg, MT2063_REG_END_REGS); 2895 pInfo->reg, MT2063_REG_END_REGS);
2976 if (status < 0) 2896 if (status < 0)
@@ -3039,13 +2959,13 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
3039 */ 2959 */
3040 2960
3041 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; 2961 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
3042 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address, 2962 status = MT2063_WriteSub(pInfo,
3043 MT2063_REG_CTUNE_CTRL, 2963 MT2063_REG_CTUNE_CTRL,
3044 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1); 2964 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1);
3045 if (status < 0) 2965 if (status < 0)
3046 return status; 2966 return status;
3047 /* Read the ClearTune filter calibration value */ 2967 /* Read the ClearTune filter calibration value */
3048 status = MT2063_ReadSub(pInfo->hUserData, pInfo->address, 2968 status = MT2063_ReadSub(pInfo,
3049 MT2063_REG_FIFFC, 2969 MT2063_REG_FIFFC,
3050 &pInfo->reg[MT2063_REG_FIFFC], 1); 2970 &pInfo->reg[MT2063_REG_FIFFC], 1);
3051 if (status < 0) 2971 if (status < 0)
@@ -3054,7 +2974,7 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
3054 fcu_osc = pInfo->reg[MT2063_REG_FIFFC]; 2974 fcu_osc = pInfo->reg[MT2063_REG_FIFFC];
3055 2975
3056 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x00; 2976 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
3057 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address, 2977 status = MT2063_WriteSub(pInfo,
3058 MT2063_REG_CTUNE_CTRL, 2978 MT2063_REG_CTUNE_CTRL,
3059 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1); 2979 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1);
3060 if (status < 0) 2980 if (status < 0)
@@ -3150,17 +3070,13 @@ static u32 MT2063_ReInit(struct MT2063_Info_t *pInfo)
3150** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 3070** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
3151** 3071**
3152****************************************************************************/ 3072****************************************************************************/
3153static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo, 3073static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3154 enum MT2063_Param param, 3074 enum MT2063_Param param,
3155 enum MT2063_DNC_Output_Enable nValue) 3075 enum MT2063_DNC_Output_Enable nValue)
3156{ 3076{
3157 u32 status = 0; /* Status to be returned */ 3077 u32 status = 0; /* Status to be returned */
3158 u8 val = 0; 3078 u8 val = 0;
3159 3079
3160 /* Verify that the handle passed points to a valid tuner */
3161 if (MT2063_IsValidHandle(pInfo) == 0)
3162 return -ENODEV;
3163
3164 switch (param) { 3080 switch (param) {
3165 /* crystal frequency */ 3081 /* crystal frequency */
3166 case MT2063_SRO_FREQ: 3082 case MT2063_SRO_FREQ:
@@ -3191,13 +3107,11 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3191 3107
3192 /* Buffer the queue for restoration later and get actual LO2 values. */ 3108 /* Buffer the queue for restoration later and get actual LO2 values. */
3193 status |= 3109 status |=
3194 MT2063_ReadSub(pInfo->hUserData, 3110 MT2063_ReadSub(pInfo,
3195 pInfo->address,
3196 MT2063_REG_LO2CQ_1, 3111 MT2063_REG_LO2CQ_1,
3197 &(tempLO2CQ[0]), 3); 3112 &(tempLO2CQ[0]), 3);
3198 status |= 3113 status |=
3199 MT2063_ReadSub(pInfo->hUserData, 3114 MT2063_ReadSub(pInfo,
3200 pInfo->address,
3201 MT2063_REG_LO2C_1, 3115 MT2063_REG_LO2C_1,
3202 &(tempLO2C[0]), 3); 3116 &(tempLO2C[0]), 3);
3203 3117
@@ -3211,8 +3125,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3211 (tempLO2CQ[2] != tempLO2C[2])) { 3125 (tempLO2CQ[2] != tempLO2C[2])) {
3212 /* put actual LO2 value into queue (with 0 in one-shot bits) */ 3126 /* put actual LO2 value into queue (with 0 in one-shot bits) */
3213 status |= 3127 status |=
3214 MT2063_WriteSub(pInfo->hUserData, 3128 MT2063_WriteSub(pInfo,
3215 pInfo->address,
3216 MT2063_REG_LO2CQ_1, 3129 MT2063_REG_LO2CQ_1,
3217 &(tempLO2C[0]), 3); 3130 &(tempLO2C[0]), 3);
3218 3131
@@ -3239,8 +3152,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3239 pInfo->reg[MT2063_REG_LO1CQ_2] = 3152 pInfo->reg[MT2063_REG_LO1CQ_2] =
3240 (u8) (FracN); 3153 (u8) (FracN);
3241 status |= 3154 status |=
3242 MT2063_WriteSub(pInfo->hUserData, 3155 MT2063_WriteSub(pInfo,
3243 pInfo->address,
3244 MT2063_REG_LO1CQ_1, 3156 MT2063_REG_LO1CQ_1,
3245 &pInfo-> 3157 &pInfo->
3246 reg[MT2063_REG_LO1CQ_1], 2); 3158 reg[MT2063_REG_LO1CQ_1], 2);
@@ -3248,8 +3160,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3248 /* set the one-shot bit to load the pair of LO values */ 3160 /* set the one-shot bit to load the pair of LO values */
3249 tmpOneShot = tempLO2CQ[2] | 0xE0; 3161 tmpOneShot = tempLO2CQ[2] | 0xE0;
3250 status |= 3162 status |=
3251 MT2063_WriteSub(pInfo->hUserData, 3163 MT2063_WriteSub(pInfo,
3252 pInfo->address,
3253 MT2063_REG_LO2CQ_3, 3164 MT2063_REG_LO2CQ_3,
3254 &tmpOneShot, 1); 3165 &tmpOneShot, 1);
3255 3166
@@ -3257,8 +3168,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3257 if (restore) { 3168 if (restore) {
3258 /* put actual LO2 value into queue (0 in one-shot bits) */ 3169 /* put actual LO2 value into queue (0 in one-shot bits) */
3259 status |= 3170 status |=
3260 MT2063_WriteSub(pInfo->hUserData, 3171 MT2063_WriteSub(pInfo,
3261 pInfo->address,
3262 MT2063_REG_LO2CQ_1, 3172 MT2063_REG_LO2CQ_1,
3263 &(tempLO2CQ[0]), 3); 3173 &(tempLO2CQ[0]), 3);
3264 3174
@@ -3271,7 +3181,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3271 tempLO2CQ[2]; 3181 tempLO2CQ[2];
3272 } 3182 }
3273 3183
3274 MT2063_GetParam(pInfo->hUserData, 3184 MT2063_GetParam(pInfo,
3275 MT2063_LO1_FREQ, 3185 MT2063_LO1_FREQ,
3276 &pInfo->AS_Data.f_LO1); 3186 &pInfo->AS_Data.f_LO1);
3277 } 3187 }
@@ -3311,13 +3221,11 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3311 3221
3312 /* Buffer the queue for restoration later and get actual LO2 values. */ 3222 /* Buffer the queue for restoration later and get actual LO2 values. */
3313 status |= 3223 status |=
3314 MT2063_ReadSub(pInfo->hUserData, 3224 MT2063_ReadSub(pInfo,
3315 pInfo->address,
3316 MT2063_REG_LO1CQ_1, 3225 MT2063_REG_LO1CQ_1,
3317 &(tempLO1CQ[0]), 2); 3226 &(tempLO1CQ[0]), 2);
3318 status |= 3227 status |=
3319 MT2063_ReadSub(pInfo->hUserData, 3228 MT2063_ReadSub(pInfo,
3320 pInfo->address,
3321 MT2063_REG_LO1C_1, 3229 MT2063_REG_LO1C_1,
3322 &(tempLO1C[0]), 2); 3230 &(tempLO1C[0]), 2);
3323 3231
@@ -3326,8 +3234,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3326 || (tempLO1CQ[1] != tempLO1C[1])) { 3234 || (tempLO1CQ[1] != tempLO1C[1])) {
3327 /* put actual LO1 value into queue */ 3235 /* put actual LO1 value into queue */
3328 status |= 3236 status |=
3329 MT2063_WriteSub(pInfo->hUserData, 3237 MT2063_WriteSub(pInfo,
3330 pInfo->address,
3331 MT2063_REG_LO1CQ_1, 3238 MT2063_REG_LO1CQ_1,
3332 &(tempLO1C[0]), 2); 3239 &(tempLO1C[0]), 2);
3333 3240
@@ -3353,8 +3260,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3353 pInfo->reg[MT2063_REG_LO2CQ_3] = 3260 pInfo->reg[MT2063_REG_LO2CQ_3] =
3354 (u8) ((FracN2 & 0x0F)); 3261 (u8) ((FracN2 & 0x0F));
3355 status |= 3262 status |=
3356 MT2063_WriteSub(pInfo->hUserData, 3263 MT2063_WriteSub(pInfo,
3357 pInfo->address,
3358 MT2063_REG_LO1CQ_1, 3264 MT2063_REG_LO1CQ_1,
3359 &pInfo-> 3265 &pInfo->
3360 reg[MT2063_REG_LO1CQ_1], 3); 3266 reg[MT2063_REG_LO1CQ_1], 3);
@@ -3363,8 +3269,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3363 tmpOneShot = 3269 tmpOneShot =
3364 pInfo->reg[MT2063_REG_LO2CQ_3] | 0xE0; 3270 pInfo->reg[MT2063_REG_LO2CQ_3] | 0xE0;
3365 status |= 3271 status |=
3366 MT2063_WriteSub(pInfo->hUserData, 3272 MT2063_WriteSub(pInfo,
3367 pInfo->address,
3368 MT2063_REG_LO2CQ_3, 3273 MT2063_REG_LO2CQ_3,
3369 &tmpOneShot, 1); 3274 &tmpOneShot, 1);
3370 3275
@@ -3372,8 +3277,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3372 if (restore) { 3277 if (restore) {
3373 /* put previous LO1 queue value back into queue */ 3278 /* put previous LO1 queue value back into queue */
3374 status |= 3279 status |=
3375 MT2063_WriteSub(pInfo->hUserData, 3280 MT2063_WriteSub(pInfo,
3376 pInfo->address,
3377 MT2063_REG_LO1CQ_1, 3281 MT2063_REG_LO1CQ_1,
3378 &(tempLO1CQ[0]), 2); 3282 &(tempLO1CQ[0]), 2);
3379 3283
@@ -3384,7 +3288,7 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3384 tempLO1CQ[1]; 3288 tempLO1CQ[1];
3385 } 3289 }
3386 3290
3387 MT2063_GetParam(pInfo->hUserData, 3291 MT2063_GetParam(pInfo,
3388 MT2063_LO2_FREQ, 3292 MT2063_LO2_FREQ,
3389 &pInfo->AS_Data.f_LO2); 3293 &pInfo->AS_Data.f_LO2);
3390 } 3294 }
@@ -3769,25 +3673,22 @@ static u32 MT2063_SetParam(struct MT2063_Info_t *pInfo,
3769** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 3673** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
3770** 3674**
3771****************************************************************************/ 3675****************************************************************************/
3772static u32 MT2063_ClearPowerMaskBits(struct MT2063_Info_t *pInfo, enum MT2063_Mask_Bits Bits) 3676static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *pInfo, enum MT2063_Mask_Bits Bits)
3773{ 3677{
3774 u32 status = 0; /* Status to be returned */ 3678 u32 status = 0; /* Status to be returned */
3775 3679
3776 /* Verify that the handle passed points to a valid tuner */
3777 if (MT2063_IsValidHandle(pInfo) == 0)
3778 return -ENODEV;
3779 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */ 3680 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */
3780 if ((Bits & 0xFF00) != 0) { 3681 if ((Bits & 0xFF00) != 0) {
3781 pInfo->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); 3682 pInfo->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
3782 status |= 3683 status |=
3783 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3684 MT2063_WriteSub(pInfo,
3784 MT2063_REG_PWR_2, 3685 MT2063_REG_PWR_2,
3785 &pInfo->reg[MT2063_REG_PWR_2], 1); 3686 &pInfo->reg[MT2063_REG_PWR_2], 1);
3786 } 3687 }
3787 if ((Bits & 0xFF) != 0) { 3688 if ((Bits & 0xFF) != 0) {
3788 pInfo->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); 3689 pInfo->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
3789 status |= 3690 status |=
3790 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3691 MT2063_WriteSub(pInfo,
3791 MT2063_REG_PWR_1, 3692 MT2063_REG_PWR_1,
3792 &pInfo->reg[MT2063_REG_PWR_1], 1); 3693 &pInfo->reg[MT2063_REG_PWR_1], 1);
3793 } 3694 }
@@ -3823,20 +3724,17 @@ static u32 MT2063_ClearPowerMaskBits(struct MT2063_Info_t *pInfo, enum MT2063_Ma
3823** correct wakeup of the LNA 3724** correct wakeup of the LNA
3824** 3725**
3825****************************************************************************/ 3726****************************************************************************/
3826static u32 MT2063_SoftwareShutdown(struct MT2063_Info_t *pInfo, u8 Shutdown) 3727static u32 MT2063_SoftwareShutdown(struct mt2063_state *pInfo, u8 Shutdown)
3827{ 3728{
3828 u32 status = 0; /* Status to be returned */ 3729 u32 status = 0; /* Status to be returned */
3829 3730
3830 /* Verify that the handle passed points to a valid tuner */
3831 if (MT2063_IsValidHandle(pInfo) == 0)
3832 return -ENODEV;
3833 if (Shutdown == 1) 3731 if (Shutdown == 1)
3834 pInfo->reg[MT2063_REG_PWR_1] |= 0x04; /* Turn the bit on */ 3732 pInfo->reg[MT2063_REG_PWR_1] |= 0x04; /* Turn the bit on */
3835 else 3733 else
3836 pInfo->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */ 3734 pInfo->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */
3837 3735
3838 status |= 3736 status |=
3839 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3737 MT2063_WriteSub(pInfo,
3840 MT2063_REG_PWR_1, 3738 MT2063_REG_PWR_1,
3841 &pInfo->reg[MT2063_REG_PWR_1], 1); 3739 &pInfo->reg[MT2063_REG_PWR_1], 1);
3842 3740
@@ -3844,14 +3742,14 @@ static u32 MT2063_SoftwareShutdown(struct MT2063_Info_t *pInfo, u8 Shutdown)
3844 pInfo->reg[MT2063_REG_BYP_CTRL] = 3742 pInfo->reg[MT2063_REG_BYP_CTRL] =
3845 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; 3743 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
3846 status |= 3744 status |=
3847 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3745 MT2063_WriteSub(pInfo,
3848 MT2063_REG_BYP_CTRL, 3746 MT2063_REG_BYP_CTRL,
3849 &pInfo->reg[MT2063_REG_BYP_CTRL], 3747 &pInfo->reg[MT2063_REG_BYP_CTRL],
3850 1); 3748 1);
3851 pInfo->reg[MT2063_REG_BYP_CTRL] = 3749 pInfo->reg[MT2063_REG_BYP_CTRL] =
3852 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F); 3750 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F);
3853 status |= 3751 status |=
3854 MT2063_WriteSub(pInfo->hUserData, pInfo->address, 3752 MT2063_WriteSub(pInfo,
3855 MT2063_REG_BYP_CTRL, 3753 MT2063_REG_BYP_CTRL,
3856 &pInfo->reg[MT2063_REG_BYP_CTRL], 3754 &pInfo->reg[MT2063_REG_BYP_CTRL],
3857 1); 3755 1);
@@ -3888,18 +3786,14 @@ static u32 MT2063_SoftwareShutdown(struct MT2063_Info_t *pInfo, u8 Shutdown)
3888** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 3786** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
3889** 3787**
3890****************************************************************************/ 3788****************************************************************************/
3891static u32 MT2063_SetReg(struct MT2063_Info_t *pInfo, u8 reg, u8 val) 3789static u32 MT2063_SetReg(struct mt2063_state *pInfo, u8 reg, u8 val)
3892{ 3790{
3893 u32 status = 0; /* Status to be returned */ 3791 u32 status = 0; /* Status to be returned */
3894 3792
3895 /* Verify that the handle passed points to a valid tuner */
3896 if (MT2063_IsValidHandle(pInfo) == 0)
3897 return -ENODEV;
3898
3899 if (reg >= MT2063_REG_END_REGS) 3793 if (reg >= MT2063_REG_END_REGS)
3900 status |= -ERANGE; 3794 status |= -ERANGE;
3901 3795
3902 status = MT2063_WriteSub(pInfo->hUserData, pInfo->address, reg, &val, 3796 status = MT2063_WriteSub(pInfo, reg, &val,
3903 1); 3797 1);
3904 if (status >= 0) 3798 if (status >= 0)
3905 pInfo->reg[reg] = val; 3799 pInfo->reg[reg] = val;
@@ -4063,7 +3957,7 @@ static u32 MT2063_CalcLO2Mult(u32 * Div,
4063** cross-over frequency values. 3957** cross-over frequency values.
4064** 3958**
4065****************************************************************************/ 3959****************************************************************************/
4066static u32 FindClearTuneFilter(struct MT2063_Info_t *pInfo, u32 f_in) 3960static u32 FindClearTuneFilter(struct mt2063_state *pInfo, u32 f_in)
4067{ 3961{
4068 u32 RFBand; 3962 u32 RFBand;
4069 u32 idx; /* index loop */ 3963 u32 idx; /* index loop */
@@ -4122,7 +4016,7 @@ static u32 FindClearTuneFilter(struct MT2063_Info_t *pInfo, u32 f_in)
4122** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 4016** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
4123** 4017**
4124****************************************************************************/ 4018****************************************************************************/
4125static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in) 4019static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in)
4126{ /* RF input center frequency */ 4020{ /* RF input center frequency */
4127 4021
4128 u32 status = 0; /* status of operation */ 4022 u32 status = 0; /* status of operation */
@@ -4140,10 +4034,6 @@ static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in)
4140 u8 val; 4034 u8 val;
4141 u32 RFBand; 4035 u32 RFBand;
4142 4036
4143 /* Verify that the handle passed points to a valid tuner */
4144 if (MT2063_IsValidHandle(pInfo) == 0)
4145 return -ENODEV;
4146
4147 /* Check the input and output frequency ranges */ 4037 /* Check the input and output frequency ranges */
4148 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ)) 4038 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ))
4149 return -EINVAL; 4039 return -EINVAL;
@@ -4185,7 +4075,7 @@ static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in)
4185 */ 4075 */
4186 if (status >= 0) { 4076 if (status >= 0) {
4187 status |= 4077 status |=
4188 MT2063_ReadSub(pInfo->hUserData, pInfo->address, 4078 MT2063_ReadSub(pInfo,
4189 MT2063_REG_FIFFC, 4079 MT2063_REG_FIFFC,
4190 &pInfo->reg[MT2063_REG_FIFFC], 1); 4080 &pInfo->reg[MT2063_REG_FIFFC], 1);
4191 fiffc = pInfo->reg[MT2063_REG_FIFFC]; 4081 fiffc = pInfo->reg[MT2063_REG_FIFFC];
@@ -4288,10 +4178,10 @@ static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in)
4288 ** IMPORTANT: There is a required order for writing 4178 ** IMPORTANT: There is a required order for writing
4289 ** (0x05 must follow all the others). 4179 ** (0x05 must follow all the others).
4290 */ 4180 */
4291 status |= MT2063_WriteSub(pInfo->hUserData, pInfo->address, MT2063_REG_LO1CQ_1, &pInfo->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */ 4181 status |= MT2063_WriteSub(pInfo, MT2063_REG_LO1CQ_1, &pInfo->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
4292 if (pInfo->tuner_id == MT2063_B0) { 4182 if (pInfo->tuner_id == MT2063_B0) {
4293 /* Re-write the one-shot bits to trigger the tune operation */ 4183 /* Re-write the one-shot bits to trigger the tune operation */
4294 status |= MT2063_WriteSub(pInfo->hUserData, pInfo->address, MT2063_REG_LO2CQ_3, &pInfo->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ 4184 status |= MT2063_WriteSub(pInfo, MT2063_REG_LO2CQ_3, &pInfo->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
4295 } 4185 }
4296 /* Write out the FIFF offset only if it's changing */ 4186 /* Write out the FIFF offset only if it's changing */
4297 if (pInfo->reg[MT2063_REG_FIFF_OFFSET] != 4187 if (pInfo->reg[MT2063_REG_FIFF_OFFSET] !=
@@ -4299,8 +4189,7 @@ static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in)
4299 pInfo->reg[MT2063_REG_FIFF_OFFSET] = 4189 pInfo->reg[MT2063_REG_FIFF_OFFSET] =
4300 (u8) fiffof; 4190 (u8) fiffof;
4301 status |= 4191 status |=
4302 MT2063_WriteSub(pInfo->hUserData, 4192 MT2063_WriteSub(pInfo,
4303 pInfo->address,
4304 MT2063_REG_FIFF_OFFSET, 4193 MT2063_REG_FIFF_OFFSET,
4305 &pInfo-> 4194 &pInfo->
4306 reg[MT2063_REG_FIFF_OFFSET], 4195 reg[MT2063_REG_FIFF_OFFSET],
@@ -4316,7 +4205,7 @@ static u32 MT2063_Tune(struct MT2063_Info_t *pInfo, u32 f_in)
4316 status |= MT2063_GetLocked(pInfo); 4205 status |= MT2063_GetLocked(pInfo);
4317 } 4206 }
4318 /* 4207 /*
4319 ** If we locked OK, assign calculated data to MT2063_Info_t structure 4208 ** If we locked OK, assign calculated data to mt2063_state structure
4320 */ 4209 */
4321 if (status >= 0) { 4210 if (status >= 0) {
4322 pInfo->f_IF1_actual = pInfo->AS_Data.f_LO1 - f_in; 4211 pInfo->f_IF1_actual = pInfo->AS_Data.f_LO1 - f_in;
@@ -4461,9 +4350,9 @@ static int mt2063_init(struct dvb_frontend *fe)
4461 u32 status = -EINVAL; 4350 u32 status = -EINVAL;
4462 struct mt2063_state *state = fe->tuner_priv; 4351 struct mt2063_state *state = fe->tuner_priv;
4463 4352
4464 status = MT2063_Open(0xC0, &(state->MT2063_ht), fe); 4353 status = MT2063_Open(fe);
4465 status |= MT2063_SoftwareShutdown(state->MT2063_ht, 1); 4354 status |= MT2063_SoftwareShutdown(state, 1);
4466 status |= MT2063_ClearPowerMaskBits(state->MT2063_ht, MT2063_ALL_SD); 4355 status |= MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
4467 4356
4468 if (0 != status) { 4357 if (0 != status) {
4469 printk("%s %d error status = 0x%x!!\n", __func__, __LINE__, 4358 printk("%s %d error status = 0x%x!!\n", __func__, __LINE__,
@@ -4484,9 +4373,9 @@ static int mt2063_get_status(struct dvb_frontend *fe, u32 * status)
4484} 4373}
4485 4374
4486static int mt2063_get_state(struct dvb_frontend *fe, 4375static int mt2063_get_state(struct dvb_frontend *fe,
4487 enum tuner_param param, struct tuner_state *state) 4376 enum tuner_param param, struct tuner_state *tunstate)
4488{ 4377{
4489 struct mt2063_state *mt2063State = fe->tuner_priv; 4378 struct mt2063_state *state = fe->tuner_priv;
4490 4379
4491 switch (param) { 4380 switch (param) {
4492 case DVBFE_TUNER_FREQUENCY: 4381 case DVBFE_TUNER_FREQUENCY:
@@ -4500,21 +4389,19 @@ static int mt2063_get_state(struct dvb_frontend *fe,
4500 //get bandwidth 4389 //get bandwidth
4501 break; 4390 break;
4502 case DVBFE_TUNER_REFCLOCK: 4391 case DVBFE_TUNER_REFCLOCK:
4503 state->refclock = 4392 tunstate->refclock = (u32) MT2063_GetLocked(state);
4504 (u32)
4505 MT2063_GetLocked((void *) (mt2063State->MT2063_ht));
4506 break; 4393 break;
4507 default: 4394 default:
4508 break; 4395 break;
4509 } 4396 }
4510 4397
4511 return (int)state->refclock; 4398 return (int)tunstate->refclock;
4512} 4399}
4513 4400
4514static int mt2063_set_state(struct dvb_frontend *fe, 4401static int mt2063_set_state(struct dvb_frontend *fe,
4515 enum tuner_param param, struct tuner_state *state) 4402 enum tuner_param param, struct tuner_state *tunstate)
4516{ 4403{
4517 struct mt2063_state *mt2063State = fe->tuner_priv; 4404 struct mt2063_state *state = fe->tuner_priv;
4518 u32 status = 0; 4405 u32 status = 0;
4519 4406
4520 switch (param) { 4407 switch (param) {
@@ -4522,11 +4409,11 @@ static int mt2063_set_state(struct dvb_frontend *fe,
4522 //set frequency 4409 //set frequency
4523 4410
4524 status = 4411 status =
4525 MT_Tune_atv((void *) (mt2063State->MT2063_ht), 4412 MT_Tune_atv(state,
4526 state->frequency, state->bandwidth, 4413 tunstate->frequency, tunstate->bandwidth,
4527 mt2063State->tv_type); 4414 state->tv_type);
4528 4415
4529 mt2063State->frequency = state->frequency; 4416 state->frequency = tunstate->frequency;
4530 break; 4417 break;
4531 case DVBFE_TUNER_TUNERSTEP: 4418 case DVBFE_TUNER_TUNERSTEP:
4532 break; 4419 break;
@@ -4534,20 +4421,20 @@ static int mt2063_set_state(struct dvb_frontend *fe,
4534 break; 4421 break;
4535 case DVBFE_TUNER_BANDWIDTH: 4422 case DVBFE_TUNER_BANDWIDTH:
4536 //set bandwidth 4423 //set bandwidth
4537 mt2063State->bandwidth = state->bandwidth; 4424 state->bandwidth = tunstate->bandwidth;
4538 break; 4425 break;
4539 case DVBFE_TUNER_REFCLOCK: 4426 case DVBFE_TUNER_REFCLOCK:
4540 4427
4541 break; 4428 break;
4542 case DVBFE_TUNER_OPEN: 4429 case DVBFE_TUNER_OPEN:
4543 status = MT2063_Open(MT2063_I2C, &(mt2063State->MT2063_ht), fe); 4430 status = MT2063_Open(fe);
4544 break; 4431 break;
4545 case DVBFE_TUNER_SOFTWARE_SHUTDOWN: 4432 case DVBFE_TUNER_SOFTWARE_SHUTDOWN:
4546 status = MT2063_SoftwareShutdown(mt2063State->MT2063_ht, 1); 4433 status = MT2063_SoftwareShutdown(state, 1);
4547 break; 4434 break;
4548 case DVBFE_TUNER_CLEAR_POWER_MASKBITS: 4435 case DVBFE_TUNER_CLEAR_POWER_MASKBITS:
4549 status = 4436 status =
4550 MT2063_ClearPowerMaskBits(mt2063State->MT2063_ht, 4437 MT2063_ClearPowerMaskBits(state,
4551 MT2063_ALL_SD); 4438 MT2063_ALL_SD);
4552 break; 4439 break;
4553 default: 4440 default:
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 04:03:15 -0500