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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-21 12:33:32 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:20:58 -0500
commit8294e3ed418e0521e9c48c3b2653cdec163bbc17 (patch)
treeae3c48b7dc2643f7f3681dc7c489b79c9bbdecd2 /drivers/media/common/tuners
parent4713e225a56858e1fb8eab961b0b6e497ce55945 (diff)
[media] mt2063: Reorder the code to avoid function prototypes
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/common/tuners')
-rw-r--r--drivers/media/common/tuners/mt2063.c331
1 files changed, 150 insertions, 181 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index f9ebe24144a7..0f4bf96b61eb 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -240,48 +240,10 @@ struct mt2063_state {
240 u8 reg[MT2063_REG_END_REGS]; 240 u8 reg[MT2063_REG_END_REGS];
241}; 241};
242 242
243/* Prototypes */
244static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
245 u32 f_min, u32 f_max);
246static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val);
247static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown);
248static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state, enum MT2063_Mask_Bits Bits);
249
250
251/*
252 * Ancillary routines visible outside mt2063
253 */
254unsigned int tuner_MT2063_SoftwareShutdown(struct dvb_frontend *fe)
255{
256 struct mt2063_state *state = fe->tuner_priv;
257 int err = 0;
258
259 err = MT2063_SoftwareShutdown(state, 1);
260 if (err < 0)
261 printk(KERN_ERR "%s: Couldn't shutdown\n", __func__);
262
263 return err;
264}
265EXPORT_SYMBOL_GPL(tuner_MT2063_SoftwareShutdown);
266
267unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
268{
269 struct mt2063_state *state = fe->tuner_priv;
270 int err = 0;
271
272 err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
273 if (err < 0)
274 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
275
276 return err;
277}
278EXPORT_SYMBOL_GPL(tuner_MT2063_ClearPowerMaskBits);
279
280/* 243/*
281 * mt2063_write - Write data into the I2C bus 244 * mt2063_write - Write data into the I2C bus
282 */ 245 */
283static u32 mt2063_write(struct mt2063_state *state, 246static u32 mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len)
284 u8 reg, u8 *data, u32 len)
285{ 247{
286 struct dvb_frontend *fe = state->frontend; 248 struct dvb_frontend *fe = state->frontend;
287 int ret; 249 int ret;
@@ -307,6 +269,26 @@ static u32 mt2063_write(struct mt2063_state *state,
307} 269}
308 270
309/* 271/*
272 * mt2063_write - Write register data into the I2C bus, caching the value
273 */
274static u32 mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val)
275{
276 u32 status;
277
278 if (reg >= MT2063_REG_END_REGS)
279 return -ERANGE;
280
281 status = mt2063_write(state, reg, &val, 1);
282 if (status < 0)
283 return status;
284
285 state->reg[reg] = val;
286
287 return 0;
288}
289
290
291/*
310 * mt2063_read - Read data from the I2C bus 292 * mt2063_read - Read data from the I2C bus
311 */ 293 */
312static u32 mt2063_read(struct mt2063_state *state, 294static u32 mt2063_read(struct mt2063_state *state,
@@ -370,76 +352,6 @@ struct MT2063_FIFZone_t {
370 s32 max_; 352 s32 max_;
371}; 353};
372 354
373/*
374** Reset all exclusion zones.
375** Add zones to protect the PLL FracN regions near zero
376**
377** N/A I 06-17-2008 RSK Ver 1.19: Refactoring avoidance of DECT
378** frequencies into MT_ResetExclZones().
379*/
380static void MT2063_ResetExclZones(struct MT2063_AvoidSpursData_t *pAS_Info)
381{
382 u32 center;
383
384 pAS_Info->nZones = 0; /* this clears the used list */
385 pAS_Info->usedZones = NULL; /* reset ptr */
386 pAS_Info->freeZones = NULL; /* reset ptr */
387
388 center =
389 pAS_Info->f_ref *
390 ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 +
391 pAS_Info->f_in) / pAS_Info->f_ref) - pAS_Info->f_in;
392 while (center <
393 pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
394 pAS_Info->f_LO1_FracN_Avoid) {
395 /* Exclude LO1 FracN */
396 MT2063_AddExclZone(pAS_Info,
397 center - pAS_Info->f_LO1_FracN_Avoid,
398 center - 1);
399 MT2063_AddExclZone(pAS_Info, center + 1,
400 center + pAS_Info->f_LO1_FracN_Avoid);
401 center += pAS_Info->f_ref;
402 }
403
404 center =
405 pAS_Info->f_ref *
406 ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 -
407 pAS_Info->f_out) / pAS_Info->f_ref) + pAS_Info->f_out;
408 while (center <
409 pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
410 pAS_Info->f_LO2_FracN_Avoid) {
411 /* Exclude LO2 FracN */
412 MT2063_AddExclZone(pAS_Info,
413 center - pAS_Info->f_LO2_FracN_Avoid,
414 center - 1);
415 MT2063_AddExclZone(pAS_Info, center + 1,
416 center + pAS_Info->f_LO2_FracN_Avoid);
417 center += pAS_Info->f_ref;
418 }
419
420 if (MT2063_EXCLUDE_US_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
421 /* Exclude LO1 values that conflict with DECT channels */
422 MT2063_AddExclZone(pAS_Info, 1920836000 - pAS_Info->f_in, 1922236000 - pAS_Info->f_in); /* Ctr = 1921.536 */
423 MT2063_AddExclZone(pAS_Info, 1922564000 - pAS_Info->f_in, 1923964000 - pAS_Info->f_in); /* Ctr = 1923.264 */
424 MT2063_AddExclZone(pAS_Info, 1924292000 - pAS_Info->f_in, 1925692000 - pAS_Info->f_in); /* Ctr = 1924.992 */
425 MT2063_AddExclZone(pAS_Info, 1926020000 - pAS_Info->f_in, 1927420000 - pAS_Info->f_in); /* Ctr = 1926.720 */
426 MT2063_AddExclZone(pAS_Info, 1927748000 - pAS_Info->f_in, 1929148000 - pAS_Info->f_in); /* Ctr = 1928.448 */
427 }
428
429 if (MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
430 MT2063_AddExclZone(pAS_Info, 1896644000 - pAS_Info->f_in, 1898044000 - pAS_Info->f_in); /* Ctr = 1897.344 */
431 MT2063_AddExclZone(pAS_Info, 1894916000 - pAS_Info->f_in, 1896316000 - pAS_Info->f_in); /* Ctr = 1895.616 */
432 MT2063_AddExclZone(pAS_Info, 1893188000 - pAS_Info->f_in, 1894588000 - pAS_Info->f_in); /* Ctr = 1893.888 */
433 MT2063_AddExclZone(pAS_Info, 1891460000 - pAS_Info->f_in, 1892860000 - pAS_Info->f_in); /* Ctr = 1892.16 */
434 MT2063_AddExclZone(pAS_Info, 1889732000 - pAS_Info->f_in, 1891132000 - pAS_Info->f_in); /* Ctr = 1890.432 */
435 MT2063_AddExclZone(pAS_Info, 1888004000 - pAS_Info->f_in, 1889404000 - pAS_Info->f_in); /* Ctr = 1888.704 */
436 MT2063_AddExclZone(pAS_Info, 1886276000 - pAS_Info->f_in, 1887676000 - pAS_Info->f_in); /* Ctr = 1886.976 */
437 MT2063_AddExclZone(pAS_Info, 1884548000 - pAS_Info->f_in, 1885948000 - pAS_Info->f_in); /* Ctr = 1885.248 */
438 MT2063_AddExclZone(pAS_Info, 1882820000 - pAS_Info->f_in, 1884220000 - pAS_Info->f_in); /* Ctr = 1883.52 */
439 MT2063_AddExclZone(pAS_Info, 1881092000 - pAS_Info->f_in, 1882492000 - pAS_Info->f_in); /* Ctr = 1881.792 */
440 }
441}
442
443static struct MT2063_ExclZone_t *InsertNode(struct MT2063_AvoidSpursData_t 355static struct MT2063_ExclZone_t *InsertNode(struct MT2063_AvoidSpursData_t
444 *pAS_Info, 356 *pAS_Info,
445 struct MT2063_ExclZone_t *pPrevNode) 357 struct MT2063_ExclZone_t *pPrevNode)
@@ -554,6 +466,76 @@ static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
554 } 466 }
555} 467}
556 468
469/*
470** Reset all exclusion zones.
471** Add zones to protect the PLL FracN regions near zero
472**
473** N/A I 06-17-2008 RSK Ver 1.19: Refactoring avoidance of DECT
474** frequencies into MT_ResetExclZones().
475*/
476static void MT2063_ResetExclZones(struct MT2063_AvoidSpursData_t *pAS_Info)
477{
478 u32 center;
479
480 pAS_Info->nZones = 0; /* this clears the used list */
481 pAS_Info->usedZones = NULL; /* reset ptr */
482 pAS_Info->freeZones = NULL; /* reset ptr */
483
484 center =
485 pAS_Info->f_ref *
486 ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 +
487 pAS_Info->f_in) / pAS_Info->f_ref) - pAS_Info->f_in;
488 while (center <
489 pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
490 pAS_Info->f_LO1_FracN_Avoid) {
491 /* Exclude LO1 FracN */
492 MT2063_AddExclZone(pAS_Info,
493 center - pAS_Info->f_LO1_FracN_Avoid,
494 center - 1);
495 MT2063_AddExclZone(pAS_Info, center + 1,
496 center + pAS_Info->f_LO1_FracN_Avoid);
497 center += pAS_Info->f_ref;
498 }
499
500 center =
501 pAS_Info->f_ref *
502 ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 -
503 pAS_Info->f_out) / pAS_Info->f_ref) + pAS_Info->f_out;
504 while (center <
505 pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
506 pAS_Info->f_LO2_FracN_Avoid) {
507 /* Exclude LO2 FracN */
508 MT2063_AddExclZone(pAS_Info,
509 center - pAS_Info->f_LO2_FracN_Avoid,
510 center - 1);
511 MT2063_AddExclZone(pAS_Info, center + 1,
512 center + pAS_Info->f_LO2_FracN_Avoid);
513 center += pAS_Info->f_ref;
514 }
515
516 if (MT2063_EXCLUDE_US_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
517 /* Exclude LO1 values that conflict with DECT channels */
518 MT2063_AddExclZone(pAS_Info, 1920836000 - pAS_Info->f_in, 1922236000 - pAS_Info->f_in); /* Ctr = 1921.536 */
519 MT2063_AddExclZone(pAS_Info, 1922564000 - pAS_Info->f_in, 1923964000 - pAS_Info->f_in); /* Ctr = 1923.264 */
520 MT2063_AddExclZone(pAS_Info, 1924292000 - pAS_Info->f_in, 1925692000 - pAS_Info->f_in); /* Ctr = 1924.992 */
521 MT2063_AddExclZone(pAS_Info, 1926020000 - pAS_Info->f_in, 1927420000 - pAS_Info->f_in); /* Ctr = 1926.720 */
522 MT2063_AddExclZone(pAS_Info, 1927748000 - pAS_Info->f_in, 1929148000 - pAS_Info->f_in); /* Ctr = 1928.448 */
523 }
524
525 if (MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
526 MT2063_AddExclZone(pAS_Info, 1896644000 - pAS_Info->f_in, 1898044000 - pAS_Info->f_in); /* Ctr = 1897.344 */
527 MT2063_AddExclZone(pAS_Info, 1894916000 - pAS_Info->f_in, 1896316000 - pAS_Info->f_in); /* Ctr = 1895.616 */
528 MT2063_AddExclZone(pAS_Info, 1893188000 - pAS_Info->f_in, 1894588000 - pAS_Info->f_in); /* Ctr = 1893.888 */
529 MT2063_AddExclZone(pAS_Info, 1891460000 - pAS_Info->f_in, 1892860000 - pAS_Info->f_in); /* Ctr = 1892.16 */
530 MT2063_AddExclZone(pAS_Info, 1889732000 - pAS_Info->f_in, 1891132000 - pAS_Info->f_in); /* Ctr = 1890.432 */
531 MT2063_AddExclZone(pAS_Info, 1888004000 - pAS_Info->f_in, 1889404000 - pAS_Info->f_in); /* Ctr = 1888.704 */
532 MT2063_AddExclZone(pAS_Info, 1886276000 - pAS_Info->f_in, 1887676000 - pAS_Info->f_in); /* Ctr = 1886.976 */
533 MT2063_AddExclZone(pAS_Info, 1884548000 - pAS_Info->f_in, 1885948000 - pAS_Info->f_in); /* Ctr = 1885.248 */
534 MT2063_AddExclZone(pAS_Info, 1882820000 - pAS_Info->f_in, 1884220000 - pAS_Info->f_in); /* Ctr = 1883.52 */
535 MT2063_AddExclZone(pAS_Info, 1881092000 - pAS_Info->f_in, 1882492000 - pAS_Info->f_in); /* Ctr = 1881.792 */
536 }
537}
538
557/***************************************************************************** 539/*****************************************************************************
558** 540**
559** Name: MT_ChooseFirstIF 541** Name: MT_ChooseFirstIF
@@ -1121,7 +1103,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1121 if (state->reg[MT2063_REG_DNC_GAIN] != 1103 if (state->reg[MT2063_REG_DNC_GAIN] !=
1122 val) 1104 val)
1123 status |= 1105 status |=
1124 MT2063_SetReg(state, 1106 mt2063_setreg(state,
1125 MT2063_REG_DNC_GAIN, 1107 MT2063_REG_DNC_GAIN,
1126 val); 1108 val);
1127 1109
@@ -1129,7 +1111,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1129 if (state->reg[MT2063_REG_VGA_GAIN] != 1111 if (state->reg[MT2063_REG_VGA_GAIN] !=
1130 val) 1112 val)
1131 status |= 1113 status |=
1132 MT2063_SetReg(state, 1114 mt2063_setreg(state,
1133 MT2063_REG_VGA_GAIN, 1115 MT2063_REG_VGA_GAIN,
1134 val); 1116 val);
1135 1117
@@ -1137,7 +1119,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1137 if (state->reg[MT2063_REG_RSVD_20] != 1119 if (state->reg[MT2063_REG_RSVD_20] !=
1138 val) 1120 val)
1139 status |= 1121 status |=
1140 MT2063_SetReg(state, 1122 mt2063_setreg(state,
1141 MT2063_REG_RSVD_20, 1123 MT2063_REG_RSVD_20,
1142 val); 1124 val);
1143 1125
@@ -1149,7 +1131,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1149 if (state->reg[MT2063_REG_DNC_GAIN] != 1131 if (state->reg[MT2063_REG_DNC_GAIN] !=
1150 val) 1132 val)
1151 status |= 1133 status |=
1152 MT2063_SetReg(state, 1134 mt2063_setreg(state,
1153 MT2063_REG_DNC_GAIN, 1135 MT2063_REG_DNC_GAIN,
1154 val); 1136 val);
1155 1137
@@ -1157,7 +1139,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1157 if (state->reg[MT2063_REG_VGA_GAIN] != 1139 if (state->reg[MT2063_REG_VGA_GAIN] !=
1158 val) 1140 val)
1159 status |= 1141 status |=
1160 MT2063_SetReg(state, 1142 mt2063_setreg(state,
1161 MT2063_REG_VGA_GAIN, 1143 MT2063_REG_VGA_GAIN,
1162 val); 1144 val);
1163 1145
@@ -1165,7 +1147,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1165 if (state->reg[MT2063_REG_RSVD_20] != 1147 if (state->reg[MT2063_REG_RSVD_20] !=
1166 val) 1148 val)
1167 status |= 1149 status |=
1168 MT2063_SetReg(state, 1150 mt2063_setreg(state,
1169 MT2063_REG_RSVD_20, 1151 MT2063_REG_RSVD_20,
1170 val); 1152 val);
1171 1153
@@ -1177,7 +1159,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1177 if (state->reg[MT2063_REG_DNC_GAIN] != 1159 if (state->reg[MT2063_REG_DNC_GAIN] !=
1178 val) 1160 val)
1179 status |= 1161 status |=
1180 MT2063_SetReg(state, 1162 mt2063_setreg(state,
1181 MT2063_REG_DNC_GAIN, 1163 MT2063_REG_DNC_GAIN,
1182 val); 1164 val);
1183 1165
@@ -1185,7 +1167,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1185 if (state->reg[MT2063_REG_VGA_GAIN] != 1167 if (state->reg[MT2063_REG_VGA_GAIN] !=
1186 val) 1168 val)
1187 status |= 1169 status |=
1188 MT2063_SetReg(state, 1170 mt2063_setreg(state,
1189 MT2063_REG_VGA_GAIN, 1171 MT2063_REG_VGA_GAIN,
1190 val); 1172 val);
1191 1173
@@ -1193,7 +1175,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1193 if (state->reg[MT2063_REG_RSVD_20] != 1175 if (state->reg[MT2063_REG_RSVD_20] !=
1194 val) 1176 val)
1195 status |= 1177 status |=
1196 MT2063_SetReg(state, 1178 mt2063_setreg(state,
1197 MT2063_REG_RSVD_20, 1179 MT2063_REG_RSVD_20,
1198 val); 1180 val);
1199 1181
@@ -1205,7 +1187,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1205 if (state->reg[MT2063_REG_DNC_GAIN] != 1187 if (state->reg[MT2063_REG_DNC_GAIN] !=
1206 val) 1188 val)
1207 status |= 1189 status |=
1208 MT2063_SetReg(state, 1190 mt2063_setreg(state,
1209 MT2063_REG_DNC_GAIN, 1191 MT2063_REG_DNC_GAIN,
1210 val); 1192 val);
1211 1193
@@ -1213,7 +1195,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1213 if (state->reg[MT2063_REG_VGA_GAIN] != 1195 if (state->reg[MT2063_REG_VGA_GAIN] !=
1214 val) 1196 val)
1215 status |= 1197 status |=
1216 MT2063_SetReg(state, 1198 mt2063_setreg(state,
1217 MT2063_REG_VGA_GAIN, 1199 MT2063_REG_VGA_GAIN,
1218 val); 1200 val);
1219 1201
@@ -1221,7 +1203,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1221 if (state->reg[MT2063_REG_RSVD_20] != 1203 if (state->reg[MT2063_REG_RSVD_20] !=
1222 val) 1204 val)
1223 status |= 1205 status |=
1224 MT2063_SetReg(state, 1206 mt2063_setreg(state,
1225 MT2063_REG_RSVD_20, 1207 MT2063_REG_RSVD_20,
1226 val); 1208 val);
1227 1209
@@ -1280,7 +1262,7 @@ static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1280** MT_OK - No errors 1262** MT_OK - No errors
1281** MT_COMM_ERR - Serial bus communications error 1263** MT_COMM_ERR - Serial bus communications error
1282** 1264**
1283** Dependencies: MT2063_SetReg - Write a byte of data to a HW register. 1265** Dependencies: mt2063_setreg - Write a byte of data to a HW register.
1284** Assumes that the tuner cache is valid. 1266** Assumes that the tuner cache is valid.
1285** 1267**
1286** Revision History: 1268** Revision History:
@@ -1335,7 +1317,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1335 ? 0x40 : 1317 ? 0x40 :
1336 0x00); 1318 0x00);
1337 if (state->reg[MT2063_REG_PD1_TGT] != val) { 1319 if (state->reg[MT2063_REG_PD1_TGT] != val) {
1338 status |= MT2063_SetReg(state, MT2063_REG_PD1_TGT, val); 1320 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1339 } 1321 }
1340 } 1322 }
1341 1323
@@ -1344,7 +1326,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1344 u8 val = (state-> reg[MT2063_REG_CTRL_2C] & (u8) ~ 0x03) | 1326 u8 val = (state-> reg[MT2063_REG_CTRL_2C] & (u8) ~ 0x03) |
1345 (LNARIN[Mode] & 0x03); 1327 (LNARIN[Mode] & 0x03);
1346 if (state->reg[MT2063_REG_CTRL_2C] != val) 1328 if (state->reg[MT2063_REG_CTRL_2C] != val)
1347 status |= MT2063_SetReg(state, MT2063_REG_CTRL_2C, 1329 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C,
1348 val); 1330 val);
1349 } 1331 }
1350 1332
@@ -1356,17 +1338,17 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1356 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4); 1338 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4);
1357 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) { 1339 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
1358 status |= 1340 status |=
1359 MT2063_SetReg(state, MT2063_REG_FIFF_CTRL2, val); 1341 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
1360 /* trigger FIFF calibration, needed after changing FIFFQ */ 1342 /* trigger FIFF calibration, needed after changing FIFFQ */
1361 val = 1343 val =
1362 (state->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01); 1344 (state->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01);
1363 status |= 1345 status |=
1364 MT2063_SetReg(state, MT2063_REG_FIFF_CTRL, val); 1346 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1365 val = 1347 val =
1366 (state-> 1348 (state->
1367 reg[MT2063_REG_FIFF_CTRL] & (u8) ~ 0x01); 1349 reg[MT2063_REG_FIFF_CTRL] & (u8) ~ 0x01);
1368 status |= 1350 status |=
1369 MT2063_SetReg(state, MT2063_REG_FIFF_CTRL, val); 1351 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1370 } 1352 }
1371 } 1353 }
1372 1354
@@ -1379,7 +1361,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1379 u8 val = (state-> reg[MT2063_REG_LNA_OV] & (u8) ~ 0x1F) | 1361 u8 val = (state-> reg[MT2063_REG_LNA_OV] & (u8) ~ 0x1F) |
1380 (ACLNAMAX[Mode] & 0x1F); 1362 (ACLNAMAX[Mode] & 0x1F);
1381 if (state->reg[MT2063_REG_LNA_OV] != val) 1363 if (state->reg[MT2063_REG_LNA_OV] != val)
1382 status |= MT2063_SetReg(state, MT2063_REG_LNA_OV, val); 1364 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
1383 } 1365 }
1384 1366
1385 /* LNATGT */ 1367 /* LNATGT */
@@ -1387,7 +1369,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1387 u8 val = (state-> reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x3F) | 1369 u8 val = (state-> reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x3F) |
1388 (LNATGT[Mode] & 0x3F); 1370 (LNATGT[Mode] & 0x3F);
1389 if (state->reg[MT2063_REG_LNA_TGT] != val) 1371 if (state->reg[MT2063_REG_LNA_TGT] != val)
1390 status |= MT2063_SetReg(state, MT2063_REG_LNA_TGT, val); 1372 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1391 } 1373 }
1392 1374
1393 /* ACRF */ 1375 /* ACRF */
@@ -1395,7 +1377,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1395 u8 val = (state-> reg[MT2063_REG_RF_OV] & (u8) ~ 0x1F) | 1377 u8 val = (state-> reg[MT2063_REG_RF_OV] & (u8) ~ 0x1F) |
1396 (ACRFMAX[Mode] & 0x1F); 1378 (ACRFMAX[Mode] & 0x1F);
1397 if (state->reg[MT2063_REG_RF_OV] != val) 1379 if (state->reg[MT2063_REG_RF_OV] != val)
1398 status |= MT2063_SetReg(state, MT2063_REG_RF_OV, val); 1380 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
1399 } 1381 }
1400 1382
1401 /* PD1TGT */ 1383 /* PD1TGT */
@@ -1403,7 +1385,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1403 u8 val = (state-> reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x3F) | 1385 u8 val = (state-> reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x3F) |
1404 (PD1TGT[Mode] & 0x3F); 1386 (PD1TGT[Mode] & 0x3F);
1405 if (state->reg[MT2063_REG_PD1_TGT] != val) 1387 if (state->reg[MT2063_REG_PD1_TGT] != val)
1406 status |= MT2063_SetReg(state, MT2063_REG_PD1_TGT, val); 1388 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1407 } 1389 }
1408 1390
1409 /* FIFATN */ 1391 /* FIFATN */
@@ -1414,7 +1396,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1414 val = (state-> reg[MT2063_REG_FIF_OV] & (u8) ~ 0x1F) | 1396 val = (state-> reg[MT2063_REG_FIF_OV] & (u8) ~ 0x1F) |
1415 (val & 0x1F); 1397 (val & 0x1F);
1416 if (state->reg[MT2063_REG_FIF_OV] != val) { 1398 if (state->reg[MT2063_REG_FIF_OV] != val) {
1417 status |= MT2063_SetReg(state, MT2063_REG_FIF_OV, val); 1399 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
1418 } 1400 }
1419 } 1401 }
1420 1402
@@ -1423,7 +1405,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1423 u8 val = (state-> reg[MT2063_REG_PD2_TGT] & (u8) ~ 0x3F) | 1405 u8 val = (state-> reg[MT2063_REG_PD2_TGT] & (u8) ~ 0x3F) |
1424 (PD2TGT[Mode] & 0x3F); 1406 (PD2TGT[Mode] & 0x3F);
1425 if (state->reg[MT2063_REG_PD2_TGT] != val) 1407 if (state->reg[MT2063_REG_PD2_TGT] != val)
1426 status |= MT2063_SetReg(state, MT2063_REG_PD2_TGT, val); 1408 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
1427 } 1409 }
1428 1410
1429 /* Ignore ATN Overload */ 1411 /* Ignore ATN Overload */
@@ -1434,7 +1416,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1434 ? 0x80 : 1416 ? 0x80 :
1435 0x00); 1417 0x00);
1436 if (state->reg[MT2063_REG_LNA_TGT] != val) { 1418 if (state->reg[MT2063_REG_LNA_TGT] != val) {
1437 status |= MT2063_SetReg(state, MT2063_REG_LNA_TGT, val); 1419 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1438 } 1420 }
1439 } 1421 }
1440 1422
@@ -1445,7 +1427,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1445 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x80) | 1427 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x80) |
1446 (FIFOVDIS[Mode] ? 0x80 : 0x00); 1428 (FIFOVDIS[Mode] ? 0x80 : 0x00);
1447 if (state->reg[MT2063_REG_PD1_TGT] != val) { 1429 if (state->reg[MT2063_REG_PD1_TGT] != val) {
1448 status |= MT2063_SetReg(state, MT2063_REG_PD1_TGT, val); 1430 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1449 } 1431 }
1450 } 1432 }
1451 1433
@@ -1566,50 +1548,6 @@ static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
1566 return status; 1548 return status;
1567} 1549}
1568 1550
1569/****************************************************************************
1570**
1571** Name: MT2063_SetReg
1572**
1573** Description: Sets an MT2063 register.
1574**
1575** Parameters: h - Tuner handle (returned by MT2063_Open)
1576** reg - MT2063 register/subaddress location
1577** val - MT2063 register/subaddress value
1578**
1579** Returns: status:
1580** MT_OK - No errors
1581** MT_COMM_ERR - Serial bus communications error
1582** MT_INV_HANDLE - Invalid tuner handle
1583** MT_ARG_RANGE - Argument out of range
1584**
1585** Dependencies: USERS MUST CALL MT2063_Open() FIRST!
1586**
1587** Use this function if you need to override a default
1588** register value
1589**
1590** Revision History:
1591**
1592** SCR Date Author Description
1593** -------------------------------------------------------------------------
1594** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
1595**
1596****************************************************************************/
1597static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val)
1598{
1599 u32 status;
1600
1601 if (reg >= MT2063_REG_END_REGS)
1602 return -ERANGE;
1603
1604 status = mt2063_write(state, reg, &val, 1);
1605 if (status < 0)
1606 return status;
1607
1608 state->reg[reg] = val;
1609
1610 return 0;
1611}
1612
1613static u32 MT2063_Round_fLO(u32 f_LO, u32 f_LO_Step, u32 f_ref) 1551static u32 MT2063_Round_fLO(u32 f_LO, u32 f_LO_Step, u32 f_ref)
1614{ 1552{
1615 return f_ref * (f_LO / f_ref) 1553 return f_ref * (f_LO / f_ref)
@@ -1866,7 +1804,7 @@ static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
1866 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08); 1804 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
1867 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) { 1805 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
1868 status |= 1806 status |=
1869 MT2063_SetReg(state, MT2063_REG_CTUNE_CTRL, val); 1807 mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val);
1870 } 1808 }
1871 val = state->reg[MT2063_REG_CTUNE_OV]; 1809 val = state->reg[MT2063_REG_CTUNE_OV];
1872 RFBand = FindClearTuneFilter(state, f_in); 1810 RFBand = FindClearTuneFilter(state, f_in);
@@ -1875,7 +1813,7 @@ static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
1875 | RFBand); 1813 | RFBand);
1876 if (state->reg[MT2063_REG_CTUNE_OV] != val) { 1814 if (state->reg[MT2063_REG_CTUNE_OV] != val) {
1877 status |= 1815 status |=
1878 MT2063_SetReg(state, MT2063_REG_CTUNE_OV, val); 1816 mt2063_setreg(state, MT2063_REG_CTUNE_OV, val);
1879 } 1817 }
1880 } 1818 }
1881 1819
@@ -2529,6 +2467,37 @@ error:
2529} 2467}
2530EXPORT_SYMBOL_GPL(mt2063_attach); 2468EXPORT_SYMBOL_GPL(mt2063_attach);
2531 2469
2470/*
2471 * Ancillary routines visible outside mt2063
2472 * FIXME: Remove them in favor of using standard tuner callbacks
2473 */
2474unsigned int tuner_MT2063_SoftwareShutdown(struct dvb_frontend *fe)
2475{
2476 struct mt2063_state *state = fe->tuner_priv;
2477 int err = 0;
2478
2479 err = MT2063_SoftwareShutdown(state, 1);
2480 if (err < 0)
2481 printk(KERN_ERR "%s: Couldn't shutdown\n", __func__);
2482
2483 return err;
2484}
2485EXPORT_SYMBOL_GPL(tuner_MT2063_SoftwareShutdown);
2486
2487unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
2488{
2489 struct mt2063_state *state = fe->tuner_priv;
2490 int err = 0;
2491
2492 err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
2493 if (err < 0)
2494 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
2495
2496 return err;
2497}
2498EXPORT_SYMBOL_GPL(tuner_MT2063_ClearPowerMaskBits);
2499
2500
2532MODULE_PARM_DESC(verbose, "Set Verbosity level"); 2501MODULE_PARM_DESC(verbose, "Set Verbosity level");
2533 2502
2534MODULE_AUTHOR("Henry"); 2503MODULE_AUTHOR("Henry");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 19:47:22 -0500