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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-21 01:25:39 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:19:21 -0500
commitdcd52d20d3428d48c2f5b86387252e90e1360573 (patch)
treebaa1956abca801735a9bb8779bd987e4aa25ff5f /drivers/media/common/tuners/mt2063.c
parent51f0f7b3edac87a1b020dc6a58aaf3624a4da40b (diff)
[media] mt2063: Use state for the state structure
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/common/tuners/mt2063.c')
-rw-r--r--drivers/media/common/tuners/mt2063.c830
1 files changed, 415 insertions, 415 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index 66633fa99e82..93015ff659df 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -415,12 +415,12 @@ struct mt2063_state {
415/* Prototypes */ 415/* Prototypes */
416static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info, 416static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
417 u32 f_min, u32 f_max); 417 u32 f_min, u32 f_max);
418static u32 MT2063_ReInit(struct mt2063_state *pInfo); 418static u32 MT2063_ReInit(struct mt2063_state *state);
419static u32 MT2063_Close(struct mt2063_state *pInfo); 419static u32 MT2063_Close(struct mt2063_state *state);
420static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val); 420static u32 MT2063_GetReg(struct mt2063_state *state, u8 reg, u8 * val);
421static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param, u32 * pValue); 421static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param, u32 * pValue);
422static u32 MT2063_SetReg(struct mt2063_state *pInfo, u8 reg, u8 val); 422static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val);
423static u32 MT2063_SetParam(struct mt2063_state *pInfo, enum MT2063_Param param, 423static u32 MT2063_SetParam(struct mt2063_state *state, enum MT2063_Param param,
424 enum MT2063_DNC_Output_Enable nValue); 424 enum MT2063_DNC_Output_Enable nValue);
425 425
426/*****************/ 426/*****************/
@@ -1980,7 +1980,7 @@ static u32 MT2063_Close(struct mt2063_state *state)
1980** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 1980** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
1981** 1981**
1982****************************************************************************/ 1982****************************************************************************/
1983static u32 MT2063_GetLocked(struct mt2063_state *pInfo) 1983static u32 MT2063_GetLocked(struct mt2063_state *state)
1984{ 1984{
1985 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */ 1985 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */
1986 const u32 nPollRate = 2; /* poll status bits every 2 ms */ 1986 const u32 nPollRate = 2; /* poll status bits every 2 ms */
@@ -1991,19 +1991,19 @@ static u32 MT2063_GetLocked(struct mt2063_state *pInfo)
1991 u32 nDelays = 0; 1991 u32 nDelays = 0;
1992 1992
1993 /* LO2 Lock bit was in a different place for B0 version */ 1993 /* LO2 Lock bit was in a different place for B0 version */
1994 if (pInfo->tuner_id == MT2063_B0) 1994 if (state->tuner_id == MT2063_B0)
1995 LO2LK = 0x40; 1995 LO2LK = 0x40;
1996 1996
1997 do { 1997 do {
1998 status |= 1998 status |=
1999 MT2063_ReadSub(pInfo, 1999 MT2063_ReadSub(state,
2000 MT2063_REG_LO_STATUS, 2000 MT2063_REG_LO_STATUS,
2001 &pInfo->reg[MT2063_REG_LO_STATUS], 1); 2001 &state->reg[MT2063_REG_LO_STATUS], 1);
2002 2002
2003 if (status < 0) 2003 if (status < 0)
2004 return (status); 2004 return (status);
2005 2005
2006 if ((pInfo->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) == 2006 if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==
2007 (LO1LK | LO2LK)) { 2007 (LO1LK | LO2LK)) {
2008 return (status); 2008 return (status);
2009 } 2009 }
@@ -2011,9 +2011,9 @@ static u32 MT2063_GetLocked(struct mt2063_state *pInfo)
2011 } 2011 }
2012 while (++nDelays < nMaxLoops); 2012 while (++nDelays < nMaxLoops);
2013 2013
2014 if ((pInfo->reg[MT2063_REG_LO_STATUS] & LO1LK) == 0x00) 2014 if ((state->reg[MT2063_REG_LO_STATUS] & LO1LK) == 0x00)
2015 status |= MT2063_UPC_UNLOCK; 2015 status |= MT2063_UPC_UNLOCK;
2016 if ((pInfo->reg[MT2063_REG_LO_STATUS] & LO2LK) == 0x00) 2016 if ((state->reg[MT2063_REG_LO_STATUS] & LO2LK) == 0x00)
2017 status |= MT2063_DNC_UNLOCK; 2017 status |= MT2063_DNC_UNLOCK;
2018 2018
2019 return (status); 2019 return (status);
@@ -2111,7 +2111,7 @@ static u32 MT2063_GetLocked(struct mt2063_state *pInfo)
2111** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 2111** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2112** 2112**
2113****************************************************************************/ 2113****************************************************************************/
2114static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param, u32 *pValue) 2114static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param, u32 *pValue)
2115{ 2115{
2116 u32 status = 0; /* Status to be returned */ 2116 u32 status = 0; /* Status to be returned */
2117 u32 Div; 2117 u32 Div;
@@ -2123,7 +2123,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2123 switch (param) { 2123 switch (param) {
2124 /* Serial Bus address of this tuner */ 2124 /* Serial Bus address of this tuner */
2125 case MT2063_IC_ADDR: 2125 case MT2063_IC_ADDR:
2126 *pValue = pInfo->config->tuner_address; 2126 *pValue = state->config->tuner_address;
2127 break; 2127 break;
2128 2128
2129 /* Max # of MT2063's allowed to be open */ 2129 /* Max # of MT2063's allowed to be open */
@@ -2138,17 +2138,17 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2138 2138
2139 /* crystal frequency */ 2139 /* crystal frequency */
2140 case MT2063_SRO_FREQ: 2140 case MT2063_SRO_FREQ:
2141 *pValue = pInfo->AS_Data.f_ref; 2141 *pValue = state->AS_Data.f_ref;
2142 break; 2142 break;
2143 2143
2144 /* minimum tuning step size */ 2144 /* minimum tuning step size */
2145 case MT2063_STEPSIZE: 2145 case MT2063_STEPSIZE:
2146 *pValue = pInfo->AS_Data.f_LO2_Step; 2146 *pValue = state->AS_Data.f_LO2_Step;
2147 break; 2147 break;
2148 2148
2149 /* input center frequency */ 2149 /* input center frequency */
2150 case MT2063_INPUT_FREQ: 2150 case MT2063_INPUT_FREQ:
2151 *pValue = pInfo->AS_Data.f_in; 2151 *pValue = state->AS_Data.f_in;
2152 break; 2152 break;
2153 2153
2154 /* LO1 Frequency */ 2154 /* LO1 Frequency */
@@ -2156,53 +2156,53 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2156 { 2156 {
2157 /* read the actual tuner register values for LO1C_1 and LO1C_2 */ 2157 /* read the actual tuner register values for LO1C_1 and LO1C_2 */
2158 status |= 2158 status |=
2159 MT2063_ReadSub(pInfo, 2159 MT2063_ReadSub(state,
2160 MT2063_REG_LO1C_1, 2160 MT2063_REG_LO1C_1,
2161 &pInfo-> 2161 &state->
2162 reg[MT2063_REG_LO1C_1], 2); 2162 reg[MT2063_REG_LO1C_1], 2);
2163 Div = pInfo->reg[MT2063_REG_LO1C_1]; 2163 Div = state->reg[MT2063_REG_LO1C_1];
2164 Num = pInfo->reg[MT2063_REG_LO1C_2] & 0x3F; 2164 Num = state->reg[MT2063_REG_LO1C_2] & 0x3F;
2165 pInfo->AS_Data.f_LO1 = 2165 state->AS_Data.f_LO1 =
2166 (pInfo->AS_Data.f_ref * Div) + 2166 (state->AS_Data.f_ref * Div) +
2167 MT2063_fLO_FractionalTerm(pInfo->AS_Data. 2167 MT2063_fLO_FractionalTerm(state->AS_Data.
2168 f_ref, Num, 64); 2168 f_ref, Num, 64);
2169 } 2169 }
2170 *pValue = pInfo->AS_Data.f_LO1; 2170 *pValue = state->AS_Data.f_LO1;
2171 break; 2171 break;
2172 2172
2173 /* LO1 minimum step size */ 2173 /* LO1 minimum step size */
2174 case MT2063_LO1_STEPSIZE: 2174 case MT2063_LO1_STEPSIZE:
2175 *pValue = pInfo->AS_Data.f_LO1_Step; 2175 *pValue = state->AS_Data.f_LO1_Step;
2176 break; 2176 break;
2177 2177
2178 /* LO1 FracN keep-out region */ 2178 /* LO1 FracN keep-out region */
2179 case MT2063_LO1_FRACN_AVOID_PARAM: 2179 case MT2063_LO1_FRACN_AVOID_PARAM:
2180 *pValue = pInfo->AS_Data.f_LO1_FracN_Avoid; 2180 *pValue = state->AS_Data.f_LO1_FracN_Avoid;
2181 break; 2181 break;
2182 2182
2183 /* Current 1st IF in use */ 2183 /* Current 1st IF in use */
2184 case MT2063_IF1_ACTUAL: 2184 case MT2063_IF1_ACTUAL:
2185 *pValue = pInfo->f_IF1_actual; 2185 *pValue = state->f_IF1_actual;
2186 break; 2186 break;
2187 2187
2188 /* Requested 1st IF */ 2188 /* Requested 1st IF */
2189 case MT2063_IF1_REQUEST: 2189 case MT2063_IF1_REQUEST:
2190 *pValue = pInfo->AS_Data.f_if1_Request; 2190 *pValue = state->AS_Data.f_if1_Request;
2191 break; 2191 break;
2192 2192
2193 /* Center of 1st IF SAW filter */ 2193 /* Center of 1st IF SAW filter */
2194 case MT2063_IF1_CENTER: 2194 case MT2063_IF1_CENTER:
2195 *pValue = pInfo->AS_Data.f_if1_Center; 2195 *pValue = state->AS_Data.f_if1_Center;
2196 break; 2196 break;
2197 2197
2198 /* Bandwidth of 1st IF SAW filter */ 2198 /* Bandwidth of 1st IF SAW filter */
2199 case MT2063_IF1_BW: 2199 case MT2063_IF1_BW:
2200 *pValue = pInfo->AS_Data.f_if1_bw; 2200 *pValue = state->AS_Data.f_if1_bw;
2201 break; 2201 break;
2202 2202
2203 /* zero-IF bandwidth */ 2203 /* zero-IF bandwidth */
2204 case MT2063_ZIF_BW: 2204 case MT2063_ZIF_BW:
2205 *pValue = pInfo->AS_Data.f_zif_bw; 2205 *pValue = state->AS_Data.f_zif_bw;
2206 break; 2206 break;
2207 2207
2208 /* LO2 Frequency */ 2208 /* LO2 Frequency */
@@ -2210,97 +2210,97 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2210 { 2210 {
2211 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */ 2211 /* Read the actual tuner register values for LO2C_1, LO2C_2 and LO2C_3 */
2212 status |= 2212 status |=
2213 MT2063_ReadSub(pInfo, 2213 MT2063_ReadSub(state,
2214 MT2063_REG_LO2C_1, 2214 MT2063_REG_LO2C_1,
2215 &pInfo-> 2215 &state->
2216 reg[MT2063_REG_LO2C_1], 3); 2216 reg[MT2063_REG_LO2C_1], 3);
2217 Div = 2217 Div =
2218 (pInfo->reg[MT2063_REG_LO2C_1] & 0xFE) >> 1; 2218 (state->reg[MT2063_REG_LO2C_1] & 0xFE) >> 1;
2219 Num = 2219 Num =
2220 ((pInfo-> 2220 ((state->
2221 reg[MT2063_REG_LO2C_1] & 0x01) << 12) | 2221 reg[MT2063_REG_LO2C_1] & 0x01) << 12) |
2222 (pInfo-> 2222 (state->
2223 reg[MT2063_REG_LO2C_2] << 4) | (pInfo-> 2223 reg[MT2063_REG_LO2C_2] << 4) | (state->
2224 reg 2224 reg
2225 [MT2063_REG_LO2C_3] 2225 [MT2063_REG_LO2C_3]
2226 & 0x00F); 2226 & 0x00F);
2227 pInfo->AS_Data.f_LO2 = 2227 state->AS_Data.f_LO2 =
2228 (pInfo->AS_Data.f_ref * Div) + 2228 (state->AS_Data.f_ref * Div) +
2229 MT2063_fLO_FractionalTerm(pInfo->AS_Data. 2229 MT2063_fLO_FractionalTerm(state->AS_Data.
2230 f_ref, Num, 8191); 2230 f_ref, Num, 8191);
2231 } 2231 }
2232 *pValue = pInfo->AS_Data.f_LO2; 2232 *pValue = state->AS_Data.f_LO2;
2233 break; 2233 break;
2234 2234
2235 /* LO2 minimum step size */ 2235 /* LO2 minimum step size */
2236 case MT2063_LO2_STEPSIZE: 2236 case MT2063_LO2_STEPSIZE:
2237 *pValue = pInfo->AS_Data.f_LO2_Step; 2237 *pValue = state->AS_Data.f_LO2_Step;
2238 break; 2238 break;
2239 2239
2240 /* LO2 FracN keep-out region */ 2240 /* LO2 FracN keep-out region */
2241 case MT2063_LO2_FRACN_AVOID: 2241 case MT2063_LO2_FRACN_AVOID:
2242 *pValue = pInfo->AS_Data.f_LO2_FracN_Avoid; 2242 *pValue = state->AS_Data.f_LO2_FracN_Avoid;
2243 break; 2243 break;
2244 2244
2245 /* output center frequency */ 2245 /* output center frequency */
2246 case MT2063_OUTPUT_FREQ: 2246 case MT2063_OUTPUT_FREQ:
2247 *pValue = pInfo->AS_Data.f_out; 2247 *pValue = state->AS_Data.f_out;
2248 break; 2248 break;
2249 2249
2250 /* output bandwidth */ 2250 /* output bandwidth */
2251 case MT2063_OUTPUT_BW: 2251 case MT2063_OUTPUT_BW:
2252 *pValue = pInfo->AS_Data.f_out_bw - 750000; 2252 *pValue = state->AS_Data.f_out_bw - 750000;
2253 break; 2253 break;
2254 2254
2255 /* min inter-tuner LO separation */ 2255 /* min inter-tuner LO separation */
2256 case MT2063_LO_SEPARATION: 2256 case MT2063_LO_SEPARATION:
2257 *pValue = pInfo->AS_Data.f_min_LO_Separation; 2257 *pValue = state->AS_Data.f_min_LO_Separation;
2258 break; 2258 break;
2259 2259
2260 /* ID of avoid-spurs algorithm in use */ 2260 /* ID of avoid-spurs algorithm in use */
2261 case MT2063_AS_ALG: 2261 case MT2063_AS_ALG:
2262 *pValue = pInfo->AS_Data.nAS_Algorithm; 2262 *pValue = state->AS_Data.nAS_Algorithm;
2263 break; 2263 break;
2264 2264
2265 /* max # of intra-tuner harmonics */ 2265 /* max # of intra-tuner harmonics */
2266 case MT2063_MAX_HARM1: 2266 case MT2063_MAX_HARM1:
2267 *pValue = pInfo->AS_Data.maxH1; 2267 *pValue = state->AS_Data.maxH1;
2268 break; 2268 break;
2269 2269
2270 /* max # of inter-tuner harmonics */ 2270 /* max # of inter-tuner harmonics */
2271 case MT2063_MAX_HARM2: 2271 case MT2063_MAX_HARM2:
2272 *pValue = pInfo->AS_Data.maxH2; 2272 *pValue = state->AS_Data.maxH2;
2273 break; 2273 break;
2274 2274
2275 /* # of 1st IF exclusion zones */ 2275 /* # of 1st IF exclusion zones */
2276 case MT2063_EXCL_ZONES: 2276 case MT2063_EXCL_ZONES:
2277 *pValue = pInfo->AS_Data.nZones; 2277 *pValue = state->AS_Data.nZones;
2278 break; 2278 break;
2279 2279
2280 /* # of spurs found/avoided */ 2280 /* # of spurs found/avoided */
2281 case MT2063_NUM_SPURS: 2281 case MT2063_NUM_SPURS:
2282 *pValue = pInfo->AS_Data.nSpursFound; 2282 *pValue = state->AS_Data.nSpursFound;
2283 break; 2283 break;
2284 2284
2285 /* >0 spurs avoided */ 2285 /* >0 spurs avoided */
2286 case MT2063_SPUR_AVOIDED: 2286 case MT2063_SPUR_AVOIDED:
2287 *pValue = pInfo->AS_Data.bSpurAvoided; 2287 *pValue = state->AS_Data.bSpurAvoided;
2288 break; 2288 break;
2289 2289
2290 /* >0 spurs in output (mathematically) */ 2290 /* >0 spurs in output (mathematically) */
2291 case MT2063_SPUR_PRESENT: 2291 case MT2063_SPUR_PRESENT:
2292 *pValue = pInfo->AS_Data.bSpurPresent; 2292 *pValue = state->AS_Data.bSpurPresent;
2293 break; 2293 break;
2294 2294
2295 /* Predefined receiver setup combination */ 2295 /* Predefined receiver setup combination */
2296 case MT2063_RCVR_MODE: 2296 case MT2063_RCVR_MODE:
2297 *pValue = pInfo->rcvr_mode; 2297 *pValue = state->rcvr_mode;
2298 break; 2298 break;
2299 2299
2300 case MT2063_PD1: 2300 case MT2063_PD1:
2301 case MT2063_PD2: { 2301 case MT2063_PD2: {
2302 u8 mask = (param == MT2063_PD1 ? 0x01 : 0x03); /* PD1 vs PD2 */ 2302 u8 mask = (param == MT2063_PD1 ? 0x01 : 0x03); /* PD1 vs PD2 */
2303 u8 orig = (pInfo->reg[MT2063_REG_BYP_CTRL]); 2303 u8 orig = (state->reg[MT2063_REG_BYP_CTRL]);
2304 u8 reg = (orig & 0xF1) | mask; /* Only set 3 bits (not 5) */ 2304 u8 reg = (orig & 0xF1) | mask; /* Only set 3 bits (not 5) */
2305 int i; 2305 int i;
2306 2306
@@ -2309,7 +2309,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2309 /* Initiate ADC output to reg 0x0A */ 2309 /* Initiate ADC output to reg 0x0A */
2310 if (reg != orig) 2310 if (reg != orig)
2311 status |= 2311 status |=
2312 MT2063_WriteSub(pInfo, 2312 MT2063_WriteSub(state,
2313 MT2063_REG_BYP_CTRL, 2313 MT2063_REG_BYP_CTRL,
2314 &reg, 1); 2314 &reg, 1);
2315 2315
@@ -2318,16 +2318,16 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2318 2318
2319 for (i = 0; i < 8; i++) { 2319 for (i = 0; i < 8; i++) {
2320 status |= 2320 status |=
2321 MT2063_ReadSub(pInfo, 2321 MT2063_ReadSub(state,
2322 MT2063_REG_ADC_OUT, 2322 MT2063_REG_ADC_OUT,
2323 &pInfo-> 2323 &state->
2324 reg 2324 reg
2325 [MT2063_REG_ADC_OUT], 2325 [MT2063_REG_ADC_OUT],
2326 1); 2326 1);
2327 2327
2328 if (status >= 0) 2328 if (status >= 0)
2329 *pValue += 2329 *pValue +=
2330 pInfo-> 2330 state->
2331 reg[MT2063_REG_ADC_OUT]; 2331 reg[MT2063_REG_ADC_OUT];
2332 else { 2332 else {
2333 if (i) 2333 if (i)
@@ -2341,7 +2341,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2341 /* Restore value of Register BYP_CTRL */ 2341 /* Restore value of Register BYP_CTRL */
2342 if (reg != orig) 2342 if (reg != orig)
2343 status |= 2343 status |=
2344 MT2063_WriteSub(pInfo, 2344 MT2063_WriteSub(state,
2345 MT2063_REG_BYP_CTRL, 2345 MT2063_REG_BYP_CTRL,
2346 &orig, 1); 2346 &orig, 1);
2347 } 2347 }
@@ -2352,7 +2352,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2352 { 2352 {
2353 u8 val; 2353 u8 val;
2354 status |= 2354 status |=
2355 MT2063_GetReg(pInfo, MT2063_REG_XO_STATUS, 2355 MT2063_GetReg(state, MT2063_REG_XO_STATUS,
2356 &val); 2356 &val);
2357 *pValue = val & 0x1f; 2357 *pValue = val & 0x1f;
2358 } 2358 }
@@ -2363,7 +2363,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2363 { 2363 {
2364 u8 val; 2364 u8 val;
2365 status |= 2365 status |=
2366 MT2063_GetReg(pInfo, MT2063_REG_RF_STATUS, 2366 MT2063_GetReg(state, MT2063_REG_RF_STATUS,
2367 &val); 2367 &val);
2368 *pValue = val & 0x1f; 2368 *pValue = val & 0x1f;
2369 } 2369 }
@@ -2374,7 +2374,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2374 { 2374 {
2375 u8 val; 2375 u8 val;
2376 status |= 2376 status |=
2377 MT2063_GetReg(pInfo, MT2063_REG_FIF_STATUS, 2377 MT2063_GetReg(state, MT2063_REG_FIF_STATUS,
2378 &val); 2378 &val);
2379 *pValue = val & 0x1f; 2379 *pValue = val & 0x1f;
2380 } 2380 }
@@ -2385,7 +2385,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2385 { 2385 {
2386 u8 val; 2386 u8 val;
2387 status |= 2387 status |=
2388 MT2063_GetReg(pInfo, MT2063_REG_LNA_OV, 2388 MT2063_GetReg(state, MT2063_REG_LNA_OV,
2389 &val); 2389 &val);
2390 *pValue = val & 0x1f; 2390 *pValue = val & 0x1f;
2391 } 2391 }
@@ -2396,7 +2396,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2396 { 2396 {
2397 u8 val; 2397 u8 val;
2398 status |= 2398 status |=
2399 MT2063_GetReg(pInfo, MT2063_REG_RF_OV, 2399 MT2063_GetReg(state, MT2063_REG_RF_OV,
2400 &val); 2400 &val);
2401 *pValue = val & 0x1f; 2401 *pValue = val & 0x1f;
2402 } 2402 }
@@ -2407,7 +2407,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2407 { 2407 {
2408 u8 val; 2408 u8 val;
2409 status |= 2409 status |=
2410 MT2063_GetReg(pInfo, MT2063_REG_FIF_OV, 2410 MT2063_GetReg(state, MT2063_REG_FIF_OV,
2411 &val); 2411 &val);
2412 *pValue = val & 0x1f; 2412 *pValue = val & 0x1f;
2413 } 2413 }
@@ -2416,8 +2416,8 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2416 /* Get current used DNC output */ 2416 /* Get current used DNC output */
2417 case MT2063_DNC_OUTPUT_ENABLE: 2417 case MT2063_DNC_OUTPUT_ENABLE:
2418 { 2418 {
2419 if ((pInfo->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */ 2419 if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
2420 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ 2420 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2421 *pValue = 2421 *pValue =
2422 (u32) MT2063_DNC_NONE; 2422 (u32) MT2063_DNC_NONE;
2423 else 2423 else
@@ -2425,7 +2425,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2425 (u32) MT2063_DNC_2; 2425 (u32) MT2063_DNC_2;
2426 } else { /* DNC1 is on */ 2426 } else { /* DNC1 is on */
2427 2427
2428 if ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ 2428 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
2429 *pValue = 2429 *pValue =
2430 (u32) MT2063_DNC_1; 2430 (u32) MT2063_DNC_1;
2431 else 2431 else
@@ -2437,32 +2437,32 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2437 2437
2438 /* Get VGA Gain Code */ 2438 /* Get VGA Gain Code */
2439 case MT2063_VGAGC: 2439 case MT2063_VGAGC:
2440 *pValue = ((pInfo->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2); 2440 *pValue = ((state->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2);
2441 break; 2441 break;
2442 2442
2443 /* Get VGA bias current */ 2443 /* Get VGA bias current */
2444 case MT2063_VGAOI: 2444 case MT2063_VGAOI:
2445 *pValue = (pInfo->reg[MT2063_REG_RSVD_31] & 0x07); 2445 *pValue = (state->reg[MT2063_REG_RSVD_31] & 0x07);
2446 break; 2446 break;
2447 2447
2448 /* Get TAGC setting */ 2448 /* Get TAGC setting */
2449 case MT2063_TAGC: 2449 case MT2063_TAGC:
2450 *pValue = (pInfo->reg[MT2063_REG_RSVD_1E] & 0x03); 2450 *pValue = (state->reg[MT2063_REG_RSVD_1E] & 0x03);
2451 break; 2451 break;
2452 2452
2453 /* Get AMP Gain Code */ 2453 /* Get AMP Gain Code */
2454 case MT2063_AMPGC: 2454 case MT2063_AMPGC:
2455 *pValue = (pInfo->reg[MT2063_REG_TEMP_SEL] & 0x03); 2455 *pValue = (state->reg[MT2063_REG_TEMP_SEL] & 0x03);
2456 break; 2456 break;
2457 2457
2458 /* Avoid DECT Frequencies */ 2458 /* Avoid DECT Frequencies */
2459 case MT2063_AVOID_DECT: 2459 case MT2063_AVOID_DECT:
2460 *pValue = pInfo->AS_Data.avoidDECT; 2460 *pValue = state->AS_Data.avoidDECT;
2461 break; 2461 break;
2462 2462
2463 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */ 2463 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
2464 case MT2063_CTFILT_SW: 2464 case MT2063_CTFILT_SW:
2465 *pValue = pInfo->ctfilt_sw; 2465 *pValue = state->ctfilt_sw;
2466 break; 2466 break;
2467 2467
2468 case MT2063_EOP: 2468 case MT2063_EOP:
@@ -2501,7 +2501,7 @@ static u32 MT2063_GetParam(struct mt2063_state *pInfo, enum MT2063_Param param,
2501** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 2501** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2502** 2502**
2503****************************************************************************/ 2503****************************************************************************/
2504static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val) 2504static u32 MT2063_GetReg(struct mt2063_state *state, u8 reg, u8 * val)
2505{ 2505{
2506 u32 status = 0; /* Status to be returned */ 2506 u32 status = 0; /* Status to be returned */
2507 2507
@@ -2511,7 +2511,7 @@ static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val)
2511 if (reg >= MT2063_REG_END_REGS) 2511 if (reg >= MT2063_REG_END_REGS)
2512 return -ERANGE; 2512 return -ERANGE;
2513 2513
2514 status = MT2063_ReadSub(pInfo, reg, &pInfo->reg[reg], 1); 2514 status = MT2063_ReadSub(state, reg, &state->reg[reg], 1);
2515 2515
2516 return (status); 2516 return (status);
2517} 2517}
@@ -2553,7 +2553,7 @@ static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val)
2553** PD2 Target | 40 | 33 | 42 | 42 | 33 | 42 2553** PD2 Target | 40 | 33 | 42 | 42 | 33 | 42
2554** 2554**
2555** 2555**
2556** Parameters: pInfo - ptr to mt2063_state structure 2556** Parameters: state - ptr to mt2063_state structure
2557** Mode - desired reciever mode 2557** Mode - desired reciever mode
2558** 2558**
2559** Usage: status = MT2063_SetReceiverMode(hMT2063, Mode); 2559** Usage: status = MT2063_SetReceiverMode(hMT2063, Mode);
@@ -2599,7 +2599,7 @@ static u32 MT2063_GetReg(struct mt2063_state *pInfo, u8 reg, u8 * val)
2599** removed GCUAUTO / BYPATNDN/UP 2599** removed GCUAUTO / BYPATNDN/UP
2600** 2600**
2601******************************************************************************/ 2601******************************************************************************/
2602static u32 MT2063_SetReceiverMode(struct mt2063_state *pInfo, 2602static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
2603 enum MT2063_RCVR_MODES Mode) 2603 enum MT2063_RCVR_MODES Mode)
2604{ 2604{
2605 u32 status = 0; /* Status to be returned */ 2605 u32 status = 0; /* Status to be returned */
@@ -2612,104 +2612,104 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *pInfo,
2612 /* RFAGCen */ 2612 /* RFAGCen */
2613 if (status >= 0) { 2613 if (status >= 0) {
2614 val = 2614 val =
2615 (pInfo-> 2615 (state->
2616 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x40) | (RFAGCEN[Mode] 2616 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x40) | (RFAGCEN[Mode]
2617 ? 0x40 : 2617 ? 0x40 :
2618 0x00); 2618 0x00);
2619 if (pInfo->reg[MT2063_REG_PD1_TGT] != val) { 2619 if (state->reg[MT2063_REG_PD1_TGT] != val) {
2620 status |= MT2063_SetReg(pInfo, MT2063_REG_PD1_TGT, val); 2620 status |= MT2063_SetReg(state, MT2063_REG_PD1_TGT, val);
2621 } 2621 }
2622 } 2622 }
2623 2623
2624 /* LNARin */ 2624 /* LNARin */
2625 if (status >= 0) { 2625 if (status >= 0) {
2626 status |= MT2063_SetParam(pInfo, MT2063_LNA_RIN, LNARIN[Mode]); 2626 status |= MT2063_SetParam(state, MT2063_LNA_RIN, LNARIN[Mode]);
2627 } 2627 }
2628 2628
2629 /* FIFFQEN and FIFFQ */ 2629 /* FIFFQEN and FIFFQ */
2630 if (status >= 0) { 2630 if (status >= 0) {
2631 val = 2631 val =
2632 (pInfo-> 2632 (state->
2633 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~ 0xF0) | 2633 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~ 0xF0) |
2634 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4); 2634 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4);
2635 if (pInfo->reg[MT2063_REG_FIFF_CTRL2] != val) { 2635 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
2636 status |= 2636 status |=
2637 MT2063_SetReg(pInfo, MT2063_REG_FIFF_CTRL2, val); 2637 MT2063_SetReg(state, MT2063_REG_FIFF_CTRL2, val);
2638 /* trigger FIFF calibration, needed after changing FIFFQ */ 2638 /* trigger FIFF calibration, needed after changing FIFFQ */
2639 val = 2639 val =
2640 (pInfo->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01); 2640 (state->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01);
2641 status |= 2641 status |=
2642 MT2063_SetReg(pInfo, MT2063_REG_FIFF_CTRL, val); 2642 MT2063_SetReg(state, MT2063_REG_FIFF_CTRL, val);
2643 val = 2643 val =
2644 (pInfo-> 2644 (state->
2645 reg[MT2063_REG_FIFF_CTRL] & (u8) ~ 0x01); 2645 reg[MT2063_REG_FIFF_CTRL] & (u8) ~ 0x01);
2646 status |= 2646 status |=
2647 MT2063_SetReg(pInfo, MT2063_REG_FIFF_CTRL, val); 2647 MT2063_SetReg(state, MT2063_REG_FIFF_CTRL, val);
2648 } 2648 }
2649 } 2649 }
2650 2650
2651 /* DNC1GC & DNC2GC */ 2651 /* DNC1GC & DNC2GC */
2652 status |= MT2063_GetParam(pInfo, MT2063_DNC_OUTPUT_ENABLE, &longval); 2652 status |= MT2063_GetParam(state, MT2063_DNC_OUTPUT_ENABLE, &longval);
2653 status |= MT2063_SetParam(pInfo, MT2063_DNC_OUTPUT_ENABLE, longval); 2653 status |= MT2063_SetParam(state, MT2063_DNC_OUTPUT_ENABLE, longval);
2654 2654
2655 /* acLNAmax */ 2655 /* acLNAmax */
2656 if (status >= 0) { 2656 if (status >= 0) {
2657 status |= 2657 status |=
2658 MT2063_SetParam(pInfo, MT2063_ACLNA_MAX, ACLNAMAX[Mode]); 2658 MT2063_SetParam(state, MT2063_ACLNA_MAX, ACLNAMAX[Mode]);
2659 } 2659 }
2660 2660
2661 /* LNATGT */ 2661 /* LNATGT */
2662 if (status >= 0) { 2662 if (status >= 0) {
2663 status |= MT2063_SetParam(pInfo, MT2063_LNA_TGT, LNATGT[Mode]); 2663 status |= MT2063_SetParam(state, MT2063_LNA_TGT, LNATGT[Mode]);
2664 } 2664 }
2665 2665
2666 /* ACRF */ 2666 /* ACRF */
2667 if (status >= 0) { 2667 if (status >= 0) {
2668 status |= 2668 status |=
2669 MT2063_SetParam(pInfo, MT2063_ACRF_MAX, ACRFMAX[Mode]); 2669 MT2063_SetParam(state, MT2063_ACRF_MAX, ACRFMAX[Mode]);
2670 } 2670 }
2671 2671
2672 /* PD1TGT */ 2672 /* PD1TGT */
2673 if (status >= 0) { 2673 if (status >= 0) {
2674 status |= MT2063_SetParam(pInfo, MT2063_PD1_TGT, PD1TGT[Mode]); 2674 status |= MT2063_SetParam(state, MT2063_PD1_TGT, PD1TGT[Mode]);
2675 } 2675 }
2676 2676
2677 /* FIFATN */ 2677 /* FIFATN */
2678 if (status >= 0) { 2678 if (status >= 0) {
2679 status |= 2679 status |=
2680 MT2063_SetParam(pInfo, MT2063_ACFIF_MAX, ACFIFMAX[Mode]); 2680 MT2063_SetParam(state, MT2063_ACFIF_MAX, ACFIFMAX[Mode]);
2681 } 2681 }
2682 2682
2683 /* PD2TGT */ 2683 /* PD2TGT */
2684 if (status >= 0) { 2684 if (status >= 0) {
2685 status |= MT2063_SetParam(pInfo, MT2063_PD2_TGT, PD2TGT[Mode]); 2685 status |= MT2063_SetParam(state, MT2063_PD2_TGT, PD2TGT[Mode]);
2686 } 2686 }
2687 2687
2688 /* Ignore ATN Overload */ 2688 /* Ignore ATN Overload */
2689 if (status >= 0) { 2689 if (status >= 0) {
2690 val = 2690 val =
2691 (pInfo-> 2691 (state->
2692 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x80) | (RFOVDIS[Mode] 2692 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x80) | (RFOVDIS[Mode]
2693 ? 0x80 : 2693 ? 0x80 :
2694 0x00); 2694 0x00);
2695 if (pInfo->reg[MT2063_REG_LNA_TGT] != val) { 2695 if (state->reg[MT2063_REG_LNA_TGT] != val) {
2696 status |= MT2063_SetReg(pInfo, MT2063_REG_LNA_TGT, val); 2696 status |= MT2063_SetReg(state, MT2063_REG_LNA_TGT, val);
2697 } 2697 }
2698 } 2698 }
2699 2699
2700 /* Ignore FIF Overload */ 2700 /* Ignore FIF Overload */
2701 if (status >= 0) { 2701 if (status >= 0) {
2702 val = 2702 val =
2703 (pInfo-> 2703 (state->
2704 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x80) | 2704 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x80) |
2705 (FIFOVDIS[Mode] ? 0x80 : 0x00); 2705 (FIFOVDIS[Mode] ? 0x80 : 0x00);
2706 if (pInfo->reg[MT2063_REG_PD1_TGT] != val) { 2706 if (state->reg[MT2063_REG_PD1_TGT] != val) {
2707 status |= MT2063_SetReg(pInfo, MT2063_REG_PD1_TGT, val); 2707 status |= MT2063_SetReg(state, MT2063_REG_PD1_TGT, val);
2708 } 2708 }
2709 } 2709 }
2710 2710
2711 if (status >= 0) 2711 if (status >= 0)
2712 pInfo->rcvr_mode = Mode; 2712 state->rcvr_mode = Mode;
2713 2713
2714 return (status); 2714 return (status);
2715} 2715}
@@ -2748,7 +2748,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *pInfo,
2748** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 2748** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2749** 2749**
2750******************************************************************************/ 2750******************************************************************************/
2751static u32 MT2063_ReInit(struct mt2063_state *pInfo) 2751static u32 MT2063_ReInit(struct mt2063_state *state)
2752{ 2752{
2753 u8 all_resets = 0xF0; /* reset/load bits */ 2753 u8 all_resets = 0xF0; /* reset/load bits */
2754 u32 status = 0; /* Status to be returned */ 2754 u32 status = 0; /* Status to be returned */
@@ -2816,33 +2816,33 @@ static u32 MT2063_ReInit(struct mt2063_state *pInfo)
2816 }; 2816 };
2817 2817
2818 /* Read the Part/Rev code from the tuner */ 2818 /* Read the Part/Rev code from the tuner */
2819 status = MT2063_ReadSub(pInfo, MT2063_REG_PART_REV, pInfo->reg, 1); 2819 status = MT2063_ReadSub(state, MT2063_REG_PART_REV, state->reg, 1);
2820 if (status < 0) 2820 if (status < 0)
2821 return status; 2821 return status;
2822 2822
2823 /* Check the part/rev code */ 2823 /* Check the part/rev code */
2824 if (((pInfo->reg[MT2063_REG_PART_REV] != MT2063_B0) /* MT2063 B0 */ 2824 if (((state->reg[MT2063_REG_PART_REV] != MT2063_B0) /* MT2063 B0 */
2825 &&(pInfo->reg[MT2063_REG_PART_REV] != MT2063_B1) /* MT2063 B1 */ 2825 &&(state->reg[MT2063_REG_PART_REV] != MT2063_B1) /* MT2063 B1 */
2826 &&(pInfo->reg[MT2063_REG_PART_REV] != MT2063_B3))) /* MT2063 B3 */ 2826 &&(state->reg[MT2063_REG_PART_REV] != MT2063_B3))) /* MT2063 B3 */
2827 return -ENODEV; /* Wrong tuner Part/Rev code */ 2827 return -ENODEV; /* Wrong tuner Part/Rev code */
2828 2828
2829 /* Check the 2nd byte of the Part/Rev code from the tuner */ 2829 /* Check the 2nd byte of the Part/Rev code from the tuner */
2830 status = MT2063_ReadSub(pInfo, 2830 status = MT2063_ReadSub(state,
2831 MT2063_REG_RSVD_3B, 2831 MT2063_REG_RSVD_3B,
2832 &pInfo->reg[MT2063_REG_RSVD_3B], 1); 2832 &state->reg[MT2063_REG_RSVD_3B], 1);
2833 2833
2834 if (status >= 0 2834 if (status >= 0
2835 &&((pInfo->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) /* b7 != 0 ==> NOT MT2063 */ 2835 &&((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) /* b7 != 0 ==> NOT MT2063 */
2836 return -ENODEV; /* Wrong tuner Part/Rev code */ 2836 return -ENODEV; /* Wrong tuner Part/Rev code */
2837 2837
2838 /* Reset the tuner */ 2838 /* Reset the tuner */
2839 status = MT2063_WriteSub(pInfo, MT2063_REG_LO2CQ_3, &all_resets, 1); 2839 status = MT2063_WriteSub(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
2840 if (status < 0) 2840 if (status < 0)
2841 return status; 2841 return status;
2842 2842
2843 /* change all of the default values that vary from the HW reset values */ 2843 /* change all of the default values that vary from the HW reset values */
2844 /* def = (pInfo->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */ 2844 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
2845 switch (pInfo->reg[MT2063_REG_PART_REV]) { 2845 switch (state->reg[MT2063_REG_PART_REV]) {
2846 case MT2063_B3: 2846 case MT2063_B3:
2847 def = MT2063B3_defaults; 2847 def = MT2063B3_defaults;
2848 break; 2848 break;
@@ -2863,7 +2863,7 @@ static u32 MT2063_ReInit(struct mt2063_state *pInfo)
2863 while (status >= 0 && *def) { 2863 while (status >= 0 && *def) {
2864 u8 reg = *def++; 2864 u8 reg = *def++;
2865 u8 val = *def++; 2865 u8 val = *def++;
2866 status = MT2063_WriteSub(pInfo, reg, &val, 1); 2866 status = MT2063_WriteSub(state, reg, &val, 1);
2867 } 2867 }
2868 if (status < 0) 2868 if (status < 0)
2869 return status; 2869 return status;
@@ -2873,116 +2873,116 @@ static u32 MT2063_ReInit(struct mt2063_state *pInfo)
2873 maxReads = 10; 2873 maxReads = 10;
2874 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) { 2874 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
2875 msleep(2); 2875 msleep(2);
2876 status = MT2063_ReadSub(pInfo, 2876 status = MT2063_ReadSub(state,
2877 MT2063_REG_XO_STATUS, 2877 MT2063_REG_XO_STATUS,
2878 &pInfo-> 2878 &state->
2879 reg[MT2063_REG_XO_STATUS], 1); 2879 reg[MT2063_REG_XO_STATUS], 1);
2880 FCRUN = (pInfo->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6; 2880 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
2881 } 2881 }
2882 2882
2883 if (FCRUN != 0) 2883 if (FCRUN != 0)
2884 return -ENODEV; 2884 return -ENODEV;
2885 2885
2886 status = MT2063_ReadSub(pInfo, 2886 status = MT2063_ReadSub(state,
2887 MT2063_REG_FIFFC, 2887 MT2063_REG_FIFFC,
2888 &pInfo->reg[MT2063_REG_FIFFC], 1); 2888 &state->reg[MT2063_REG_FIFFC], 1);
2889 if (status < 0) 2889 if (status < 0)
2890 return status; 2890 return status;
2891 2891
2892 /* Read back all the registers from the tuner */ 2892 /* Read back all the registers from the tuner */
2893 status = MT2063_ReadSub(pInfo, 2893 status = MT2063_ReadSub(state,
2894 MT2063_REG_PART_REV, 2894 MT2063_REG_PART_REV,
2895 pInfo->reg, MT2063_REG_END_REGS); 2895 state->reg, MT2063_REG_END_REGS);
2896 if (status < 0) 2896 if (status < 0)
2897 return status; 2897 return status;
2898 2898
2899 /* Initialize the tuner state. */ 2899 /* Initialize the tuner state. */
2900 pInfo->tuner_id = pInfo->reg[MT2063_REG_PART_REV]; 2900 state->tuner_id = state->reg[MT2063_REG_PART_REV];
2901 pInfo->AS_Data.f_ref = MT2063_REF_FREQ; 2901 state->AS_Data.f_ref = MT2063_REF_FREQ;
2902 pInfo->AS_Data.f_if1_Center = (pInfo->AS_Data.f_ref / 8) * 2902 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
2903 ((u32) pInfo->reg[MT2063_REG_FIFFC] + 640); 2903 ((u32) state->reg[MT2063_REG_FIFFC] + 640);
2904 pInfo->AS_Data.f_if1_bw = MT2063_IF1_BW; 2904 state->AS_Data.f_if1_bw = MT2063_IF1_BW;
2905 pInfo->AS_Data.f_out = 43750000UL; 2905 state->AS_Data.f_out = 43750000UL;
2906 pInfo->AS_Data.f_out_bw = 6750000UL; 2906 state->AS_Data.f_out_bw = 6750000UL;
2907 pInfo->AS_Data.f_zif_bw = MT2063_ZIF_BW; 2907 state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
2908 pInfo->AS_Data.f_LO1_Step = pInfo->AS_Data.f_ref / 64; 2908 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
2909 pInfo->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE; 2909 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
2910 pInfo->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1; 2910 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
2911 pInfo->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2; 2911 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
2912 pInfo->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP; 2912 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
2913 pInfo->AS_Data.f_if1_Request = pInfo->AS_Data.f_if1_Center; 2913 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
2914 pInfo->AS_Data.f_LO1 = 2181000000UL; 2914 state->AS_Data.f_LO1 = 2181000000UL;
2915 pInfo->AS_Data.f_LO2 = 1486249786UL; 2915 state->AS_Data.f_LO2 = 1486249786UL;
2916 pInfo->f_IF1_actual = pInfo->AS_Data.f_if1_Center; 2916 state->f_IF1_actual = state->AS_Data.f_if1_Center;
2917 pInfo->AS_Data.f_in = pInfo->AS_Data.f_LO1 - pInfo->f_IF1_actual; 2917 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
2918 pInfo->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID; 2918 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
2919 pInfo->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID; 2919 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
2920 pInfo->num_regs = MT2063_REG_END_REGS; 2920 state->num_regs = MT2063_REG_END_REGS;
2921 pInfo->AS_Data.avoidDECT = MT2063_AVOID_BOTH; 2921 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
2922 pInfo->ctfilt_sw = 0; 2922 state->ctfilt_sw = 0;
2923 2923
2924 pInfo->CTFiltMax[0] = 69230000; 2924 state->CTFiltMax[0] = 69230000;
2925 pInfo->CTFiltMax[1] = 105770000; 2925 state->CTFiltMax[1] = 105770000;
2926 pInfo->CTFiltMax[2] = 140350000; 2926 state->CTFiltMax[2] = 140350000;
2927 pInfo->CTFiltMax[3] = 177110000; 2927 state->CTFiltMax[3] = 177110000;
2928 pInfo->CTFiltMax[4] = 212860000; 2928 state->CTFiltMax[4] = 212860000;
2929 pInfo->CTFiltMax[5] = 241130000; 2929 state->CTFiltMax[5] = 241130000;
2930 pInfo->CTFiltMax[6] = 274370000; 2930 state->CTFiltMax[6] = 274370000;
2931 pInfo->CTFiltMax[7] = 309820000; 2931 state->CTFiltMax[7] = 309820000;
2932 pInfo->CTFiltMax[8] = 342450000; 2932 state->CTFiltMax[8] = 342450000;
2933 pInfo->CTFiltMax[9] = 378870000; 2933 state->CTFiltMax[9] = 378870000;
2934 pInfo->CTFiltMax[10] = 416210000; 2934 state->CTFiltMax[10] = 416210000;
2935 pInfo->CTFiltMax[11] = 456500000; 2935 state->CTFiltMax[11] = 456500000;
2936 pInfo->CTFiltMax[12] = 495790000; 2936 state->CTFiltMax[12] = 495790000;
2937 pInfo->CTFiltMax[13] = 534530000; 2937 state->CTFiltMax[13] = 534530000;
2938 pInfo->CTFiltMax[14] = 572610000; 2938 state->CTFiltMax[14] = 572610000;
2939 pInfo->CTFiltMax[15] = 598970000; 2939 state->CTFiltMax[15] = 598970000;
2940 pInfo->CTFiltMax[16] = 635910000; 2940 state->CTFiltMax[16] = 635910000;
2941 pInfo->CTFiltMax[17] = 672130000; 2941 state->CTFiltMax[17] = 672130000;
2942 pInfo->CTFiltMax[18] = 714840000; 2942 state->CTFiltMax[18] = 714840000;
2943 pInfo->CTFiltMax[19] = 739660000; 2943 state->CTFiltMax[19] = 739660000;
2944 pInfo->CTFiltMax[20] = 770410000; 2944 state->CTFiltMax[20] = 770410000;
2945 pInfo->CTFiltMax[21] = 814660000; 2945 state->CTFiltMax[21] = 814660000;
2946 pInfo->CTFiltMax[22] = 846950000; 2946 state->CTFiltMax[22] = 846950000;
2947 pInfo->CTFiltMax[23] = 867820000; 2947 state->CTFiltMax[23] = 867820000;
2948 pInfo->CTFiltMax[24] = 915980000; 2948 state->CTFiltMax[24] = 915980000;
2949 pInfo->CTFiltMax[25] = 947450000; 2949 state->CTFiltMax[25] = 947450000;
2950 pInfo->CTFiltMax[26] = 983110000; 2950 state->CTFiltMax[26] = 983110000;
2951 pInfo->CTFiltMax[27] = 1021630000; 2951 state->CTFiltMax[27] = 1021630000;
2952 pInfo->CTFiltMax[28] = 1061870000; 2952 state->CTFiltMax[28] = 1061870000;
2953 pInfo->CTFiltMax[29] = 1098330000; 2953 state->CTFiltMax[29] = 1098330000;
2954 pInfo->CTFiltMax[30] = 1138990000; 2954 state->CTFiltMax[30] = 1138990000;
2955 2955
2956 /* 2956 /*
2957 ** Fetch the FCU osc value and use it and the fRef value to 2957 ** Fetch the FCU osc value and use it and the fRef value to
2958 ** scale all of the Band Max values 2958 ** scale all of the Band Max values
2959 */ 2959 */
2960 2960
2961 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; 2961 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
2962 status = MT2063_WriteSub(pInfo, 2962 status = MT2063_WriteSub(state,
2963 MT2063_REG_CTUNE_CTRL, 2963 MT2063_REG_CTUNE_CTRL,
2964 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1); 2964 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2965 if (status < 0) 2965 if (status < 0)
2966 return status; 2966 return status;
2967 /* Read the ClearTune filter calibration value */ 2967 /* Read the ClearTune filter calibration value */
2968 status = MT2063_ReadSub(pInfo, 2968 status = MT2063_ReadSub(state,
2969 MT2063_REG_FIFFC, 2969 MT2063_REG_FIFFC,
2970 &pInfo->reg[MT2063_REG_FIFFC], 1); 2970 &state->reg[MT2063_REG_FIFFC], 1);
2971 if (status < 0) 2971 if (status < 0)
2972 return status; 2972 return status;
2973 2973
2974 fcu_osc = pInfo->reg[MT2063_REG_FIFFC]; 2974 fcu_osc = state->reg[MT2063_REG_FIFFC];
2975 2975
2976 pInfo->reg[MT2063_REG_CTUNE_CTRL] = 0x00; 2976 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
2977 status = MT2063_WriteSub(pInfo, 2977 status = MT2063_WriteSub(state,
2978 MT2063_REG_CTUNE_CTRL, 2978 MT2063_REG_CTUNE_CTRL,
2979 &pInfo->reg[MT2063_REG_CTUNE_CTRL], 1); 2979 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2980 if (status < 0) 2980 if (status < 0)
2981 return status; 2981 return status;
2982 2982
2983 /* Adjust each of the values in the ClearTune filter cross-over table */ 2983 /* Adjust each of the values in the ClearTune filter cross-over table */
2984 for (i = 0; i < 31; i++) 2984 for (i = 0; i < 31; i++)
2985 pInfo->CTFiltMax[i] =(pInfo->CTFiltMax[i] / 768) * (fcu_osc + 640); 2985 state->CTFiltMax[i] =(state->CTFiltMax[i] / 768) * (fcu_osc + 640);
2986 2986
2987 return (status); 2987 return (status);
2988} 2988}
@@ -3070,7 +3070,7 @@ static u32 MT2063_ReInit(struct mt2063_state *pInfo)
3070** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 3070** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
3071** 3071**
3072****************************************************************************/ 3072****************************************************************************/
3073static u32 MT2063_SetParam(struct mt2063_state *pInfo, 3073static u32 MT2063_SetParam(struct mt2063_state *state,
3074 enum MT2063_Param param, 3074 enum MT2063_Param param,
3075 enum MT2063_DNC_Output_Enable nValue) 3075 enum MT2063_DNC_Output_Enable nValue)
3076{ 3076{
@@ -3080,18 +3080,18 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3080 switch (param) { 3080 switch (param) {
3081 /* crystal frequency */ 3081 /* crystal frequency */
3082 case MT2063_SRO_FREQ: 3082 case MT2063_SRO_FREQ:
3083 pInfo->AS_Data.f_ref = nValue; 3083 state->AS_Data.f_ref = nValue;
3084 pInfo->AS_Data.f_LO1_FracN_Avoid = 0; 3084 state->AS_Data.f_LO1_FracN_Avoid = 0;
3085 pInfo->AS_Data.f_LO2_FracN_Avoid = nValue / 80 - 1; 3085 state->AS_Data.f_LO2_FracN_Avoid = nValue / 80 - 1;
3086 pInfo->AS_Data.f_LO1_Step = nValue / 64; 3086 state->AS_Data.f_LO1_Step = nValue / 64;
3087 pInfo->AS_Data.f_if1_Center = 3087 state->AS_Data.f_if1_Center =
3088 (pInfo->AS_Data.f_ref / 8) * 3088 (state->AS_Data.f_ref / 8) *
3089 (pInfo->reg[MT2063_REG_FIFFC] + 640); 3089 (state->reg[MT2063_REG_FIFFC] + 640);
3090 break; 3090 break;
3091 3091
3092 /* minimum tuning step size */ 3092 /* minimum tuning step size */
3093 case MT2063_STEPSIZE: 3093 case MT2063_STEPSIZE:
3094 pInfo->AS_Data.f_LO2_Step = nValue; 3094 state->AS_Data.f_LO2_Step = nValue;
3095 break; 3095 break;
3096 3096
3097 /* LO1 frequency */ 3097 /* LO1 frequency */
@@ -3107,11 +3107,11 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3107 3107
3108 /* Buffer the queue for restoration later and get actual LO2 values. */ 3108 /* Buffer the queue for restoration later and get actual LO2 values. */
3109 status |= 3109 status |=
3110 MT2063_ReadSub(pInfo, 3110 MT2063_ReadSub(state,
3111 MT2063_REG_LO2CQ_1, 3111 MT2063_REG_LO2CQ_1,
3112 &(tempLO2CQ[0]), 3); 3112 &(tempLO2CQ[0]), 3);
3113 status |= 3113 status |=
3114 MT2063_ReadSub(pInfo, 3114 MT2063_ReadSub(state,
3115 MT2063_REG_LO2C_1, 3115 MT2063_REG_LO2C_1,
3116 &(tempLO2C[0]), 3); 3116 &(tempLO2C[0]), 3);
3117 3117
@@ -3125,17 +3125,17 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3125 (tempLO2CQ[2] != tempLO2C[2])) { 3125 (tempLO2CQ[2] != tempLO2C[2])) {
3126 /* put actual LO2 value into queue (with 0 in one-shot bits) */ 3126 /* put actual LO2 value into queue (with 0 in one-shot bits) */
3127 status |= 3127 status |=
3128 MT2063_WriteSub(pInfo, 3128 MT2063_WriteSub(state,
3129 MT2063_REG_LO2CQ_1, 3129 MT2063_REG_LO2CQ_1,
3130 &(tempLO2C[0]), 3); 3130 &(tempLO2C[0]), 3);
3131 3131
3132 if (status == 0) { 3132 if (status == 0) {
3133 /* cache the bytes just written. */ 3133 /* cache the bytes just written. */
3134 pInfo->reg[MT2063_REG_LO2CQ_1] = 3134 state->reg[MT2063_REG_LO2CQ_1] =
3135 tempLO2C[0]; 3135 tempLO2C[0];
3136 pInfo->reg[MT2063_REG_LO2CQ_2] = 3136 state->reg[MT2063_REG_LO2CQ_2] =
3137 tempLO2C[1]; 3137 tempLO2C[1];
3138 pInfo->reg[MT2063_REG_LO2CQ_3] = 3138 state->reg[MT2063_REG_LO2CQ_3] =
3139 tempLO2C[2]; 3139 tempLO2C[2];
3140 } 3140 }
3141 restore = 1; 3141 restore = 1;
@@ -3144,23 +3144,23 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3144 /* Calculate the Divider and Numberator components of LO1 */ 3144 /* Calculate the Divider and Numberator components of LO1 */
3145 status = 3145 status =
3146 MT2063_CalcLO1Mult(&Div, &FracN, nValue, 3146 MT2063_CalcLO1Mult(&Div, &FracN, nValue,
3147 pInfo->AS_Data.f_ref / 3147 state->AS_Data.f_ref /
3148 64, 3148 64,
3149 pInfo->AS_Data.f_ref); 3149 state->AS_Data.f_ref);
3150 pInfo->reg[MT2063_REG_LO1CQ_1] = 3150 state->reg[MT2063_REG_LO1CQ_1] =
3151 (u8) (Div & 0x00FF); 3151 (u8) (Div & 0x00FF);
3152 pInfo->reg[MT2063_REG_LO1CQ_2] = 3152 state->reg[MT2063_REG_LO1CQ_2] =
3153 (u8) (FracN); 3153 (u8) (FracN);
3154 status |= 3154 status |=
3155 MT2063_WriteSub(pInfo, 3155 MT2063_WriteSub(state,
3156 MT2063_REG_LO1CQ_1, 3156 MT2063_REG_LO1CQ_1,
3157 &pInfo-> 3157 &state->
3158 reg[MT2063_REG_LO1CQ_1], 2); 3158 reg[MT2063_REG_LO1CQ_1], 2);
3159 3159
3160 /* set the one-shot bit to load the pair of LO values */ 3160 /* set the one-shot bit to load the pair of LO values */
3161 tmpOneShot = tempLO2CQ[2] | 0xE0; 3161 tmpOneShot = tempLO2CQ[2] | 0xE0;
3162 status |= 3162 status |=
3163 MT2063_WriteSub(pInfo, 3163 MT2063_WriteSub(state,
3164 MT2063_REG_LO2CQ_3, 3164 MT2063_REG_LO2CQ_3,
3165 &tmpOneShot, 1); 3165 &tmpOneShot, 1);
3166 3166
@@ -3168,43 +3168,43 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3168 if (restore) { 3168 if (restore) {
3169 /* put actual LO2 value into queue (0 in one-shot bits) */ 3169 /* put actual LO2 value into queue (0 in one-shot bits) */
3170 status |= 3170 status |=
3171 MT2063_WriteSub(pInfo, 3171 MT2063_WriteSub(state,
3172 MT2063_REG_LO2CQ_1, 3172 MT2063_REG_LO2CQ_1,
3173 &(tempLO2CQ[0]), 3); 3173 &(tempLO2CQ[0]), 3);
3174 3174
3175 /* cache the bytes just written. */ 3175 /* cache the bytes just written. */
3176 pInfo->reg[MT2063_REG_LO2CQ_1] = 3176 state->reg[MT2063_REG_LO2CQ_1] =
3177 tempLO2CQ[0]; 3177 tempLO2CQ[0];
3178 pInfo->reg[MT2063_REG_LO2CQ_2] = 3178 state->reg[MT2063_REG_LO2CQ_2] =
3179 tempLO2CQ[1]; 3179 tempLO2CQ[1];
3180 pInfo->reg[MT2063_REG_LO2CQ_3] = 3180 state->reg[MT2063_REG_LO2CQ_3] =
3181 tempLO2CQ[2]; 3181 tempLO2CQ[2];
3182 } 3182 }
3183 3183
3184 MT2063_GetParam(pInfo, 3184 MT2063_GetParam(state,
3185 MT2063_LO1_FREQ, 3185 MT2063_LO1_FREQ,
3186 &pInfo->AS_Data.f_LO1); 3186 &state->AS_Data.f_LO1);
3187 } 3187 }
3188 break; 3188 break;
3189 3189
3190 /* LO1 minimum step size */ 3190 /* LO1 minimum step size */
3191 case MT2063_LO1_STEPSIZE: 3191 case MT2063_LO1_STEPSIZE:
3192 pInfo->AS_Data.f_LO1_Step = nValue; 3192 state->AS_Data.f_LO1_Step = nValue;
3193 break; 3193 break;
3194 3194
3195 /* LO1 FracN keep-out region */ 3195 /* LO1 FracN keep-out region */
3196 case MT2063_LO1_FRACN_AVOID_PARAM: 3196 case MT2063_LO1_FRACN_AVOID_PARAM:
3197 pInfo->AS_Data.f_LO1_FracN_Avoid = nValue; 3197 state->AS_Data.f_LO1_FracN_Avoid = nValue;
3198 break; 3198 break;
3199 3199
3200 /* Requested 1st IF */ 3200 /* Requested 1st IF */
3201 case MT2063_IF1_REQUEST: 3201 case MT2063_IF1_REQUEST:
3202 pInfo->AS_Data.f_if1_Request = nValue; 3202 state->AS_Data.f_if1_Request = nValue;
3203 break; 3203 break;
3204 3204
3205 /* zero-IF bandwidth */ 3205 /* zero-IF bandwidth */
3206 case MT2063_ZIF_BW: 3206 case MT2063_ZIF_BW:
3207 pInfo->AS_Data.f_zif_bw = nValue; 3207 state->AS_Data.f_zif_bw = nValue;
3208 break; 3208 break;
3209 3209
3210 /* LO2 frequency */ 3210 /* LO2 frequency */
@@ -3221,11 +3221,11 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3221 3221
3222 /* Buffer the queue for restoration later and get actual LO2 values. */ 3222 /* Buffer the queue for restoration later and get actual LO2 values. */
3223 status |= 3223 status |=
3224 MT2063_ReadSub(pInfo, 3224 MT2063_ReadSub(state,
3225 MT2063_REG_LO1CQ_1, 3225 MT2063_REG_LO1CQ_1,
3226 &(tempLO1CQ[0]), 2); 3226 &(tempLO1CQ[0]), 2);
3227 status |= 3227 status |=
3228 MT2063_ReadSub(pInfo, 3228 MT2063_ReadSub(state,
3229 MT2063_REG_LO1C_1, 3229 MT2063_REG_LO1C_1,
3230 &(tempLO1C[0]), 2); 3230 &(tempLO1C[0]), 2);
3231 3231
@@ -3234,14 +3234,14 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3234 || (tempLO1CQ[1] != tempLO1C[1])) { 3234 || (tempLO1CQ[1] != tempLO1C[1])) {
3235 /* put actual LO1 value into queue */ 3235 /* put actual LO1 value into queue */
3236 status |= 3236 status |=
3237 MT2063_WriteSub(pInfo, 3237 MT2063_WriteSub(state,
3238 MT2063_REG_LO1CQ_1, 3238 MT2063_REG_LO1CQ_1,
3239 &(tempLO1C[0]), 2); 3239 &(tempLO1C[0]), 2);
3240 3240
3241 /* cache the bytes just written. */ 3241 /* cache the bytes just written. */
3242 pInfo->reg[MT2063_REG_LO1CQ_1] = 3242 state->reg[MT2063_REG_LO1CQ_1] =
3243 tempLO1C[0]; 3243 tempLO1C[0];
3244 pInfo->reg[MT2063_REG_LO1CQ_2] = 3244 state->reg[MT2063_REG_LO1CQ_2] =
3245 tempLO1C[1]; 3245 tempLO1C[1];
3246 restore = 1; 3246 restore = 1;
3247 } 3247 }
@@ -3249,27 +3249,27 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3249 /* Calculate the Divider and Numberator components of LO2 */ 3249 /* Calculate the Divider and Numberator components of LO2 */
3250 status = 3250 status =
3251 MT2063_CalcLO2Mult(&Div2, &FracN2, nValue, 3251 MT2063_CalcLO2Mult(&Div2, &FracN2, nValue,
3252 pInfo->AS_Data.f_ref / 3252 state->AS_Data.f_ref /
3253 8191, 3253 8191,
3254 pInfo->AS_Data.f_ref); 3254 state->AS_Data.f_ref);
3255 pInfo->reg[MT2063_REG_LO2CQ_1] = 3255 state->reg[MT2063_REG_LO2CQ_1] =
3256 (u8) ((Div2 << 1) | 3256 (u8) ((Div2 << 1) |
3257 ((FracN2 >> 12) & 0x01)) & 0xFF; 3257 ((FracN2 >> 12) & 0x01)) & 0xFF;
3258 pInfo->reg[MT2063_REG_LO2CQ_2] = 3258 state->reg[MT2063_REG_LO2CQ_2] =
3259 (u8) ((FracN2 >> 4) & 0xFF); 3259 (u8) ((FracN2 >> 4) & 0xFF);
3260 pInfo->reg[MT2063_REG_LO2CQ_3] = 3260 state->reg[MT2063_REG_LO2CQ_3] =
3261 (u8) ((FracN2 & 0x0F)); 3261 (u8) ((FracN2 & 0x0F));
3262 status |= 3262 status |=
3263 MT2063_WriteSub(pInfo, 3263 MT2063_WriteSub(state,
3264 MT2063_REG_LO1CQ_1, 3264 MT2063_REG_LO1CQ_1,
3265 &pInfo-> 3265 &state->
3266 reg[MT2063_REG_LO1CQ_1], 3); 3266 reg[MT2063_REG_LO1CQ_1], 3);
3267 3267
3268 /* set the one-shot bit to load the LO values */ 3268 /* set the one-shot bit to load the LO values */
3269 tmpOneShot = 3269 tmpOneShot =
3270 pInfo->reg[MT2063_REG_LO2CQ_3] | 0xE0; 3270 state->reg[MT2063_REG_LO2CQ_3] | 0xE0;
3271 status |= 3271 status |=
3272 MT2063_WriteSub(pInfo, 3272 MT2063_WriteSub(state,
3273 MT2063_REG_LO2CQ_3, 3273 MT2063_REG_LO2CQ_3,
3274 &tmpOneShot, 1); 3274 &tmpOneShot, 1);
3275 3275
@@ -3277,61 +3277,61 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3277 if (restore) { 3277 if (restore) {
3278 /* put previous LO1 queue value back into queue */ 3278 /* put previous LO1 queue value back into queue */
3279 status |= 3279 status |=
3280 MT2063_WriteSub(pInfo, 3280 MT2063_WriteSub(state,
3281 MT2063_REG_LO1CQ_1, 3281 MT2063_REG_LO1CQ_1,
3282 &(tempLO1CQ[0]), 2); 3282 &(tempLO1CQ[0]), 2);
3283 3283
3284 /* cache the bytes just written. */ 3284 /* cache the bytes just written. */
3285 pInfo->reg[MT2063_REG_LO1CQ_1] = 3285 state->reg[MT2063_REG_LO1CQ_1] =
3286 tempLO1CQ[0]; 3286 tempLO1CQ[0];
3287 pInfo->reg[MT2063_REG_LO1CQ_2] = 3287 state->reg[MT2063_REG_LO1CQ_2] =
3288 tempLO1CQ[1]; 3288 tempLO1CQ[1];
3289 } 3289 }
3290 3290
3291 MT2063_GetParam(pInfo, 3291 MT2063_GetParam(state,
3292 MT2063_LO2_FREQ, 3292 MT2063_LO2_FREQ,
3293 &pInfo->AS_Data.f_LO2); 3293 &state->AS_Data.f_LO2);
3294 } 3294 }
3295 break; 3295 break;
3296 3296
3297 /* LO2 minimum step size */ 3297 /* LO2 minimum step size */
3298 case MT2063_LO2_STEPSIZE: 3298 case MT2063_LO2_STEPSIZE:
3299 pInfo->AS_Data.f_LO2_Step = nValue; 3299 state->AS_Data.f_LO2_Step = nValue;
3300 break; 3300 break;
3301 3301
3302 /* LO2 FracN keep-out region */ 3302 /* LO2 FracN keep-out region */
3303 case MT2063_LO2_FRACN_AVOID: 3303 case MT2063_LO2_FRACN_AVOID:
3304 pInfo->AS_Data.f_LO2_FracN_Avoid = nValue; 3304 state->AS_Data.f_LO2_FracN_Avoid = nValue;
3305 break; 3305 break;
3306 3306
3307 /* output center frequency */ 3307 /* output center frequency */
3308 case MT2063_OUTPUT_FREQ: 3308 case MT2063_OUTPUT_FREQ:
3309 pInfo->AS_Data.f_out = nValue; 3309 state->AS_Data.f_out = nValue;
3310 break; 3310 break;
3311 3311
3312 /* output bandwidth */ 3312 /* output bandwidth */
3313 case MT2063_OUTPUT_BW: 3313 case MT2063_OUTPUT_BW:
3314 pInfo->AS_Data.f_out_bw = nValue + 750000; 3314 state->AS_Data.f_out_bw = nValue + 750000;
3315 break; 3315 break;
3316 3316
3317 /* min inter-tuner LO separation */ 3317 /* min inter-tuner LO separation */
3318 case MT2063_LO_SEPARATION: 3318 case MT2063_LO_SEPARATION:
3319 pInfo->AS_Data.f_min_LO_Separation = nValue; 3319 state->AS_Data.f_min_LO_Separation = nValue;
3320 break; 3320 break;
3321 3321
3322 /* max # of intra-tuner harmonics */ 3322 /* max # of intra-tuner harmonics */
3323 case MT2063_MAX_HARM1: 3323 case MT2063_MAX_HARM1:
3324 pInfo->AS_Data.maxH1 = nValue; 3324 state->AS_Data.maxH1 = nValue;
3325 break; 3325 break;
3326 3326
3327 /* max # of inter-tuner harmonics */ 3327 /* max # of inter-tuner harmonics */
3328 case MT2063_MAX_HARM2: 3328 case MT2063_MAX_HARM2:
3329 pInfo->AS_Data.maxH2 = nValue; 3329 state->AS_Data.maxH2 = nValue;
3330 break; 3330 break;
3331 3331
3332 case MT2063_RCVR_MODE: 3332 case MT2063_RCVR_MODE:
3333 status |= 3333 status |=
3334 MT2063_SetReceiverMode(pInfo, 3334 MT2063_SetReceiverMode(state,
3335 (enum MT2063_RCVR_MODES) 3335 (enum MT2063_RCVR_MODES)
3336 nValue); 3336 nValue);
3337 break; 3337 break;
@@ -3339,12 +3339,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3339 /* Set LNA Rin -- nValue is desired value */ 3339 /* Set LNA Rin -- nValue is desired value */
3340 case MT2063_LNA_RIN: 3340 case MT2063_LNA_RIN:
3341 val = 3341 val =
3342 (pInfo-> 3342 (state->
3343 reg[MT2063_REG_CTRL_2C] & (u8) ~ 0x03) | 3343 reg[MT2063_REG_CTRL_2C] & (u8) ~ 0x03) |
3344 (nValue & 0x03); 3344 (nValue & 0x03);
3345 if (pInfo->reg[MT2063_REG_CTRL_2C] != val) { 3345 if (state->reg[MT2063_REG_CTRL_2C] != val) {
3346 status |= 3346 status |=
3347 MT2063_SetReg(pInfo, MT2063_REG_CTRL_2C, 3347 MT2063_SetReg(state, MT2063_REG_CTRL_2C,
3348 val); 3348 val);
3349 } 3349 }
3350 break; 3350 break;
@@ -3352,12 +3352,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3352 /* Set target power level at LNA -- nValue is desired value */ 3352 /* Set target power level at LNA -- nValue is desired value */
3353 case MT2063_LNA_TGT: 3353 case MT2063_LNA_TGT:
3354 val = 3354 val =
3355 (pInfo-> 3355 (state->
3356 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x3F) | 3356 reg[MT2063_REG_LNA_TGT] & (u8) ~ 0x3F) |
3357 (nValue & 0x3F); 3357 (nValue & 0x3F);
3358 if (pInfo->reg[MT2063_REG_LNA_TGT] != val) { 3358 if (state->reg[MT2063_REG_LNA_TGT] != val) {
3359 status |= 3359 status |=
3360 MT2063_SetReg(pInfo, MT2063_REG_LNA_TGT, 3360 MT2063_SetReg(state, MT2063_REG_LNA_TGT,
3361 val); 3361 val);
3362 } 3362 }
3363 break; 3363 break;
@@ -3365,12 +3365,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3365 /* Set target power level at PD1 -- nValue is desired value */ 3365 /* Set target power level at PD1 -- nValue is desired value */
3366 case MT2063_PD1_TGT: 3366 case MT2063_PD1_TGT:
3367 val = 3367 val =
3368 (pInfo-> 3368 (state->
3369 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x3F) | 3369 reg[MT2063_REG_PD1_TGT] & (u8) ~ 0x3F) |
3370 (nValue & 0x3F); 3370 (nValue & 0x3F);
3371 if (pInfo->reg[MT2063_REG_PD1_TGT] != val) { 3371 if (state->reg[MT2063_REG_PD1_TGT] != val) {
3372 status |= 3372 status |=
3373 MT2063_SetReg(pInfo, MT2063_REG_PD1_TGT, 3373 MT2063_SetReg(state, MT2063_REG_PD1_TGT,
3374 val); 3374 val);
3375 } 3375 }
3376 break; 3376 break;
@@ -3378,12 +3378,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3378 /* Set target power level at PD2 -- nValue is desired value */ 3378 /* Set target power level at PD2 -- nValue is desired value */
3379 case MT2063_PD2_TGT: 3379 case MT2063_PD2_TGT:
3380 val = 3380 val =
3381 (pInfo-> 3381 (state->
3382 reg[MT2063_REG_PD2_TGT] & (u8) ~ 0x3F) | 3382 reg[MT2063_REG_PD2_TGT] & (u8) ~ 0x3F) |
3383 (nValue & 0x3F); 3383 (nValue & 0x3F);
3384 if (pInfo->reg[MT2063_REG_PD2_TGT] != val) { 3384 if (state->reg[MT2063_REG_PD2_TGT] != val) {
3385 status |= 3385 status |=
3386 MT2063_SetReg(pInfo, MT2063_REG_PD2_TGT, 3386 MT2063_SetReg(state, MT2063_REG_PD2_TGT,
3387 val); 3387 val);
3388 } 3388 }
3389 break; 3389 break;
@@ -3391,13 +3391,13 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3391 /* Set LNA atten limit -- nValue is desired value */ 3391 /* Set LNA atten limit -- nValue is desired value */
3392 case MT2063_ACLNA_MAX: 3392 case MT2063_ACLNA_MAX:
3393 val = 3393 val =
3394 (pInfo-> 3394 (state->
3395 reg[MT2063_REG_LNA_OV] & (u8) ~ 0x1F) | (nValue 3395 reg[MT2063_REG_LNA_OV] & (u8) ~ 0x1F) | (nValue
3396 & 3396 &
3397 0x1F); 3397 0x1F);
3398 if (pInfo->reg[MT2063_REG_LNA_OV] != val) { 3398 if (state->reg[MT2063_REG_LNA_OV] != val) {
3399 status |= 3399 status |=
3400 MT2063_SetReg(pInfo, MT2063_REG_LNA_OV, 3400 MT2063_SetReg(state, MT2063_REG_LNA_OV,
3401 val); 3401 val);
3402 } 3402 }
3403 break; 3403 break;
@@ -3405,29 +3405,29 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3405 /* Set RF atten limit -- nValue is desired value */ 3405 /* Set RF atten limit -- nValue is desired value */
3406 case MT2063_ACRF_MAX: 3406 case MT2063_ACRF_MAX:
3407 val = 3407 val =
3408 (pInfo-> 3408 (state->
3409 reg[MT2063_REG_RF_OV] & (u8) ~ 0x1F) | (nValue 3409 reg[MT2063_REG_RF_OV] & (u8) ~ 0x1F) | (nValue
3410 & 3410 &
3411 0x1F); 3411 0x1F);
3412 if (pInfo->reg[MT2063_REG_RF_OV] != val) { 3412 if (state->reg[MT2063_REG_RF_OV] != val) {
3413 status |= 3413 status |=
3414 MT2063_SetReg(pInfo, MT2063_REG_RF_OV, val); 3414 MT2063_SetReg(state, MT2063_REG_RF_OV, val);
3415 } 3415 }
3416 break; 3416 break;
3417 3417
3418 /* Set FIF atten limit -- nValue is desired value, max. 5 if no B3 */ 3418 /* Set FIF atten limit -- nValue is desired value, max. 5 if no B3 */
3419 case MT2063_ACFIF_MAX: 3419 case MT2063_ACFIF_MAX:
3420 if (pInfo->reg[MT2063_REG_PART_REV] != MT2063_B3 3420 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3
3421 && nValue > 5) 3421 && nValue > 5)
3422 nValue = 5; 3422 nValue = 5;
3423 val = 3423 val =
3424 (pInfo-> 3424 (state->
3425 reg[MT2063_REG_FIF_OV] & (u8) ~ 0x1F) | (nValue 3425 reg[MT2063_REG_FIF_OV] & (u8) ~ 0x1F) | (nValue
3426 & 3426 &
3427 0x1F); 3427 0x1F);
3428 if (pInfo->reg[MT2063_REG_FIF_OV] != val) { 3428 if (state->reg[MT2063_REG_FIF_OV] != val) {
3429 status |= 3429 status |=
3430 MT2063_SetReg(pInfo, MT2063_REG_FIF_OV, 3430 MT2063_SetReg(state, MT2063_REG_FIF_OV,
3431 val); 3431 val);
3432 } 3432 }
3433 break; 3433 break;
@@ -3437,27 +3437,27 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3437 switch (nValue) { 3437 switch (nValue) {
3438 case MT2063_DNC_NONE: 3438 case MT2063_DNC_NONE:
3439 { 3439 {
3440 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ 3440 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
3441 if (pInfo->reg[MT2063_REG_DNC_GAIN] != 3441 if (state->reg[MT2063_REG_DNC_GAIN] !=
3442 val) 3442 val)
3443 status |= 3443 status |=
3444 MT2063_SetReg(pInfo, 3444 MT2063_SetReg(state,
3445 MT2063_REG_DNC_GAIN, 3445 MT2063_REG_DNC_GAIN,
3446 val); 3446 val);
3447 3447
3448 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ 3448 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
3449 if (pInfo->reg[MT2063_REG_VGA_GAIN] != 3449 if (state->reg[MT2063_REG_VGA_GAIN] !=
3450 val) 3450 val)
3451 status |= 3451 status |=
3452 MT2063_SetReg(pInfo, 3452 MT2063_SetReg(state,
3453 MT2063_REG_VGA_GAIN, 3453 MT2063_REG_VGA_GAIN,
3454 val); 3454 val);
3455 3455
3456 val = (pInfo->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ 3456 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
3457 if (pInfo->reg[MT2063_REG_RSVD_20] != 3457 if (state->reg[MT2063_REG_RSVD_20] !=
3458 val) 3458 val)
3459 status |= 3459 status |=
3460 MT2063_SetReg(pInfo, 3460 MT2063_SetReg(state,
3461 MT2063_REG_RSVD_20, 3461 MT2063_REG_RSVD_20,
3462 val); 3462 val);
3463 3463
@@ -3465,27 +3465,27 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3465 } 3465 }
3466 case MT2063_DNC_1: 3466 case MT2063_DNC_1:
3467 { 3467 {
3468 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[pInfo->rcvr_mode] & 0x03); /* Set DNC1GC=x */ 3468 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
3469 if (pInfo->reg[MT2063_REG_DNC_GAIN] != 3469 if (state->reg[MT2063_REG_DNC_GAIN] !=
3470 val) 3470 val)
3471 status |= 3471 status |=
3472 MT2063_SetReg(pInfo, 3472 MT2063_SetReg(state,
3473 MT2063_REG_DNC_GAIN, 3473 MT2063_REG_DNC_GAIN,
3474 val); 3474 val);
3475 3475
3476 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ 3476 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
3477 if (pInfo->reg[MT2063_REG_VGA_GAIN] != 3477 if (state->reg[MT2063_REG_VGA_GAIN] !=
3478 val) 3478 val)
3479 status |= 3479 status |=
3480 MT2063_SetReg(pInfo, 3480 MT2063_SetReg(state,
3481 MT2063_REG_VGA_GAIN, 3481 MT2063_REG_VGA_GAIN,
3482 val); 3482 val);
3483 3483
3484 val = (pInfo->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ 3484 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
3485 if (pInfo->reg[MT2063_REG_RSVD_20] != 3485 if (state->reg[MT2063_REG_RSVD_20] !=
3486 val) 3486 val)
3487 status |= 3487 status |=
3488 MT2063_SetReg(pInfo, 3488 MT2063_SetReg(state,
3489 MT2063_REG_RSVD_20, 3489 MT2063_REG_RSVD_20,
3490 val); 3490 val);
3491 3491
@@ -3493,27 +3493,27 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3493 } 3493 }
3494 case MT2063_DNC_2: 3494 case MT2063_DNC_2:
3495 { 3495 {
3496 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ 3496 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
3497 if (pInfo->reg[MT2063_REG_DNC_GAIN] != 3497 if (state->reg[MT2063_REG_DNC_GAIN] !=
3498 val) 3498 val)
3499 status |= 3499 status |=
3500 MT2063_SetReg(pInfo, 3500 MT2063_SetReg(state,
3501 MT2063_REG_DNC_GAIN, 3501 MT2063_REG_DNC_GAIN,
3502 val); 3502 val);
3503 3503
3504 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[pInfo->rcvr_mode] & 0x03); /* Set DNC2GC=x */ 3504 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
3505 if (pInfo->reg[MT2063_REG_VGA_GAIN] != 3505 if (state->reg[MT2063_REG_VGA_GAIN] !=
3506 val) 3506 val)
3507 status |= 3507 status |=
3508 MT2063_SetReg(pInfo, 3508 MT2063_SetReg(state,
3509 MT2063_REG_VGA_GAIN, 3509 MT2063_REG_VGA_GAIN,
3510 val); 3510 val);
3511 3511
3512 val = (pInfo->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ 3512 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
3513 if (pInfo->reg[MT2063_REG_RSVD_20] != 3513 if (state->reg[MT2063_REG_RSVD_20] !=
3514 val) 3514 val)
3515 status |= 3515 status |=
3516 MT2063_SetReg(pInfo, 3516 MT2063_SetReg(state,
3517 MT2063_REG_RSVD_20, 3517 MT2063_REG_RSVD_20,
3518 val); 3518 val);
3519 3519
@@ -3521,27 +3521,27 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3521 } 3521 }
3522 case MT2063_DNC_BOTH: 3522 case MT2063_DNC_BOTH:
3523 { 3523 {
3524 val = (pInfo->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[pInfo->rcvr_mode] & 0x03); /* Set DNC1GC=x */ 3524 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
3525 if (pInfo->reg[MT2063_REG_DNC_GAIN] != 3525 if (state->reg[MT2063_REG_DNC_GAIN] !=
3526 val) 3526 val)
3527 status |= 3527 status |=
3528 MT2063_SetReg(pInfo, 3528 MT2063_SetReg(state,
3529 MT2063_REG_DNC_GAIN, 3529 MT2063_REG_DNC_GAIN,
3530 val); 3530 val);
3531 3531
3532 val = (pInfo->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[pInfo->rcvr_mode] & 0x03); /* Set DNC2GC=x */ 3532 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
3533 if (pInfo->reg[MT2063_REG_VGA_GAIN] != 3533 if (state->reg[MT2063_REG_VGA_GAIN] !=
3534 val) 3534 val)
3535 status |= 3535 status |=
3536 MT2063_SetReg(pInfo, 3536 MT2063_SetReg(state,
3537 MT2063_REG_VGA_GAIN, 3537 MT2063_REG_VGA_GAIN,
3538 val); 3538 val);
3539 3539
3540 val = (pInfo->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ 3540 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
3541 if (pInfo->reg[MT2063_REG_RSVD_20] != 3541 if (state->reg[MT2063_REG_RSVD_20] !=
3542 val) 3542 val)
3543 status |= 3543 status |=
3544 MT2063_SetReg(pInfo, 3544 MT2063_SetReg(state,
3545 MT2063_REG_RSVD_20, 3545 MT2063_REG_RSVD_20,
3546 val); 3546 val);
3547 3547
@@ -3555,12 +3555,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3555 case MT2063_VGAGC: 3555 case MT2063_VGAGC:
3556 /* Set VGA gain code */ 3556 /* Set VGA gain code */
3557 val = 3557 val =
3558 (pInfo-> 3558 (state->
3559 reg[MT2063_REG_VGA_GAIN] & (u8) ~ 0x0C) | 3559 reg[MT2063_REG_VGA_GAIN] & (u8) ~ 0x0C) |
3560 ((nValue & 0x03) << 2); 3560 ((nValue & 0x03) << 2);
3561 if (pInfo->reg[MT2063_REG_VGA_GAIN] != val) { 3561 if (state->reg[MT2063_REG_VGA_GAIN] != val) {
3562 status |= 3562 status |=
3563 MT2063_SetReg(pInfo, MT2063_REG_VGA_GAIN, 3563 MT2063_SetReg(state, MT2063_REG_VGA_GAIN,
3564 val); 3564 val);
3565 } 3565 }
3566 break; 3566 break;
@@ -3568,12 +3568,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3568 case MT2063_VGAOI: 3568 case MT2063_VGAOI:
3569 /* Set VGA bias current */ 3569 /* Set VGA bias current */
3570 val = 3570 val =
3571 (pInfo-> 3571 (state->
3572 reg[MT2063_REG_RSVD_31] & (u8) ~ 0x07) | 3572 reg[MT2063_REG_RSVD_31] & (u8) ~ 0x07) |
3573 (nValue & 0x07); 3573 (nValue & 0x07);
3574 if (pInfo->reg[MT2063_REG_RSVD_31] != val) { 3574 if (state->reg[MT2063_REG_RSVD_31] != val) {
3575 status |= 3575 status |=
3576 MT2063_SetReg(pInfo, MT2063_REG_RSVD_31, 3576 MT2063_SetReg(state, MT2063_REG_RSVD_31,
3577 val); 3577 val);
3578 } 3578 }
3579 break; 3579 break;
@@ -3581,12 +3581,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3581 case MT2063_TAGC: 3581 case MT2063_TAGC:
3582 /* Set TAGC */ 3582 /* Set TAGC */
3583 val = 3583 val =
3584 (pInfo-> 3584 (state->
3585 reg[MT2063_REG_RSVD_1E] & (u8) ~ 0x03) | 3585 reg[MT2063_REG_RSVD_1E] & (u8) ~ 0x03) |
3586 (nValue & 0x03); 3586 (nValue & 0x03);
3587 if (pInfo->reg[MT2063_REG_RSVD_1E] != val) { 3587 if (state->reg[MT2063_REG_RSVD_1E] != val) {
3588 status |= 3588 status |=
3589 MT2063_SetReg(pInfo, MT2063_REG_RSVD_1E, 3589 MT2063_SetReg(state, MT2063_REG_RSVD_1E,
3590 val); 3590 val);
3591 } 3591 }
3592 break; 3592 break;
@@ -3594,12 +3594,12 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3594 case MT2063_AMPGC: 3594 case MT2063_AMPGC:
3595 /* Set Amp gain code */ 3595 /* Set Amp gain code */
3596 val = 3596 val =
3597 (pInfo-> 3597 (state->
3598 reg[MT2063_REG_TEMP_SEL] & (u8) ~ 0x03) | 3598 reg[MT2063_REG_TEMP_SEL] & (u8) ~ 0x03) |
3599 (nValue & 0x03); 3599 (nValue & 0x03);
3600 if (pInfo->reg[MT2063_REG_TEMP_SEL] != val) { 3600 if (state->reg[MT2063_REG_TEMP_SEL] != val) {
3601 status |= 3601 status |=
3602 MT2063_SetReg(pInfo, MT2063_REG_TEMP_SEL, 3602 MT2063_SetReg(state, MT2063_REG_TEMP_SEL,
3603 val); 3603 val);
3604 } 3604 }
3605 break; 3605 break;
@@ -3612,7 +3612,7 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3612 if ((newAvoidSetting >= 3612 if ((newAvoidSetting >=
3613 MT2063_NO_DECT_AVOIDANCE) 3613 MT2063_NO_DECT_AVOIDANCE)
3614 && (newAvoidSetting <= MT2063_AVOID_BOTH)) { 3614 && (newAvoidSetting <= MT2063_AVOID_BOTH)) {
3615 pInfo->AS_Data.avoidDECT = 3615 state->AS_Data.avoidDECT =
3616 newAvoidSetting; 3616 newAvoidSetting;
3617 } 3617 }
3618 } 3618 }
@@ -3620,7 +3620,7 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3620 3620
3621 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */ 3621 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
3622 case MT2063_CTFILT_SW: 3622 case MT2063_CTFILT_SW:
3623 pInfo->ctfilt_sw = (nValue & 0x01); 3623 state->ctfilt_sw = (nValue & 0x01);
3624 break; 3624 break;
3625 3625
3626 /* These parameters are read-only */ 3626 /* These parameters are read-only */
@@ -3673,24 +3673,24 @@ static u32 MT2063_SetParam(struct mt2063_state *pInfo,
3673** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 3673** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
3674** 3674**
3675****************************************************************************/ 3675****************************************************************************/
3676static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *pInfo, enum MT2063_Mask_Bits Bits) 3676static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state, enum MT2063_Mask_Bits Bits)
3677{ 3677{
3678 u32 status = 0; /* Status to be returned */ 3678 u32 status = 0; /* Status to be returned */
3679 3679
3680 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */ 3680 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */
3681 if ((Bits & 0xFF00) != 0) { 3681 if ((Bits & 0xFF00) != 0) {
3682 pInfo->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); 3682 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
3683 status |= 3683 status |=
3684 MT2063_WriteSub(pInfo, 3684 MT2063_WriteSub(state,
3685 MT2063_REG_PWR_2, 3685 MT2063_REG_PWR_2,
3686 &pInfo->reg[MT2063_REG_PWR_2], 1); 3686 &state->reg[MT2063_REG_PWR_2], 1);
3687 } 3687 }
3688 if ((Bits & 0xFF) != 0) { 3688 if ((Bits & 0xFF) != 0) {
3689 pInfo->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); 3689 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
3690 status |= 3690 status |=
3691 MT2063_WriteSub(pInfo, 3691 MT2063_WriteSub(state,
3692 MT2063_REG_PWR_1, 3692 MT2063_REG_PWR_1,
3693 &pInfo->reg[MT2063_REG_PWR_1], 1); 3693 &state->reg[MT2063_REG_PWR_1], 1);
3694 } 3694 }
3695 3695
3696 return (status); 3696 return (status);
@@ -3724,34 +3724,34 @@ static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *pInfo, enum MT2063_Mas
3724** correct wakeup of the LNA 3724** correct wakeup of the LNA
3725** 3725**
3726****************************************************************************/ 3726****************************************************************************/
3727static u32 MT2063_SoftwareShutdown(struct mt2063_state *pInfo, u8 Shutdown) 3727static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
3728{ 3728{
3729 u32 status = 0; /* Status to be returned */ 3729 u32 status = 0; /* Status to be returned */
3730 3730
3731 if (Shutdown == 1) 3731 if (Shutdown == 1)
3732 pInfo->reg[MT2063_REG_PWR_1] |= 0x04; /* Turn the bit on */ 3732 state->reg[MT2063_REG_PWR_1] |= 0x04; /* Turn the bit on */
3733 else 3733 else
3734 pInfo->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */ 3734 state->reg[MT2063_REG_PWR_1] &= ~0x04; /* Turn off the bit */
3735 3735
3736 status |= 3736 status |=
3737 MT2063_WriteSub(pInfo, 3737 MT2063_WriteSub(state,
3738 MT2063_REG_PWR_1, 3738 MT2063_REG_PWR_1,
3739 &pInfo->reg[MT2063_REG_PWR_1], 1); 3739 &state->reg[MT2063_REG_PWR_1], 1);
3740 3740
3741 if (Shutdown != 1) { 3741 if (Shutdown != 1) {
3742 pInfo->reg[MT2063_REG_BYP_CTRL] = 3742 state->reg[MT2063_REG_BYP_CTRL] =
3743 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; 3743 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
3744 status |= 3744 status |=
3745 MT2063_WriteSub(pInfo, 3745 MT2063_WriteSub(state,
3746 MT2063_REG_BYP_CTRL, 3746 MT2063_REG_BYP_CTRL,
3747 &pInfo->reg[MT2063_REG_BYP_CTRL], 3747 &state->reg[MT2063_REG_BYP_CTRL],
3748 1); 3748 1);
3749 pInfo->reg[MT2063_REG_BYP_CTRL] = 3749 state->reg[MT2063_REG_BYP_CTRL] =
3750 (pInfo->reg[MT2063_REG_BYP_CTRL] & 0x9F); 3750 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F);
3751 status |= 3751 status |=
3752 MT2063_WriteSub(pInfo, 3752 MT2063_WriteSub(state,
3753 MT2063_REG_BYP_CTRL, 3753 MT2063_REG_BYP_CTRL,
3754 &pInfo->reg[MT2063_REG_BYP_CTRL], 3754 &state->reg[MT2063_REG_BYP_CTRL],
3755 1); 3755 1);
3756 } 3756 }
3757 3757
@@ -3786,17 +3786,17 @@ static u32 MT2063_SoftwareShutdown(struct mt2063_state *pInfo, u8 Shutdown)
3786** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b. 3786** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
3787** 3787**
3788****************************************************************************/ 3788****************************************************************************/
3789static u32 MT2063_SetReg(struct mt2063_state *pInfo, u8 reg, u8 val) 3789static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val)
3790{ 3790{
3791 u32 status = 0; /* Status to be returned */ 3791 u32 status = 0; /* Status to be returned */
3792 3792
3793 if (reg >= MT2063_REG_END_REGS) 3793 if (reg >= MT2063_REG_END_REGS)
3794 status |= -ERANGE; 3794 status |= -ERANGE;
3795 3795
3796 status = MT2063_WriteSub(pInfo, reg, &val, 3796 status = MT2063_WriteSub(state, reg, &val,
3797 1); 3797 1);
3798 if (status >= 0) 3798 if (status >= 0)
3799 pInfo->reg[reg] = val; 3799 state->reg[reg] = val;
3800 3800
3801 return (status); 3801 return (status);
3802} 3802}
@@ -3942,7 +3942,7 @@ static u32 MT2063_CalcLO2Mult(u32 * Div,
3942** Description: Calculate the corrrect ClearTune filter to be used for 3942** Description: Calculate the corrrect ClearTune filter to be used for
3943** a given input frequency. 3943** a given input frequency.
3944** 3944**
3945** Parameters: pInfo - ptr to tuner data structure 3945** Parameters: state - ptr to tuner data structure
3946** f_in - RF input center frequency (in Hz). 3946** f_in - RF input center frequency (in Hz).
3947** 3947**
3948** Returns: ClearTune filter number (0-31) 3948** Returns: ClearTune filter number (0-31)
@@ -3957,7 +3957,7 @@ static u32 MT2063_CalcLO2Mult(u32 * Div,
3957** cross-over frequency values. 3957** cross-over frequency values.
3958** 3958**
3959****************************************************************************/ 3959****************************************************************************/
3960static u32 FindClearTuneFilter(struct mt2063_state *pInfo, u32 f_in) 3960static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in)
3961{ 3961{
3962 u32 RFBand; 3962 u32 RFBand;
3963 u32 idx; /* index loop */ 3963 u32 idx; /* index loop */
@@ -3967,7 +3967,7 @@ static u32 FindClearTuneFilter(struct mt2063_state *pInfo, u32 f_in)
3967 */ 3967 */
3968 RFBand = 31; /* def when f_in > all */ 3968 RFBand = 31; /* def when f_in > all */
3969 for (idx = 0; idx < 31; ++idx) { 3969 for (idx = 0; idx < 31; ++idx) {
3970 if (pInfo->CTFiltMax[idx] >= f_in) { 3970 if (state->CTFiltMax[idx] >= f_in) {
3971 RFBand = idx; 3971 RFBand = idx;
3972 break; 3972 break;
3973 } 3973 }
@@ -4016,7 +4016,7 @@ static u32 FindClearTuneFilter(struct mt2063_state *pInfo, u32 f_in)
4016** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW 4016** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
4017** 4017**
4018****************************************************************************/ 4018****************************************************************************/
4019static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in) 4019static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
4020{ /* RF input center frequency */ 4020{ /* RF input center frequency */
4021 4021
4022 u32 status = 0; /* status of operation */ 4022 u32 status = 0; /* status of operation */
@@ -4038,35 +4038,35 @@ static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in)
4038 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ)) 4038 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ))
4039 return -EINVAL; 4039 return -EINVAL;
4040 4040
4041 if ((pInfo->AS_Data.f_out < MT2063_MIN_FOUT_FREQ) 4041 if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ)
4042 || (pInfo->AS_Data.f_out > MT2063_MAX_FOUT_FREQ)) 4042 || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ))
4043 return -EINVAL; 4043 return -EINVAL;
4044 4044
4045 /* 4045 /*
4046 ** Save original LO1 and LO2 register values 4046 ** Save original LO1 and LO2 register values
4047 */ 4047 */
4048 ofLO1 = pInfo->AS_Data.f_LO1; 4048 ofLO1 = state->AS_Data.f_LO1;
4049 ofLO2 = pInfo->AS_Data.f_LO2; 4049 ofLO2 = state->AS_Data.f_LO2;
4050 ofin = pInfo->AS_Data.f_in; 4050 ofin = state->AS_Data.f_in;
4051 ofout = pInfo->AS_Data.f_out; 4051 ofout = state->AS_Data.f_out;
4052 4052
4053 /* 4053 /*
4054 ** Find and set RF Band setting 4054 ** Find and set RF Band setting
4055 */ 4055 */
4056 if (pInfo->ctfilt_sw == 1) { 4056 if (state->ctfilt_sw == 1) {
4057 val = (pInfo->reg[MT2063_REG_CTUNE_CTRL] | 0x08); 4057 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
4058 if (pInfo->reg[MT2063_REG_CTUNE_CTRL] != val) { 4058 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
4059 status |= 4059 status |=
4060 MT2063_SetReg(pInfo, MT2063_REG_CTUNE_CTRL, val); 4060 MT2063_SetReg(state, MT2063_REG_CTUNE_CTRL, val);
4061 } 4061 }
4062 val = pInfo->reg[MT2063_REG_CTUNE_OV]; 4062 val = state->reg[MT2063_REG_CTUNE_OV];
4063 RFBand = FindClearTuneFilter(pInfo, f_in); 4063 RFBand = FindClearTuneFilter(state, f_in);
4064 pInfo->reg[MT2063_REG_CTUNE_OV] = 4064 state->reg[MT2063_REG_CTUNE_OV] =
4065 (u8) ((pInfo->reg[MT2063_REG_CTUNE_OV] & ~0x1F) 4065 (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F)
4066 | RFBand); 4066 | RFBand);
4067 if (pInfo->reg[MT2063_REG_CTUNE_OV] != val) { 4067 if (state->reg[MT2063_REG_CTUNE_OV] != val) {
4068 status |= 4068 status |=
4069 MT2063_SetReg(pInfo, MT2063_REG_CTUNE_OV, val); 4069 MT2063_SetReg(state, MT2063_REG_CTUNE_OV, val);
4070 } 4070 }
4071 } 4071 }
4072 4072
@@ -4075,77 +4075,77 @@ static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in)
4075 */ 4075 */
4076 if (status >= 0) { 4076 if (status >= 0) {
4077 status |= 4077 status |=
4078 MT2063_ReadSub(pInfo, 4078 MT2063_ReadSub(state,
4079 MT2063_REG_FIFFC, 4079 MT2063_REG_FIFFC,
4080 &pInfo->reg[MT2063_REG_FIFFC], 1); 4080 &state->reg[MT2063_REG_FIFFC], 1);
4081 fiffc = pInfo->reg[MT2063_REG_FIFFC]; 4081 fiffc = state->reg[MT2063_REG_FIFFC];
4082 } 4082 }
4083 /* 4083 /*
4084 ** Assign in the requested values 4084 ** Assign in the requested values
4085 */ 4085 */
4086 pInfo->AS_Data.f_in = f_in; 4086 state->AS_Data.f_in = f_in;
4087 /* Request a 1st IF such that LO1 is on a step size */ 4087 /* Request a 1st IF such that LO1 is on a step size */
4088 pInfo->AS_Data.f_if1_Request = 4088 state->AS_Data.f_if1_Request =
4089 MT2063_Round_fLO(pInfo->AS_Data.f_if1_Request + f_in, 4089 MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in,
4090 pInfo->AS_Data.f_LO1_Step, 4090 state->AS_Data.f_LO1_Step,
4091 pInfo->AS_Data.f_ref) - f_in; 4091 state->AS_Data.f_ref) - f_in;
4092 4092
4093 /* 4093 /*
4094 ** Calculate frequency settings. f_IF1_FREQ + f_in is the 4094 ** Calculate frequency settings. f_IF1_FREQ + f_in is the
4095 ** desired LO1 frequency 4095 ** desired LO1 frequency
4096 */ 4096 */
4097 MT2063_ResetExclZones(&pInfo->AS_Data); 4097 MT2063_ResetExclZones(&state->AS_Data);
4098 4098
4099 f_IF1 = MT2063_ChooseFirstIF(&pInfo->AS_Data); 4099 f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data);
4100 4100
4101 pInfo->AS_Data.f_LO1 = 4101 state->AS_Data.f_LO1 =
4102 MT2063_Round_fLO(f_IF1 + f_in, pInfo->AS_Data.f_LO1_Step, 4102 MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step,
4103 pInfo->AS_Data.f_ref); 4103 state->AS_Data.f_ref);
4104 4104
4105 pInfo->AS_Data.f_LO2 = 4105 state->AS_Data.f_LO2 =
4106 MT2063_Round_fLO(pInfo->AS_Data.f_LO1 - pInfo->AS_Data.f_out - f_in, 4106 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
4107 pInfo->AS_Data.f_LO2_Step, pInfo->AS_Data.f_ref); 4107 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
4108 4108
4109 /* 4109 /*
4110 ** Check for any LO spurs in the output bandwidth and adjust 4110 ** Check for any LO spurs in the output bandwidth and adjust
4111 ** the LO settings to avoid them if needed 4111 ** the LO settings to avoid them if needed
4112 */ 4112 */
4113 status |= MT2063_AvoidSpurs(pInfo, &pInfo->AS_Data); 4113 status |= MT2063_AvoidSpurs(state, &state->AS_Data);
4114 /* 4114 /*
4115 ** MT_AvoidSpurs spurs may have changed the LO1 & LO2 values. 4115 ** MT_AvoidSpurs spurs may have changed the LO1 & LO2 values.
4116 ** Recalculate the LO frequencies and the values to be placed 4116 ** Recalculate the LO frequencies and the values to be placed
4117 ** in the tuning registers. 4117 ** in the tuning registers.
4118 */ 4118 */
4119 pInfo->AS_Data.f_LO1 = 4119 state->AS_Data.f_LO1 =
4120 MT2063_CalcLO1Mult(&LO1, &Num1, pInfo->AS_Data.f_LO1, 4120 MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1,
4121 pInfo->AS_Data.f_LO1_Step, pInfo->AS_Data.f_ref); 4121 state->AS_Data.f_LO1_Step, state->AS_Data.f_ref);
4122 pInfo->AS_Data.f_LO2 = 4122 state->AS_Data.f_LO2 =
4123 MT2063_Round_fLO(pInfo->AS_Data.f_LO1 - pInfo->AS_Data.f_out - f_in, 4123 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
4124 pInfo->AS_Data.f_LO2_Step, pInfo->AS_Data.f_ref); 4124 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
4125 pInfo->AS_Data.f_LO2 = 4125 state->AS_Data.f_LO2 =
4126 MT2063_CalcLO2Mult(&LO2, &Num2, pInfo->AS_Data.f_LO2, 4126 MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2,
4127 pInfo->AS_Data.f_LO2_Step, pInfo->AS_Data.f_ref); 4127 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
4128 4128
4129 /* 4129 /*
4130 ** Check the upconverter and downconverter frequency ranges 4130 ** Check the upconverter and downconverter frequency ranges
4131 */ 4131 */
4132 if ((pInfo->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ) 4132 if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ)
4133 || (pInfo->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ)) 4133 || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ))
4134 status |= MT2063_UPC_RANGE; 4134 status |= MT2063_UPC_RANGE;
4135 if ((pInfo->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ) 4135 if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ)
4136 || (pInfo->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ)) 4136 || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ))
4137 status |= MT2063_DNC_RANGE; 4137 status |= MT2063_DNC_RANGE;
4138 /* LO2 Lock bit was in a different place for B0 version */ 4138 /* LO2 Lock bit was in a different place for B0 version */
4139 if (pInfo->tuner_id == MT2063_B0) 4139 if (state->tuner_id == MT2063_B0)
4140 LO2LK = 0x40; 4140 LO2LK = 0x40;
4141 4141
4142 /* 4142 /*
4143 ** If we have the same LO frequencies and we're already locked, 4143 ** If we have the same LO frequencies and we're already locked,
4144 ** then skip re-programming the LO registers. 4144 ** then skip re-programming the LO registers.
4145 */ 4145 */
4146 if ((ofLO1 != pInfo->AS_Data.f_LO1) 4146 if ((ofLO1 != state->AS_Data.f_LO1)
4147 || (ofLO2 != pInfo->AS_Data.f_LO2) 4147 || (ofLO2 != state->AS_Data.f_LO2)
4148 || ((pInfo->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) != 4148 || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) !=
4149 (LO1LK | LO2LK))) { 4149 (LO1LK | LO2LK))) {
4150 /* 4150 /*
4151 ** Calculate the FIFFOF register value 4151 ** Calculate the FIFFOF register value
@@ -4155,8 +4155,8 @@ static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in)
4155 ** f_ref/64 4155 ** f_ref/64
4156 */ 4156 */
4157 fiffof = 4157 fiffof =
4158 (pInfo->AS_Data.f_LO1 - 4158 (state->AS_Data.f_LO1 -
4159 f_in) / (pInfo->AS_Data.f_ref / 64) - 8 * (u32) fiffc - 4159 f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc -
4160 4992; 4160 4992;
4161 if (fiffof > 0xFF) 4161 if (fiffof > 0xFF)
4162 fiffof = 0xFF; 4162 fiffof = 0xFF;
@@ -4166,32 +4166,32 @@ static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in)
4166 ** register fields. 4166 ** register fields.
4167 */ 4167 */
4168 if (status >= 0) { 4168 if (status >= 0) {
4169 pInfo->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */ 4169 state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */
4170 pInfo->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */ 4170 state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */
4171 pInfo->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */ 4171 state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */
4172 |(Num2 >> 12)); /* NUM2q (hi) */ 4172 |(Num2 >> 12)); /* NUM2q (hi) */
4173 pInfo->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */ 4173 state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */
4174 pInfo->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */ 4174 state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */
4175 4175
4176 /* 4176 /*
4177 ** Now write out the computed register values 4177 ** Now write out the computed register values
4178 ** IMPORTANT: There is a required order for writing 4178 ** IMPORTANT: There is a required order for writing
4179 ** (0x05 must follow all the others). 4179 ** (0x05 must follow all the others).
4180 */ 4180 */
4181 status |= MT2063_WriteSub(pInfo, MT2063_REG_LO1CQ_1, &pInfo->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */ 4181 status |= MT2063_WriteSub(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
4182 if (pInfo->tuner_id == MT2063_B0) { 4182 if (state->tuner_id == MT2063_B0) {
4183 /* Re-write the one-shot bits to trigger the tune operation */ 4183 /* Re-write the one-shot bits to trigger the tune operation */
4184 status |= MT2063_WriteSub(pInfo, MT2063_REG_LO2CQ_3, &pInfo->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ 4184 status |= MT2063_WriteSub(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
4185 } 4185 }
4186 /* Write out the FIFF offset only if it's changing */ 4186 /* Write out the FIFF offset only if it's changing */
4187 if (pInfo->reg[MT2063_REG_FIFF_OFFSET] != 4187 if (state->reg[MT2063_REG_FIFF_OFFSET] !=
4188 (u8) fiffof) { 4188 (u8) fiffof) {
4189 pInfo->reg[MT2063_REG_FIFF_OFFSET] = 4189 state->reg[MT2063_REG_FIFF_OFFSET] =
4190 (u8) fiffof; 4190 (u8) fiffof;
4191 status |= 4191 status |=
4192 MT2063_WriteSub(pInfo, 4192 MT2063_WriteSub(state,
4193 MT2063_REG_FIFF_OFFSET, 4193 MT2063_REG_FIFF_OFFSET,
4194 &pInfo-> 4194 &state->
4195 reg[MT2063_REG_FIFF_OFFSET], 4195 reg[MT2063_REG_FIFF_OFFSET],
4196 1); 4196 1);
4197 } 4197 }
@@ -4202,13 +4202,13 @@ static u32 MT2063_Tune(struct mt2063_state *pInfo, u32 f_in)
4202 */ 4202 */
4203 4203
4204 if (status >= 0) { 4204 if (status >= 0) {
4205 status |= MT2063_GetLocked(pInfo); 4205 status |= MT2063_GetLocked(state);
4206 } 4206 }
4207 /* 4207 /*
4208 ** If we locked OK, assign calculated data to mt2063_state structure 4208 ** If we locked OK, assign calculated data to mt2063_state structure
4209 */ 4209 */
4210 if (status >= 0) { 4210 if (status >= 0) {
4211 pInfo->f_IF1_actual = pInfo->AS_Data.f_LO1 - f_in; 4211 state->f_IF1_actual = state->AS_Data.f_LO1 - f_in;
4212 } 4212 }
4213 } 4213 }
4214 4214
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 05:21:12 -0500