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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-21 02:20:43 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:19:53 -0500
commit01e0dafc6460096c0ef5a548fbc99b64a8b58ba4 (patch)
tree84d747294691b2bbc408f8f12cabcef53fb648e4 /drivers/media/common/tuners/mt2063.c
parente930b3a03e28b3ac8d936eee431e58052e6cf26c (diff)
[media] mt2063: Simplify device init logic
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/common/tuners/mt2063.c')
-rw-r--r--drivers/media/common/tuners/mt2063.c575
1 files changed, 242 insertions, 333 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index 10116356f304..c5e95ddd11f9 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -11,7 +11,6 @@ module_param(verbose, int, 0644);
11/* Internal structures and types */ 11/* Internal structures and types */
12 12
13/* FIXME: we probably don't need these new FE get/set property types for tuner */ 13/* FIXME: we probably don't need these new FE get/set property types for tuner */
14#define DVBFE_TUNER_OPEN 99
15#define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100 14#define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100
16#define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101 15#define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101
17 16
@@ -387,7 +386,6 @@ struct mt2063_state {
387 struct dvb_tuner_ops ops; 386 struct dvb_tuner_ops ops;
388 struct dvb_frontend *frontend; 387 struct dvb_frontend *frontend;
389 struct tuner_state status; 388 struct tuner_state status;
390 bool MT2063_init;
391 389
392 enum MTTune_atv_standard tv_type; 390 enum MTTune_atv_standard tv_type;
393 u32 frequency; 391 u32 frequency;
@@ -408,7 +406,6 @@ struct mt2063_state {
408/* Prototypes */ 406/* Prototypes */
409static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info, 407static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
410 u32 f_min, u32 f_max); 408 u32 f_min, u32 f_max);
411static u32 MT2063_ReInit(struct mt2063_state *state);
412static u32 MT2063_GetReg(struct mt2063_state *state, u8 reg, u8 * val); 409static u32 MT2063_GetReg(struct mt2063_state *state, u8 reg, u8 * val);
413static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param, u32 * pValue); 410static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param, u32 * pValue);
414static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val); 411static u32 MT2063_SetReg(struct mt2063_state *state, u8 reg, u8 val);
@@ -1347,51 +1344,6 @@ static u32 MT2063_CalcLO2Mult(u32 * Div, u32 * FracN, u32 f_LO,
1347static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num, 1344static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num,
1348 u32 denom); 1345 u32 denom);
1349 1346
1350/******************************************************************************
1351**
1352** Name: MT2063_Open
1353**
1354** Description: Initialize the tuner's register values.
1355**
1356** Parameters: MT2063_Addr - Serial bus address of the tuner.
1357** hMT2063 - Tuner handle passed back.
1358** hUserData - User-defined data, if needed for the
1359** MT_ReadSub() & MT_WriteSub functions.
1360**
1361** Returns: status:
1362** MT_OK - No errors
1363** MT_TUNER_ID_ERR - Tuner Part/Rev code mismatch
1364** MT_TUNER_INIT_ERR - Tuner initialization failed
1365** MT_COMM_ERR - Serial bus communications error
1366** MT_ARG_NULL - Null pointer argument passed
1367** MT_TUNER_CNT_ERR - Too many tuners open
1368**
1369** Dependencies: MT_ReadSub - Read byte(s) of data from the two-wire bus
1370** MT_WriteSub - Write byte(s) of data to the two-wire bus
1371**
1372** Revision History:
1373**
1374** SCR Date Author Description
1375** -------------------------------------------------------------------------
1376** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
1377**
1378******************************************************************************/
1379static u32 MT2063_Open(struct dvb_frontend *fe)
1380{
1381 u32 status; /* Status to be returned. */
1382 struct mt2063_state *state = fe->tuner_priv;
1383
1384 state->rcvr_mode = MT2063_CABLE_QAM;
1385 if (state->MT2063_init != false) {
1386 status = MT2063_ReInit(state);
1387 if (status < 0)
1388 return status;
1389 }
1390
1391 state->MT2063_init = true;
1392 return 0;
1393}
1394
1395/**************************************************************************** 1347/****************************************************************************
1396** 1348**
1397** Name: MT2063_GetLocked 1349** Name: MT2063_GetLocked
@@ -2146,279 +2098,6 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
2146 return (status); 2098 return (status);
2147} 2099}
2148 2100
2149/******************************************************************************
2150**
2151** Name: MT2063_ReInit
2152**
2153** Description: Initialize the tuner's register values.
2154**
2155** Parameters: h - Tuner handle (returned by MT2063_Open)
2156**
2157** Returns: status:
2158** MT_OK - No errors
2159** MT_TUNER_ID_ERR - Tuner Part/Rev code mismatch
2160** MT_INV_HANDLE - Invalid tuner handle
2161** MT_COMM_ERR - Serial bus communications error
2162**
2163** Dependencies: MT_ReadSub - Read byte(s) of data from the two-wire bus
2164** MT_WriteSub - Write byte(s) of data to the two-wire bus
2165**
2166** Revision History:
2167**
2168** SCR Date Author Description
2169** -------------------------------------------------------------------------
2170** 138 06-19-2007 DAD Ver 1.00: Initial, derived from mt2067_b.
2171** 148 09-04-2007 RSK Ver 1.02: Corrected logic of Reg 3B Reference
2172** 153 09-07-2007 RSK Ver 1.03: Lock Time improvements
2173** N/A 10-31-2007 PINZ Ver 1.08: Changed values suitable to rcvr-mode 0
2174** N/A 11-12-2007 PINZ Ver 1.09: Changed values suitable to rcvr-mode 0
2175** N/A 01-03-2007 PINZ Ver 1.10: Added AFCsd = 1 into defaults
2176** N/A 01-04-2007 PINZ Ver 1.10: Changed CAP1sel default
2177** 01-14-2008 PINZ Ver 1.11: Updated gain settings
2178** 03-18-2008 PINZ Ver 1.13: Added Support for B3
2179** 175 I 06-19-2008 RSK Ver 1.17: Refactor DECT control to SpurAvoid.
2180** 06-24-2008 PINZ Ver 1.18: Add Get/SetParam CTFILT_SW
2181**
2182******************************************************************************/
2183static u32 MT2063_ReInit(struct mt2063_state *state)
2184{
2185 u8 all_resets = 0xF0; /* reset/load bits */
2186 u32 status = 0; /* Status to be returned */
2187 u8 *def = NULL;
2188 u32 FCRUN;
2189 s32 maxReads;
2190 u32 fcu_osc;
2191 u32 i;
2192 u8 MT2063B0_defaults[] = { /* Reg, Value */
2193 0x19, 0x05,
2194 0x1B, 0x1D,
2195 0x1C, 0x1F,
2196 0x1D, 0x0F,
2197 0x1E, 0x3F,
2198 0x1F, 0x0F,
2199 0x20, 0x3F,
2200 0x22, 0x21,
2201 0x23, 0x3F,
2202 0x24, 0x20,
2203 0x25, 0x3F,
2204 0x27, 0xEE,
2205 0x2C, 0x27, /* bit at 0x20 is cleared below */
2206 0x30, 0x03,
2207 0x2C, 0x07, /* bit at 0x20 is cleared here */
2208 0x2D, 0x87,
2209 0x2E, 0xAA,
2210 0x28, 0xE1, /* Set the FIFCrst bit here */
2211 0x28, 0xE0, /* Clear the FIFCrst bit here */
2212 0x00
2213 };
2214 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
2215 u8 MT2063B1_defaults[] = { /* Reg, Value */
2216 0x05, 0xF0,
2217 0x11, 0x10, /* New Enable AFCsd */
2218 0x19, 0x05,
2219 0x1A, 0x6C,
2220 0x1B, 0x24,
2221 0x1C, 0x28,
2222 0x1D, 0x8F,
2223 0x1E, 0x14,
2224 0x1F, 0x8F,
2225 0x20, 0x57,
2226 0x22, 0x21, /* New - ver 1.03 */
2227 0x23, 0x3C, /* New - ver 1.10 */
2228 0x24, 0x20, /* New - ver 1.03 */
2229 0x2C, 0x24, /* bit at 0x20 is cleared below */
2230 0x2D, 0x87, /* FIFFQ=0 */
2231 0x2F, 0xF3,
2232 0x30, 0x0C, /* New - ver 1.11 */
2233 0x31, 0x1B, /* New - ver 1.11 */
2234 0x2C, 0x04, /* bit at 0x20 is cleared here */
2235 0x28, 0xE1, /* Set the FIFCrst bit here */
2236 0x28, 0xE0, /* Clear the FIFCrst bit here */
2237 0x00
2238 };
2239 /* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
2240 u8 MT2063B3_defaults[] = { /* Reg, Value */
2241 0x05, 0xF0,
2242 0x19, 0x3D,
2243 0x2C, 0x24, /* bit at 0x20 is cleared below */
2244 0x2C, 0x04, /* bit at 0x20 is cleared here */
2245 0x28, 0xE1, /* Set the FIFCrst bit here */
2246 0x28, 0xE0, /* Clear the FIFCrst bit here */
2247 0x00
2248 };
2249
2250 /* Read the Part/Rev code from the tuner */
2251 status = mt2063_read(state, MT2063_REG_PART_REV, state->reg, 1);
2252 if (status < 0)
2253 return status;
2254
2255 /* Check the part/rev code */
2256 if (((state->reg[MT2063_REG_PART_REV] != MT2063_B0) /* MT2063 B0 */
2257 &&(state->reg[MT2063_REG_PART_REV] != MT2063_B1) /* MT2063 B1 */
2258 &&(state->reg[MT2063_REG_PART_REV] != MT2063_B3))) /* MT2063 B3 */
2259 return -ENODEV; /* Wrong tuner Part/Rev code */
2260
2261 /* Check the 2nd byte of the Part/Rev code from the tuner */
2262 status = mt2063_read(state,
2263 MT2063_REG_RSVD_3B,
2264 &state->reg[MT2063_REG_RSVD_3B], 1);
2265
2266 if (status >= 0
2267 &&((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) /* b7 != 0 ==> NOT MT2063 */
2268 return -ENODEV; /* Wrong tuner Part/Rev code */
2269
2270 /* Reset the tuner */
2271 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
2272 if (status < 0)
2273 return status;
2274
2275 /* change all of the default values that vary from the HW reset values */
2276 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
2277 switch (state->reg[MT2063_REG_PART_REV]) {
2278 case MT2063_B3:
2279 def = MT2063B3_defaults;
2280 break;
2281
2282 case MT2063_B1:
2283 def = MT2063B1_defaults;
2284 break;
2285
2286 case MT2063_B0:
2287 def = MT2063B0_defaults;
2288 break;
2289
2290 default:
2291 return -ENODEV;
2292 break;
2293 }
2294
2295 while (status >= 0 && *def) {
2296 u8 reg = *def++;
2297 u8 val = *def++;
2298 status = mt2063_write(state, reg, &val, 1);
2299 }
2300 if (status < 0)
2301 return status;
2302
2303 /* Wait for FIFF location to complete. */
2304 FCRUN = 1;
2305 maxReads = 10;
2306 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
2307 msleep(2);
2308 status = mt2063_read(state,
2309 MT2063_REG_XO_STATUS,
2310 &state->
2311 reg[MT2063_REG_XO_STATUS], 1);
2312 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
2313 }
2314
2315 if (FCRUN != 0)
2316 return -ENODEV;
2317
2318 status = mt2063_read(state,
2319 MT2063_REG_FIFFC,
2320 &state->reg[MT2063_REG_FIFFC], 1);
2321 if (status < 0)
2322 return status;
2323
2324 /* Read back all the registers from the tuner */
2325 status = mt2063_read(state,
2326 MT2063_REG_PART_REV,
2327 state->reg, MT2063_REG_END_REGS);
2328 if (status < 0)
2329 return status;
2330
2331 /* Initialize the tuner state. */
2332 state->tuner_id = state->reg[MT2063_REG_PART_REV];
2333 state->AS_Data.f_ref = MT2063_REF_FREQ;
2334 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
2335 ((u32) state->reg[MT2063_REG_FIFFC] + 640);
2336 state->AS_Data.f_if1_bw = MT2063_IF1_BW;
2337 state->AS_Data.f_out = 43750000UL;
2338 state->AS_Data.f_out_bw = 6750000UL;
2339 state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
2340 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
2341 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
2342 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
2343 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
2344 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
2345 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
2346 state->AS_Data.f_LO1 = 2181000000UL;
2347 state->AS_Data.f_LO2 = 1486249786UL;
2348 state->f_IF1_actual = state->AS_Data.f_if1_Center;
2349 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
2350 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
2351 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
2352 state->num_regs = MT2063_REG_END_REGS;
2353 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
2354 state->ctfilt_sw = 0;
2355
2356 state->CTFiltMax[0] = 69230000;
2357 state->CTFiltMax[1] = 105770000;
2358 state->CTFiltMax[2] = 140350000;
2359 state->CTFiltMax[3] = 177110000;
2360 state->CTFiltMax[4] = 212860000;
2361 state->CTFiltMax[5] = 241130000;
2362 state->CTFiltMax[6] = 274370000;
2363 state->CTFiltMax[7] = 309820000;
2364 state->CTFiltMax[8] = 342450000;
2365 state->CTFiltMax[9] = 378870000;
2366 state->CTFiltMax[10] = 416210000;
2367 state->CTFiltMax[11] = 456500000;
2368 state->CTFiltMax[12] = 495790000;
2369 state->CTFiltMax[13] = 534530000;
2370 state->CTFiltMax[14] = 572610000;
2371 state->CTFiltMax[15] = 598970000;
2372 state->CTFiltMax[16] = 635910000;
2373 state->CTFiltMax[17] = 672130000;
2374 state->CTFiltMax[18] = 714840000;
2375 state->CTFiltMax[19] = 739660000;
2376 state->CTFiltMax[20] = 770410000;
2377 state->CTFiltMax[21] = 814660000;
2378 state->CTFiltMax[22] = 846950000;
2379 state->CTFiltMax[23] = 867820000;
2380 state->CTFiltMax[24] = 915980000;
2381 state->CTFiltMax[25] = 947450000;
2382 state->CTFiltMax[26] = 983110000;
2383 state->CTFiltMax[27] = 1021630000;
2384 state->CTFiltMax[28] = 1061870000;
2385 state->CTFiltMax[29] = 1098330000;
2386 state->CTFiltMax[30] = 1138990000;
2387
2388 /*
2389 ** Fetch the FCU osc value and use it and the fRef value to
2390 ** scale all of the Band Max values
2391 */
2392
2393 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
2394 status = mt2063_write(state,
2395 MT2063_REG_CTUNE_CTRL,
2396 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2397 if (status < 0)
2398 return status;
2399 /* Read the ClearTune filter calibration value */
2400 status = mt2063_read(state,
2401 MT2063_REG_FIFFC,
2402 &state->reg[MT2063_REG_FIFFC], 1);
2403 if (status < 0)
2404 return status;
2405
2406 fcu_osc = state->reg[MT2063_REG_FIFFC];
2407
2408 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
2409 status = mt2063_write(state,
2410 MT2063_REG_CTUNE_CTRL,
2411 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2412 if (status < 0)
2413 return status;
2414
2415 /* Adjust each of the values in the ClearTune filter cross-over table */
2416 for (i = 0; i < 31; i++)
2417 state->CTFiltMax[i] =(state->CTFiltMax[i] / 768) * (fcu_osc + 640);
2418
2419 return (status);
2420}
2421
2422/**************************************************************************** 2101/****************************************************************************
2423** 2102**
2424** Name: MT2063_SetParam 2103** Name: MT2063_SetParam
@@ -3777,21 +3456,255 @@ static u32 MT_Tune_atv(void *h, u32 f_in, u32 bw_in,
3777 return (u32) status; 3456 return (u32) status;
3778} 3457}
3779 3458
3459static const u8 MT2063B0_defaults[] = {
3460 /* Reg, Value */
3461 0x19, 0x05,
3462 0x1B, 0x1D,
3463 0x1C, 0x1F,
3464 0x1D, 0x0F,
3465 0x1E, 0x3F,
3466 0x1F, 0x0F,
3467 0x20, 0x3F,
3468 0x22, 0x21,
3469 0x23, 0x3F,
3470 0x24, 0x20,
3471 0x25, 0x3F,
3472 0x27, 0xEE,
3473 0x2C, 0x27, /* bit at 0x20 is cleared below */
3474 0x30, 0x03,
3475 0x2C, 0x07, /* bit at 0x20 is cleared here */
3476 0x2D, 0x87,
3477 0x2E, 0xAA,
3478 0x28, 0xE1, /* Set the FIFCrst bit here */
3479 0x28, 0xE0, /* Clear the FIFCrst bit here */
3480 0x00
3481};
3482
3483/* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
3484static const u8 MT2063B1_defaults[] = {
3485 /* Reg, Value */
3486 0x05, 0xF0,
3487 0x11, 0x10, /* New Enable AFCsd */
3488 0x19, 0x05,
3489 0x1A, 0x6C,
3490 0x1B, 0x24,
3491 0x1C, 0x28,
3492 0x1D, 0x8F,
3493 0x1E, 0x14,
3494 0x1F, 0x8F,
3495 0x20, 0x57,
3496 0x22, 0x21, /* New - ver 1.03 */
3497 0x23, 0x3C, /* New - ver 1.10 */
3498 0x24, 0x20, /* New - ver 1.03 */
3499 0x2C, 0x24, /* bit at 0x20 is cleared below */
3500 0x2D, 0x87, /* FIFFQ=0 */
3501 0x2F, 0xF3,
3502 0x30, 0x0C, /* New - ver 1.11 */
3503 0x31, 0x1B, /* New - ver 1.11 */
3504 0x2C, 0x04, /* bit at 0x20 is cleared here */
3505 0x28, 0xE1, /* Set the FIFCrst bit here */
3506 0x28, 0xE0, /* Clear the FIFCrst bit here */
3507 0x00
3508};
3509
3510/* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
3511static const u8 MT2063B3_defaults[] = {
3512 /* Reg, Value */
3513 0x05, 0xF0,
3514 0x19, 0x3D,
3515 0x2C, 0x24, /* bit at 0x20 is cleared below */
3516 0x2C, 0x04, /* bit at 0x20 is cleared here */
3517 0x28, 0xE1, /* Set the FIFCrst bit here */
3518 0x28, 0xE0, /* Clear the FIFCrst bit here */
3519 0x00
3520};
3521
3780static int mt2063_init(struct dvb_frontend *fe) 3522static int mt2063_init(struct dvb_frontend *fe)
3781{ 3523{
3782 u32 status = -EINVAL; 3524 u32 status;
3783 struct mt2063_state *state = fe->tuner_priv; 3525 struct mt2063_state *state = fe->tuner_priv;
3526 u8 all_resets = 0xF0; /* reset/load bits */
3527 const u8 *def = NULL;
3528 u32 FCRUN;
3529 s32 maxReads;
3530 u32 fcu_osc;
3531 u32 i;
3532
3533 state->rcvr_mode = MT2063_CABLE_QAM;
3534
3535 /* Read the Part/Rev code from the tuner */
3536 status = mt2063_read(state, MT2063_REG_PART_REV, state->reg, 1);
3537 if (status < 0)
3538 return status;
3539
3540 /* Check the part/rev code */
3541 if (((state->reg[MT2063_REG_PART_REV] != MT2063_B0) /* MT2063 B0 */
3542 &&(state->reg[MT2063_REG_PART_REV] != MT2063_B1) /* MT2063 B1 */
3543 &&(state->reg[MT2063_REG_PART_REV] != MT2063_B3))) /* MT2063 B3 */
3544 return -ENODEV; /* Wrong tuner Part/Rev code */
3784 3545
3785 status = MT2063_Open(fe); 3546 /* Check the 2nd byte of the Part/Rev code from the tuner */
3786 status |= MT2063_SoftwareShutdown(state, 1); 3547 status = mt2063_read(state, MT2063_REG_RSVD_3B,
3787 status |= MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD); 3548 &state->reg[MT2063_REG_RSVD_3B], 1);
3788 3549
3789 if (0 != status) { 3550 /* b7 != 0 ==> NOT MT2063 */
3790 printk("%s %d error status = 0x%x!!\n", __func__, __LINE__, 3551 if (status < 0 ||((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00))
3791 status); 3552 return -ENODEV; /* Wrong tuner Part/Rev code */
3792 return -1; 3553
3554 /* Reset the tuner */
3555 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
3556 if (status < 0)
3557 return status;
3558
3559 /* change all of the default values that vary from the HW reset values */
3560 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
3561 switch (state->reg[MT2063_REG_PART_REV]) {
3562 case MT2063_B3:
3563 def = MT2063B3_defaults;
3564 break;
3565
3566 case MT2063_B1:
3567 def = MT2063B1_defaults;
3568 break;
3569
3570 case MT2063_B0:
3571 def = MT2063B0_defaults;
3572 break;
3573
3574 default:
3575 return -ENODEV;
3576 break;
3793 } 3577 }
3794 3578
3579 while (status >= 0 && *def) {
3580 u8 reg = *def++;
3581 u8 val = *def++;
3582 status = mt2063_write(state, reg, &val, 1);
3583 }
3584 if (status < 0)
3585 return status;
3586
3587 /* Wait for FIFF location to complete. */
3588 FCRUN = 1;
3589 maxReads = 10;
3590 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
3591 msleep(2);
3592 status = mt2063_read(state,
3593 MT2063_REG_XO_STATUS,
3594 &state->
3595 reg[MT2063_REG_XO_STATUS], 1);
3596 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
3597 }
3598
3599 if (FCRUN != 0 || status < 0)
3600 return -ENODEV;
3601
3602 status = mt2063_read(state,
3603 MT2063_REG_FIFFC,
3604 &state->reg[MT2063_REG_FIFFC], 1);
3605 if (status < 0)
3606 return status;
3607
3608 /* Read back all the registers from the tuner */
3609 status = mt2063_read(state,
3610 MT2063_REG_PART_REV,
3611 state->reg, MT2063_REG_END_REGS);
3612 if (status < 0)
3613 return status;
3614
3615 /* Initialize the tuner state. */
3616 state->tuner_id = state->reg[MT2063_REG_PART_REV];
3617 state->AS_Data.f_ref = MT2063_REF_FREQ;
3618 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
3619 ((u32) state->reg[MT2063_REG_FIFFC] + 640);
3620 state->AS_Data.f_if1_bw = MT2063_IF1_BW;
3621 state->AS_Data.f_out = 43750000UL;
3622 state->AS_Data.f_out_bw = 6750000UL;
3623 state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
3624 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
3625 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
3626 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
3627 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
3628 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
3629 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
3630 state->AS_Data.f_LO1 = 2181000000UL;
3631 state->AS_Data.f_LO2 = 1486249786UL;
3632 state->f_IF1_actual = state->AS_Data.f_if1_Center;
3633 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
3634 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
3635 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
3636 state->num_regs = MT2063_REG_END_REGS;
3637 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
3638 state->ctfilt_sw = 0;
3639
3640 state->CTFiltMax[0] = 69230000;
3641 state->CTFiltMax[1] = 105770000;
3642 state->CTFiltMax[2] = 140350000;
3643 state->CTFiltMax[3] = 177110000;
3644 state->CTFiltMax[4] = 212860000;
3645 state->CTFiltMax[5] = 241130000;
3646 state->CTFiltMax[6] = 274370000;
3647 state->CTFiltMax[7] = 309820000;
3648 state->CTFiltMax[8] = 342450000;
3649 state->CTFiltMax[9] = 378870000;
3650 state->CTFiltMax[10] = 416210000;
3651 state->CTFiltMax[11] = 456500000;
3652 state->CTFiltMax[12] = 495790000;
3653 state->CTFiltMax[13] = 534530000;
3654 state->CTFiltMax[14] = 572610000;
3655 state->CTFiltMax[15] = 598970000;
3656 state->CTFiltMax[16] = 635910000;
3657 state->CTFiltMax[17] = 672130000;
3658 state->CTFiltMax[18] = 714840000;
3659 state->CTFiltMax[19] = 739660000;
3660 state->CTFiltMax[20] = 770410000;
3661 state->CTFiltMax[21] = 814660000;
3662 state->CTFiltMax[22] = 846950000;
3663 state->CTFiltMax[23] = 867820000;
3664 state->CTFiltMax[24] = 915980000;
3665 state->CTFiltMax[25] = 947450000;
3666 state->CTFiltMax[26] = 983110000;
3667 state->CTFiltMax[27] = 1021630000;
3668 state->CTFiltMax[28] = 1061870000;
3669 state->CTFiltMax[29] = 1098330000;
3670 state->CTFiltMax[30] = 1138990000;
3671
3672 /*
3673 ** Fetch the FCU osc value and use it and the fRef value to
3674 ** scale all of the Band Max values
3675 */
3676
3677 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
3678 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
3679 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
3680 if (status < 0)
3681 return status;
3682
3683 /* Read the ClearTune filter calibration value */
3684 status = mt2063_read(state, MT2063_REG_FIFFC,
3685 &state->reg[MT2063_REG_FIFFC], 1);
3686 if (status < 0)
3687 return status;
3688
3689 fcu_osc = state->reg[MT2063_REG_FIFFC];
3690
3691 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
3692 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
3693 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
3694 if (status < 0)
3695 return status;
3696
3697 /* Adjust each of the values in the ClearTune filter cross-over table */
3698 for (i = 0; i < 31; i++)
3699 state->CTFiltMax[i] =(state->CTFiltMax[i] / 768) * (fcu_osc + 640);
3700
3701 status = MT2063_SoftwareShutdown(state, 1);
3702 if (status < 0)
3703 return status;
3704 status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
3705 if (status < 0)
3706 return status;
3707
3795 return 0; 3708 return 0;
3796} 3709}
3797 3710
@@ -3858,9 +3771,6 @@ static int mt2063_set_state(struct dvb_frontend *fe,
3858 case DVBFE_TUNER_REFCLOCK: 3771 case DVBFE_TUNER_REFCLOCK:
3859 3772
3860 break; 3773 break;
3861 case DVBFE_TUNER_OPEN:
3862 status = MT2063_Open(fe);
3863 break;
3864 case DVBFE_TUNER_SOFTWARE_SHUTDOWN: 3774 case DVBFE_TUNER_SOFTWARE_SHUTDOWN:
3865 status = MT2063_SoftwareShutdown(state, 1); 3775 status = MT2063_SoftwareShutdown(state, 1);
3866 break; 3776 break;
@@ -3916,7 +3826,6 @@ struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
3916 state->i2c = i2c; 3826 state->i2c = i2c;
3917 state->frontend = fe; 3827 state->frontend = fe;
3918 state->reference = config->refclock / 1000; /* kHz */ 3828 state->reference = config->refclock / 1000; /* kHz */
3919 state->MT2063_init = false;
3920 fe->tuner_priv = state; 3829 fe->tuner_priv = state;
3921 fe->ops.tuner_ops = mt2063_ops; 3830 fe->ops.tuner_ops = mt2063_ops;
3922 3831
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 15:40:15 -0500