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authorJonathan Brassow <jbrassow@redhat.com>2009-04-02 14:55:35 -0400
committerAlasdair G Kergon <agk@redhat.com>2009-04-02 14:55:35 -0400
commit1e302a929e2da6e8448e2058e4b07b07252b57fe (patch)
tree3345d31926a2254a2041d62d270cba76b2590bae /drivers/md/dm-snap-persistent.c
parentfee1998e9c690f9920671e1e0ef187a48cfbbde4 (diff)
dm snapshot: move status to exception store
Let the exception store types print out their status through the new API, rather than having the snapshot code do it. Adjust the buffer position to allow for the preceding DMEMIT in the arguments to type->status(). Signed-off-by: Jonathan Brassow <jbrassow@redhat.com> Signed-off-by: Alasdair G Kergon <agk@redhat.com>
Diffstat (limited to 'drivers/md/dm-snap-persistent.c')
-rw-r--r--drivers/md/dm-snap-persistent.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/md/dm-snap-persistent.c b/drivers/md/dm-snap-persistent.c
index 3907c4ce2ae5..1799205cd945 100644
--- a/drivers/md/dm-snap-persistent.c
+++ b/drivers/md/dm-snap-persistent.c
@@ -688,11 +688,19 @@ static int persistent_ctr(struct dm_exception_store *store,
688 return 0; 688 return 0;
689} 689}
690 690
691static int persistent_status(struct dm_exception_store *store, 691static unsigned persistent_status(struct dm_exception_store *store,
692 status_type_t status, char *result, 692 status_type_t status, char *result,
693 unsigned int maxlen) 693 unsigned maxlen)
694{ 694{
695 int sz = 0; 695 unsigned sz = 0;
696
697 switch (status) {
698 case STATUSTYPE_INFO:
699 break;
700 case STATUSTYPE_TABLE:
701 DMEMIT(" %s P %llu", store->cow->name,
702 (unsigned long long)store->chunk_size);
703 }
696 704
697 return sz; 705 return sz;
698} 706}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 21:03:07 -0500
> #define APIC_LVT_REMOTE_IRR (1<<14) #define APIC_INPUT_POLARITY (1<<13) #define APIC_SEND_PENDING (1<<12) #define APIC_MODE_MASK 0x700 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) #define APIC_MODE_FIXED 0x0 #define APIC_MODE_NMI 0x4 #define APIC_MODE_EXTINT 0x7 #define APIC_LVT1 0x360 #define APIC_LVTERR 0x370 #define APIC_TMICT 0x380 #define APIC_TMCCT 0x390 #define APIC_TDCR 0x3E0 #define APIC_TDR_DIV_TMBASE (1<<2) #define APIC_TDR_DIV_1 0xB #define APIC_TDR_DIV_2 0x0 #define APIC_TDR_DIV_4 0x1 #define APIC_TDR_DIV_8 0x2 #define APIC_TDR_DIV_16 0x3 #define APIC_TDR_DIV_32 0x8 #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define MAX_IO_APICS 64 /* * the local APIC register structure, memory mapped. Not terribly well * tested, but we might eventually use this one in the future - the * problem why we cannot use it right now is the P5 APIC, it has an * errata which cannot take 8-bit reads and writes, only 32-bit ones ... */ #define u32 unsigned int #define lapic ((volatile struct local_apic *)APIC_BASE) struct local_apic { /*000*/ struct { u32 __reserved[4]; } __reserved_01; /*010*/ struct { u32 __reserved[4]; } __reserved_02; /*020*/ struct { /* APIC ID Register */ u32 __reserved_1 : 24, phys_apic_id : 4, __reserved_2 : 4; u32 __reserved[3]; } id; /*030*/ const struct { /* APIC Version Register */ u32 version : 8, __reserved_1 : 8, max_lvt : 8, __reserved_2 : 8; u32 __reserved[3]; } version; /*040*/ struct { u32 __reserved[4]; } __reserved_03; /*050*/ struct { u32 __reserved[4]; } __reserved_04; /*060*/ struct { u32 __reserved[4]; } __reserved_05; /*070*/ struct { u32 __reserved[4]; } __reserved_06; /*080*/ struct { /* Task Priority Register */ u32 priority : 8, __reserved_1 : 24; u32 __reserved_2[3]; } tpr; /*090*/ const struct { /* Arbitration Priority Register */ u32 priority : 8, __reserved_1 : 24; u32 __reserved_2[3]; } apr; /*0A0*/ const struct { /* Processor Priority Register */ u32 priority : 8, __reserved_1 : 24; u32 __reserved_2[3]; } ppr; /*0B0*/ struct { /* End Of Interrupt Register */ u32 eoi; u32 __reserved[3]; } eoi; /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; /*0D0*/ struct { /* Logical Destination Register */ u32 __reserved_1 : 24, logical_dest : 8; u32 __reserved_2[3]; } ldr; /*0E0*/ struct { /* Destination Format Register */ u32 __reserved_1 : 28, model : 4; u32 __reserved_2[3]; } dfr; /*0F0*/ struct { /* Spurious Interrupt Vector Register */ u32 spurious_vector : 8, apic_enabled : 1, focus_cpu : 1, __reserved_2 : 22; u32 __reserved_3[3]; } svr; /*100*/ struct { /* In Service Register */ /*170*/ u32 bitfield; u32 __reserved[3]; } isr [8]; /*180*/ struct { /* Trigger Mode Register */ /*1F0*/ u32 bitfield; u32 __reserved[3]; } tmr [8]; /*200*/ struct { /* Interrupt Request Register */ /*270*/ u32 bitfield; u32 __reserved[3]; } irr [8]; /*280*/ union { /* Error Status Register */ struct { u32 send_cs_error : 1, receive_cs_error : 1, send_accept_error : 1, receive_accept_error : 1, __reserved_1 : 1, send_illegal_vector : 1, receive_illegal_vector : 1, illegal_register_address : 1, __reserved_2 : 24; u32 __reserved_3[3]; } error_bits; struct { u32 errors; u32 __reserved_3[3]; } all_errors; } esr; /*290*/ struct { u32 __reserved[4]; } __reserved_08; /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; /*300*/ struct { /* Interrupt Command Register 1 */ u32 vector : 8, delivery_mode : 3, destination_mode : 1, delivery_status : 1, __reserved_1 : 1, level : 1, trigger : 1, __reserved_2 : 2, shorthand : 2, __reserved_3 : 12; u32 __reserved_4[3]; } icr1; /*310*/ struct { /* Interrupt Command Register 2 */ union { u32 __reserved_1 : 24, phys_dest : 4, __reserved_2 : 4; u32 __reserved_3 : 24, logical_dest : 8; } dest; u32 __reserved_4[3]; } icr2; /*320*/ struct { /* LVT - Timer */ u32 vector : 8, __reserved_1 : 4, delivery_status : 1, __reserved_2 : 3, mask : 1, timer_mode : 1, __reserved_3 : 14; u32 __reserved_4[3]; } lvt_timer; /*330*/ struct { /* LVT - Thermal Sensor */ u32 vector : 8, delivery_mode : 3, __reserved_1 : 1, delivery_status : 1, __reserved_2 : 3, mask : 1, __reserved_3 : 15; u32 __reserved_4[3]; } lvt_thermal; /*340*/ struct { /* LVT - Performance Counter */ u32 vector : 8, delivery_mode : 3, __reserved_1 : 1, delivery_status : 1, __reserved_2 : 3, mask : 1, __reserved_3 : 15; u32 __reserved_4[3]; } lvt_pc; /*350*/ struct { /* LVT - LINT0 */ u32 vector : 8, delivery_mode : 3, __reserved_1 : 1, delivery_status : 1, polarity : 1, remote_irr : 1, trigger : 1, mask : 1, __reserved_2 : 15; u32 __reserved_3[3]; } lvt_lint0; /*360*/ struct { /* LVT - LINT1 */ u32 vector : 8, delivery_mode : 3, __reserved_1 : 1, delivery_status : 1, polarity : 1, remote_irr : 1, trigger : 1, mask : 1, __reserved_2 : 15; u32 __reserved_3[3]; } lvt_lint1; /*370*/ struct { /* LVT - Error */ u32 vector : 8, __reserved_1 : 4, delivery_status : 1, __reserved_2 : 3, mask : 1, __reserved_3 : 15; u32 __reserved_4[3]; } lvt_error; /*380*/ struct { /* Timer Initial Count Register */ u32 initial_count; u32 __reserved_2[3]; } timer_icr; /*390*/ const struct { /* Timer Current Count Register */ u32 curr_count; u32 __reserved_2[3]; } timer_ccr; /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; /*3E0*/ struct { /* Timer Divide Configuration Register */ u32 divisor : 4, __reserved_1 : 28; u32 __reserved_2[3]; } timer_dcr; /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; } __attribute__ ((packed)); #undef u32 #endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 21:03:07 -0500