diff options
| author | Graf Yang <graf.yang@analog.com> | 2009-07-10 07:34:51 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-07-16 01:52:51 -0400 |
| commit | 5bc6e3cfe6db5f33c60f042a9ba203431f334756 (patch) | |
| tree | ff171234a9d19171e955bc1d05279e38c4b39f97 /drivers/md/Makefile | |
| parent | f574a76a3b19848ac61814756716e26f85f2c3f7 (diff) | |
Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions. Any code that attempted to use these would wrongly crash due to
a CPLB miss.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'drivers/md/Makefile')
0 files changed, 0 insertions, 0 deletions