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authorJoe Perches <joe@perches.com>2012-02-19 22:52:38 -0500
committerJoe Perches <joe@perches.com>2012-02-21 12:04:01 -0500
commit475be4d85a274d0961593db41cf85689db1d583c (patch)
treeb2b8931eb747794730522c3cf1898e46948527b9 /drivers/isdn/hisax/isac.c
parent0b0a635f79f91f3755b6518627ea06dd0dbfd523 (diff)
isdn: whitespace coding style cleanup
isdn source code uses a not-current coding style. Update the coding style used on a per-line basis so that git diff -w shows only elided blank lines at EOF. Done with emacs and some scripts and some typing. Built x86 allyesconfig. No detected change in objdump -d or size. Signed-off-by: Joe Perches <joe@perches.com>
Diffstat (limited to 'drivers/isdn/hisax/isac.c')
-rw-r--r--drivers/isdn/hisax/isac.c320
1 files changed, 160 insertions, 160 deletions
diff --git a/drivers/isdn/hisax/isac.c b/drivers/isdn/hisax/isac.c
index 2b66728136d5..bcd70a387307 100644
--- a/drivers/isdn/hisax/isac.c
+++ b/drivers/isdn/hisax/isac.c
@@ -4,7 +4,7 @@
4 * 4 *
5 * Author Karsten Keil 5 * Author Karsten Keil
6 * Copyright by Karsten Keil <keil@isdn4linux.de> 6 * Copyright by Karsten Keil <keil@isdn4linux.de>
7 * 7 *
8 * This software may be used and distributed according to the terms 8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference. 9 * of the GNU General Public License, incorporated herein by reference.
10 * 10 *
@@ -49,34 +49,34 @@ static void
49isac_new_ph(struct IsdnCardState *cs) 49isac_new_ph(struct IsdnCardState *cs)
50{ 50{
51 switch (cs->dc.isac.ph_state) { 51 switch (cs->dc.isac.ph_state) {
52 case (ISAC_IND_RS): 52 case (ISAC_IND_RS):
53 case (ISAC_IND_EI): 53 case (ISAC_IND_EI):
54 ph_command(cs, ISAC_CMD_DUI); 54 ph_command(cs, ISAC_CMD_DUI);
55 l1_msg(cs, HW_RESET | INDICATION, NULL); 55 l1_msg(cs, HW_RESET | INDICATION, NULL);
56 break; 56 break;
57 case (ISAC_IND_DID): 57 case (ISAC_IND_DID):
58 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL); 58 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
59 break; 59 break;
60 case (ISAC_IND_DR): 60 case (ISAC_IND_DR):
61 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); 61 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
62 break; 62 break;
63 case (ISAC_IND_PU): 63 case (ISAC_IND_PU):
64 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); 64 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
65 break; 65 break;
66 case (ISAC_IND_RSY): 66 case (ISAC_IND_RSY):
67 l1_msg(cs, HW_RSYNC | INDICATION, NULL); 67 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
68 break; 68 break;
69 case (ISAC_IND_ARD): 69 case (ISAC_IND_ARD):
70 l1_msg(cs, HW_INFO2 | INDICATION, NULL); 70 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
71 break; 71 break;
72 case (ISAC_IND_AI8): 72 case (ISAC_IND_AI8):
73 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); 73 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
74 break; 74 break;
75 case (ISAC_IND_AI10): 75 case (ISAC_IND_AI10):
76 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL); 76 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
77 break; 77 break;
78 default: 78 default:
79 break; 79 break;
80 } 80 }
81} 81}
82 82
@@ -86,7 +86,7 @@ isac_bh(struct work_struct *work)
86 struct IsdnCardState *cs = 86 struct IsdnCardState *cs =
87 container_of(work, struct IsdnCardState, tqueue); 87 container_of(work, struct IsdnCardState, tqueue);
88 struct PStack *stptr; 88 struct PStack *stptr;
89 89
90 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) { 90 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
91 if (cs->debug) 91 if (cs->debug)
92 debugl1(cs, "D-Channel Busy cleared"); 92 debugl1(cs, "D-Channel Busy cleared");
@@ -97,7 +97,7 @@ isac_bh(struct work_struct *work)
97 } 97 }
98 } 98 }
99 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) 99 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
100 isac_new_ph(cs); 100 isac_new_ph(cs);
101 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) 101 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
102 DChannel_proc_rcv(cs); 102 DChannel_proc_rcv(cs);
103 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) 103 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
@@ -257,11 +257,11 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
257 } else 257 } else
258 schedule_event(cs, D_XMTBUFREADY); 258 schedule_event(cs, D_XMTBUFREADY);
259 } 259 }
260 afterXPR: 260afterXPR:
261 if (val & 0x04) { /* CISQ */ 261 if (val & 0x04) { /* CISQ */
262 exval = cs->readisac(cs, ISAC_CIR0); 262 exval = cs->readisac(cs, ISAC_CIR0);
263 if (cs->debug & L1_DEB_ISAC) 263 if (cs->debug & L1_DEB_ISAC)
264 debugl1(cs, "ISAC CIR0 %02X", exval ); 264 debugl1(cs, "ISAC CIR0 %02X", exval);
265 if (exval & 2) { 265 if (exval & 2) {
266 cs->dc.isac.ph_state = (exval >> 2) & 0xf; 266 cs->dc.isac.ph_state = (exval >> 2) & 0xf;
267 if (cs->debug & L1_DEB_ISAC) 267 if (cs->debug & L1_DEB_ISAC)
@@ -271,7 +271,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
271 if (exval & 1) { 271 if (exval & 1) {
272 exval = cs->readisac(cs, ISAC_CIR1); 272 exval = cs->readisac(cs, ISAC_CIR1);
273 if (cs->debug & L1_DEB_ISAC) 273 if (cs->debug & L1_DEB_ISAC)
274 debugl1(cs, "ISAC CIR1 %02X", exval ); 274 debugl1(cs, "ISAC CIR1 %02X", exval);
275 } 275 }
276 } 276 }
277 if (val & 0x02) { /* SIN */ 277 if (val & 0x02) { /* SIN */
@@ -334,13 +334,13 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
334 } 334 }
335 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0); 335 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
336 if (cs->debug & L1_DEB_MONITOR) 336 if (cs->debug & L1_DEB_MONITOR)
337 debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]); 337 debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp - 1]);
338 if (cs->dc.isac.mon_rxp == 1) { 338 if (cs->dc.isac.mon_rxp == 1) {
339 cs->dc.isac.mocr |= 0x04; 339 cs->dc.isac.mocr |= 0x04;
340 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 340 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
341 } 341 }
342 } 342 }
343 afterMONR0: 343 afterMONR0:
344 if (v1 & 0x80) { 344 if (v1 & 0x80) {
345 if (!cs->dc.isac.mon_rx) { 345 if (!cs->dc.isac.mon_rx) {
346 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { 346 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
@@ -364,11 +364,11 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
364 } 364 }
365 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1); 365 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
366 if (cs->debug & L1_DEB_MONITOR) 366 if (cs->debug & L1_DEB_MONITOR)
367 debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]); 367 debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp - 1]);
368 cs->dc.isac.mocr |= 0x40; 368 cs->dc.isac.mocr |= 0x40;
369 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 369 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
370 } 370 }
371 afterMONR1: 371 afterMONR1:
372 if (v1 & 0x04) { 372 if (v1 & 0x04) {
373 cs->dc.isac.mocr &= 0xf0; 373 cs->dc.isac.mocr &= 0xf0;
374 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 374 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
@@ -384,15 +384,15 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
384 schedule_event(cs, D_RX_MON1); 384 schedule_event(cs, D_RX_MON1);
385 } 385 }
386 if (v1 & 0x02) { 386 if (v1 & 0x02) {
387 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc && 387 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
388 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) && 388 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
389 !(v1 & 0x08))) { 389 !(v1 & 0x08))) {
390 cs->dc.isac.mocr &= 0xf0; 390 cs->dc.isac.mocr &= 0xf0;
391 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 391 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
392 cs->dc.isac.mocr |= 0x0a; 392 cs->dc.isac.mocr |= 0x0a;
393 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 393 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
394 if (cs->dc.isac.mon_txc && 394 if (cs->dc.isac.mon_txc &&
395 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) 395 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
396 schedule_event(cs, D_TX_MON0); 396 schedule_event(cs, D_TX_MON0);
397 goto AfterMOX0; 397 goto AfterMOX0;
398 } 398 }
@@ -401,21 +401,21 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
401 goto AfterMOX0; 401 goto AfterMOX0;
402 } 402 }
403 cs->writeisac(cs, ISAC_MOX0, 403 cs->writeisac(cs, ISAC_MOX0,
404 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]); 404 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
405 if (cs->debug & L1_DEB_MONITOR) 405 if (cs->debug & L1_DEB_MONITOR)
406 debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]); 406 debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp - 1]);
407 } 407 }
408 AfterMOX0: 408 AfterMOX0:
409 if (v1 & 0x20) { 409 if (v1 & 0x20) {
410 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc && 410 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
411 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) && 411 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
412 !(v1 & 0x80))) { 412 !(v1 & 0x80))) {
413 cs->dc.isac.mocr &= 0x0f; 413 cs->dc.isac.mocr &= 0x0f;
414 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 414 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
415 cs->dc.isac.mocr |= 0xa0; 415 cs->dc.isac.mocr |= 0xa0;
416 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); 416 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
417 if (cs->dc.isac.mon_txc && 417 if (cs->dc.isac.mon_txc &&
418 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) 418 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
419 schedule_event(cs, D_TX_MON1); 419 schedule_event(cs, D_TX_MON1);
420 goto AfterMOX1; 420 goto AfterMOX1;
421 } 421 }
@@ -424,11 +424,11 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
424 goto AfterMOX1; 424 goto AfterMOX1;
425 } 425 }
426 cs->writeisac(cs, ISAC_MOX1, 426 cs->writeisac(cs, ISAC_MOX1,
427 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]); 427 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
428 if (cs->debug & L1_DEB_MONITOR) 428 if (cs->debug & L1_DEB_MONITOR)
429 debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]); 429 debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp - 1]);
430 } 430 }
431 AfterMOX1:; 431 AfterMOX1:;
432#endif 432#endif
433 } 433 }
434 } 434 }
@@ -443,123 +443,123 @@ ISAC_l1hw(struct PStack *st, int pr, void *arg)
443 int val; 443 int val;
444 444
445 switch (pr) { 445 switch (pr) {
446 case (PH_DATA |REQUEST): 446 case (PH_DATA | REQUEST):
447 if (cs->debug & DEB_DLOG_HEX) 447 if (cs->debug & DEB_DLOG_HEX)
448 LogFrame(cs, skb->data, skb->len); 448 LogFrame(cs, skb->data, skb->len);
449 if (cs->debug & DEB_DLOG_VERBOSE) 449 if (cs->debug & DEB_DLOG_VERBOSE)
450 dlogframe(cs, skb, 0); 450 dlogframe(cs, skb, 0);
451 spin_lock_irqsave(&cs->lock, flags); 451 spin_lock_irqsave(&cs->lock, flags);
452 if (cs->tx_skb) { 452 if (cs->tx_skb) {
453 skb_queue_tail(&cs->sq, skb); 453 skb_queue_tail(&cs->sq, skb);
454#ifdef L2FRAME_DEBUG /* psa */ 454#ifdef L2FRAME_DEBUG /* psa */
455 if (cs->debug & L1_DEB_LAPD) 455 if (cs->debug & L1_DEB_LAPD)
456 Logl2Frame(cs, skb, "PH_DATA Queued", 0); 456 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
457#endif 457#endif
458 } else { 458 } else {
459 cs->tx_skb = skb; 459 cs->tx_skb = skb;
460 cs->tx_cnt = 0; 460 cs->tx_cnt = 0;
461#ifdef L2FRAME_DEBUG /* psa */ 461#ifdef L2FRAME_DEBUG /* psa */
462 if (cs->debug & L1_DEB_LAPD) 462 if (cs->debug & L1_DEB_LAPD)
463 Logl2Frame(cs, skb, "PH_DATA", 0); 463 Logl2Frame(cs, skb, "PH_DATA", 0);
464#endif 464#endif
465 isac_fill_fifo(cs); 465 isac_fill_fifo(cs);
466 } 466 }
467 spin_unlock_irqrestore(&cs->lock, flags); 467 spin_unlock_irqrestore(&cs->lock, flags);
468 break; 468 break;
469 case (PH_PULL |INDICATION): 469 case (PH_PULL | INDICATION):
470 spin_lock_irqsave(&cs->lock, flags); 470 spin_lock_irqsave(&cs->lock, flags);
471 if (cs->tx_skb) { 471 if (cs->tx_skb) {
472 if (cs->debug & L1_DEB_WARN) 472 if (cs->debug & L1_DEB_WARN)
473 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); 473 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
474 skb_queue_tail(&cs->sq, skb); 474 skb_queue_tail(&cs->sq, skb);
475 } else { 475 } else {
476 if (cs->debug & DEB_DLOG_HEX) 476 if (cs->debug & DEB_DLOG_HEX)
477 LogFrame(cs, skb->data, skb->len); 477 LogFrame(cs, skb->data, skb->len);
478 if (cs->debug & DEB_DLOG_VERBOSE) 478 if (cs->debug & DEB_DLOG_VERBOSE)
479 dlogframe(cs, skb, 0); 479 dlogframe(cs, skb, 0);
480 cs->tx_skb = skb; 480 cs->tx_skb = skb;
481 cs->tx_cnt = 0; 481 cs->tx_cnt = 0;
482#ifdef L2FRAME_DEBUG /* psa */ 482#ifdef L2FRAME_DEBUG /* psa */
483 if (cs->debug & L1_DEB_LAPD) 483 if (cs->debug & L1_DEB_LAPD)
484 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); 484 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
485#endif 485#endif
486 isac_fill_fifo(cs); 486 isac_fill_fifo(cs);
487 } 487 }
488 spin_unlock_irqrestore(&cs->lock, flags); 488 spin_unlock_irqrestore(&cs->lock, flags);
489 break; 489 break;
490 case (PH_PULL | REQUEST): 490 case (PH_PULL | REQUEST):
491#ifdef L2FRAME_DEBUG /* psa */ 491#ifdef L2FRAME_DEBUG /* psa */
492 if (cs->debug & L1_DEB_LAPD) 492 if (cs->debug & L1_DEB_LAPD)
493 debugl1(cs, "-> PH_REQUEST_PULL"); 493 debugl1(cs, "-> PH_REQUEST_PULL");
494#endif 494#endif
495 if (!cs->tx_skb) { 495 if (!cs->tx_skb) {
496 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 496 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
497 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 497 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
498 } else 498 } else
499 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 499 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
500 break; 500 break;
501 case (HW_RESET | REQUEST): 501 case (HW_RESET | REQUEST):
502 spin_lock_irqsave(&cs->lock, flags); 502 spin_lock_irqsave(&cs->lock, flags);
503 if ((cs->dc.isac.ph_state == ISAC_IND_EI) || 503 if ((cs->dc.isac.ph_state == ISAC_IND_EI) ||
504 (cs->dc.isac.ph_state == ISAC_IND_DR) || 504 (cs->dc.isac.ph_state == ISAC_IND_DR) ||
505 (cs->dc.isac.ph_state == ISAC_IND_RS)) 505 (cs->dc.isac.ph_state == ISAC_IND_RS))
506 ph_command(cs, ISAC_CMD_TIM);
507 else
508 ph_command(cs, ISAC_CMD_RS);
509 spin_unlock_irqrestore(&cs->lock, flags);
510 break;
511 case (HW_ENABLE | REQUEST):
512 spin_lock_irqsave(&cs->lock, flags);
513 ph_command(cs, ISAC_CMD_TIM); 506 ph_command(cs, ISAC_CMD_TIM);
514 spin_unlock_irqrestore(&cs->lock, flags); 507 else
515 break; 508 ph_command(cs, ISAC_CMD_RS);
516 case (HW_INFO3 | REQUEST): 509 spin_unlock_irqrestore(&cs->lock, flags);
517 spin_lock_irqsave(&cs->lock, flags); 510 break;
518 ph_command(cs, ISAC_CMD_AR8); 511 case (HW_ENABLE | REQUEST):
519 spin_unlock_irqrestore(&cs->lock, flags); 512 spin_lock_irqsave(&cs->lock, flags);
520 break; 513 ph_command(cs, ISAC_CMD_TIM);
521 case (HW_TESTLOOP | REQUEST): 514 spin_unlock_irqrestore(&cs->lock, flags);
522 spin_lock_irqsave(&cs->lock, flags); 515 break;
523 val = 0; 516 case (HW_INFO3 | REQUEST):
524 if (1 & (long) arg) 517 spin_lock_irqsave(&cs->lock, flags);
525 val |= 0x0c; 518 ph_command(cs, ISAC_CMD_AR8);
526 if (2 & (long) arg) 519 spin_unlock_irqrestore(&cs->lock, flags);
527 val |= 0x3; 520 break;
528 if (test_bit(HW_IOM1, &cs->HW_Flags)) { 521 case (HW_TESTLOOP | REQUEST):
529 /* IOM 1 Mode */ 522 spin_lock_irqsave(&cs->lock, flags);
530 if (!val) { 523 val = 0;
531 cs->writeisac(cs, ISAC_SPCR, 0xa); 524 if (1 & (long) arg)
532 cs->writeisac(cs, ISAC_ADF1, 0x2); 525 val |= 0x0c;
533 } else { 526 if (2 & (long) arg)
534 cs->writeisac(cs, ISAC_SPCR, val); 527 val |= 0x3;
535 cs->writeisac(cs, ISAC_ADF1, 0xa); 528 if (test_bit(HW_IOM1, &cs->HW_Flags)) {
536 } 529 /* IOM 1 Mode */
530 if (!val) {
531 cs->writeisac(cs, ISAC_SPCR, 0xa);
532 cs->writeisac(cs, ISAC_ADF1, 0x2);
537 } else { 533 } else {
538 /* IOM 2 Mode */
539 cs->writeisac(cs, ISAC_SPCR, val); 534 cs->writeisac(cs, ISAC_SPCR, val);
540 if (val) 535 cs->writeisac(cs, ISAC_ADF1, 0xa);
541 cs->writeisac(cs, ISAC_ADF1, 0x8);
542 else
543 cs->writeisac(cs, ISAC_ADF1, 0x0);
544 } 536 }
545 spin_unlock_irqrestore(&cs->lock, flags); 537 } else {
546 break; 538 /* IOM 2 Mode */
547 case (HW_DEACTIVATE | RESPONSE): 539 cs->writeisac(cs, ISAC_SPCR, val);
548 skb_queue_purge(&cs->rq); 540 if (val)
549 skb_queue_purge(&cs->sq); 541 cs->writeisac(cs, ISAC_ADF1, 0x8);
550 if (cs->tx_skb) { 542 else
551 dev_kfree_skb_any(cs->tx_skb); 543 cs->writeisac(cs, ISAC_ADF1, 0x0);
552 cs->tx_skb = NULL; 544 }
553 } 545 spin_unlock_irqrestore(&cs->lock, flags);
554 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) 546 break;
555 del_timer(&cs->dbusytimer); 547 case (HW_DEACTIVATE | RESPONSE):
556 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) 548 skb_queue_purge(&cs->rq);
557 schedule_event(cs, D_CLEARBUSY); 549 skb_queue_purge(&cs->sq);
558 break; 550 if (cs->tx_skb) {
559 default: 551 dev_kfree_skb_any(cs->tx_skb);
560 if (cs->debug & L1_DEB_WARN) 552 cs->tx_skb = NULL;
561 debugl1(cs, "isac_l1hw unknown %04x", pr); 553 }
562 break; 554 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
555 del_timer(&cs->dbusytimer);
556 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
557 schedule_event(cs, D_CLEARBUSY);
558 break;
559 default:
560 if (cs->debug & L1_DEB_WARN)
561 debugl1(cs, "isac_l1hw unknown %04x", pr);
562 break;
563 } 563 }
564} 564}
565 565
@@ -587,7 +587,7 @@ dbusy_timer_handler(struct IsdnCardState *cs)
587 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { 587 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
588 rbch = cs->readisac(cs, ISAC_RBCH); 588 rbch = cs->readisac(cs, ISAC_RBCH);
589 star = cs->readisac(cs, ISAC_STAR); 589 star = cs->readisac(cs, ISAC_STAR);
590 if (cs->debug) 590 if (cs->debug)
591 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x", 591 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
592 rbch, star); 592 rbch, star);
593 if (rbch & ISAC_RBCH_XAC) { /* D-Channel Busy */ 593 if (rbch & ISAC_RBCH_XAC) { /* D-Channel Busy */
@@ -620,8 +620,8 @@ void initisac(struct IsdnCardState *cs)
620 cs->DC_Close = DC_Close_isac; 620 cs->DC_Close = DC_Close_isac;
621 cs->dc.isac.mon_tx = NULL; 621 cs->dc.isac.mon_tx = NULL;
622 cs->dc.isac.mon_rx = NULL; 622 cs->dc.isac.mon_rx = NULL;
623 cs->writeisac(cs, ISAC_MASK, 0xff); 623 cs->writeisac(cs, ISAC_MASK, 0xff);
624 cs->dc.isac.mocr = 0xaa; 624 cs->dc.isac.mocr = 0xaa;
625 if (test_bit(HW_IOM1, &cs->HW_Flags)) { 625 if (test_bit(HW_IOM1, &cs->HW_Flags)) {
626 /* IOM 1 Mode */ 626 /* IOM 1 Mode */
627 cs->writeisac(cs, ISAC_ADF2, 0x0); 627 cs->writeisac(cs, ISAC_ADF2, 0x0);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 04:24:47 -0500