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authorJoe Perches <joe@perches.com>2012-02-19 22:52:38 -0500
committerJoe Perches <joe@perches.com>2012-02-21 12:04:01 -0500
commit475be4d85a274d0961593db41cf85689db1d583c (patch)
treeb2b8931eb747794730522c3cf1898e46948527b9 /drivers/isdn/hisax/ipacx.c
parent0b0a635f79f91f3755b6518627ea06dd0dbfd523 (diff)
isdn: whitespace coding style cleanup
isdn source code uses a not-current coding style. Update the coding style used on a per-line basis so that git diff -w shows only elided blank lines at EOF. Done with emacs and some scripts and some typing. Built x86 allyesconfig. No detected change in objdump -d or size. Signed-off-by: Joe Perches <joe@perches.com>
Diffstat (limited to 'drivers/isdn/hisax/ipacx.c')
-rw-r--r--drivers/isdn/hisax/ipacx.c675
1 files changed, 337 insertions, 338 deletions
diff --git a/drivers/isdn/hisax/ipacx.c b/drivers/isdn/hisax/ipacx.c
index 690840444184..74feb5c83067 100644
--- a/drivers/isdn/hisax/ipacx.c
+++ b/drivers/isdn/hisax/ipacx.c
@@ -1,10 +1,10 @@
1/* 1/*
2 * 2 *
3 * IPACX specific routines 3 * IPACX specific routines
4 * 4 *
5 * Author Joerg Petersohn 5 * Author Joerg Petersohn
6 * Derived from hisax_isac.c, isac.c, hscx.c and others 6 * Derived from hisax_isac.c, isac.c, hscx.c and others
7 * 7 *
8 * This software may be used and distributed according to the terms 8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference. 9 * of the GNU General Public License, incorporated herein by reference.
10 * 10 *
@@ -24,7 +24,7 @@
24#define D_FIFO_SIZE 32 24#define D_FIFO_SIZE 32
25 25
26 26
27// ipacx interrupt mask values 27// ipacx interrupt mask values
28#define _MASK_IMASK 0x2E // global mask 28#define _MASK_IMASK 0x2E // global mask
29#define _MASKB_IMASK 0x0B 29#define _MASKB_IMASK 0x0B
30#define _MASKD_IMASK 0x03 // all on 30#define _MASKD_IMASK 0x03 // all on
@@ -55,33 +55,33 @@ static void clear_pending_ints(struct IsdnCardState *cs);
55//---------------------------------------------------------- 55//----------------------------------------------------------
56// Issue Layer 1 command to chip 56// Issue Layer 1 command to chip
57//---------------------------------------------------------- 57//----------------------------------------------------------
58static void 58static void
59ph_command(struct IsdnCardState *cs, unsigned int command) 59ph_command(struct IsdnCardState *cs, unsigned int command)
60{ 60{
61 if (cs->debug &L1_DEB_ISAC) 61 if (cs->debug & L1_DEB_ISAC)
62 debugl1(cs, "ph_command (%#x) in (%#x)", command, 62 debugl1(cs, "ph_command (%#x) in (%#x)", command,
63 cs->dc.isac.ph_state); 63 cs->dc.isac.ph_state);
64//################################### 64//###################################
65// printk(KERN_INFO "ph_command (%#x)\n", command); 65// printk(KERN_INFO "ph_command (%#x)\n", command);
66//################################### 66//###################################
67 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E); 67 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
68} 68}
69 69
70//---------------------------------------------------------- 70//----------------------------------------------------------
71// Transceiver interrupt handler 71// Transceiver interrupt handler
72//---------------------------------------------------------- 72//----------------------------------------------------------
73static inline void 73static inline void
74cic_int(struct IsdnCardState *cs) 74cic_int(struct IsdnCardState *cs)
75{ 75{
76 u_char event; 76 u_char event;
77 77
78 event = cs->readisac(cs, IPACX_CIR0) >> 4; 78 event = cs->readisac(cs, IPACX_CIR0) >> 4;
79 if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event); 79 if (cs->debug & L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
80//######################################### 80//#########################################
81// printk(KERN_INFO "cic_int(%x)\n", event); 81// printk(KERN_INFO "cic_int(%x)\n", event);
82//######################################### 82//#########################################
83 cs->dc.isac.ph_state = event; 83 cs->dc.isac.ph_state = event;
84 schedule_event(cs, D_L1STATECHANGE); 84 schedule_event(cs, D_L1STATECHANGE);
85} 85}
86 86
87//========================================================== 87//==========================================================
@@ -99,99 +99,99 @@ dch_l2l1(struct PStack *st, int pr, void *arg)
99 u_char cda1_cr; 99 u_char cda1_cr;
100 100
101 switch (pr) { 101 switch (pr) {
102 case (PH_DATA |REQUEST): 102 case (PH_DATA | REQUEST):
103 if (cs->debug &DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); 103 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
104 if (cs->debug &DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); 104 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
105 if (cs->tx_skb) { 105 if (cs->tx_skb) {
106 skb_queue_tail(&cs->sq, skb); 106 skb_queue_tail(&cs->sq, skb);
107#ifdef L2FRAME_DEBUG
108 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
109#endif
110 } else {
111 cs->tx_skb = skb;
112 cs->tx_cnt = 0;
113#ifdef L2FRAME_DEBUG 107#ifdef L2FRAME_DEBUG
114 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0); 108 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
115#endif 109#endif
116 dch_fill_fifo(cs); 110 } else {
117 }
118 break;
119
120 case (PH_PULL |INDICATION):
121 if (cs->tx_skb) {
122 if (cs->debug & L1_DEB_WARN)
123 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
124 skb_queue_tail(&cs->sq, skb);
125 break;
126 }
127 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
128 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
129 cs->tx_skb = skb; 111 cs->tx_skb = skb;
130 cs->tx_cnt = 0; 112 cs->tx_cnt = 0;
131#ifdef L2FRAME_DEBUG 113#ifdef L2FRAME_DEBUG
132 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); 114 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
133#endif 115#endif
134 dch_fill_fifo(cs); 116 dch_fill_fifo(cs);
117 }
118 break;
119
120 case (PH_PULL | INDICATION):
121 if (cs->tx_skb) {
122 if (cs->debug & L1_DEB_WARN)
123 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
124 skb_queue_tail(&cs->sq, skb);
135 break; 125 break;
136 126 }
137 case (PH_PULL | REQUEST): 127 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
128 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
129 cs->tx_skb = skb;
130 cs->tx_cnt = 0;
138#ifdef L2FRAME_DEBUG 131#ifdef L2FRAME_DEBUG
139 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL"); 132 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
140#endif 133#endif
141 if (!cs->tx_skb) { 134 dch_fill_fifo(cs);
142 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 135 break;
143 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
144 } else
145 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
146 break;
147
148 case (HW_RESET | REQUEST):
149 case (HW_ENABLE | REQUEST):
150 if ((cs->dc.isac.ph_state == IPACX_IND_RES) ||
151 (cs->dc.isac.ph_state == IPACX_IND_DR) ||
152 (cs->dc.isac.ph_state == IPACX_IND_DC))
153 ph_command(cs, IPACX_CMD_TIM);
154 else
155 ph_command(cs, IPACX_CMD_RES);
156 break;
157
158 case (HW_INFO3 | REQUEST):
159 ph_command(cs, IPACX_CMD_AR8);
160 break;
161
162 case (HW_TESTLOOP | REQUEST):
163 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
164 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
165 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
166 (void) cs->readisac(cs, IPACX_CDA2_CR);
167 if ((long)arg &1) { // loop B1
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
169 }
170 else { // B1 off
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
172 }
173 if ((long)arg &2) { // loop B2
174 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
175 }
176 else { // B2 off
177 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
178 }
179 break;
180 136
181 case (HW_DEACTIVATE | RESPONSE): 137 case (PH_PULL | REQUEST):
182 skb_queue_purge(&cs->rq); 138#ifdef L2FRAME_DEBUG
183 skb_queue_purge(&cs->sq); 139 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
184 if (cs->tx_skb) { 140#endif
185 dev_kfree_skb_any(cs->tx_skb); 141 if (!cs->tx_skb) {
186 cs->tx_skb = NULL; 142 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
187 } 143 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
188 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) 144 } else
189 del_timer(&cs->dbusytimer); 145 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
190 break; 146 break;
147
148 case (HW_RESET | REQUEST):
149 case (HW_ENABLE | REQUEST):
150 if ((cs->dc.isac.ph_state == IPACX_IND_RES) ||
151 (cs->dc.isac.ph_state == IPACX_IND_DR) ||
152 (cs->dc.isac.ph_state == IPACX_IND_DC))
153 ph_command(cs, IPACX_CMD_TIM);
154 else
155 ph_command(cs, IPACX_CMD_RES);
156 break;
157
158 case (HW_INFO3 | REQUEST):
159 ph_command(cs, IPACX_CMD_AR8);
160 break;
161
162 case (HW_TESTLOOP | REQUEST):
163 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
164 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
165 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
166 (void) cs->readisac(cs, IPACX_CDA2_CR);
167 if ((long)arg & 1) { // loop B1
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a);
169 }
170 else { // B1 off
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a);
172 }
173 if ((long)arg & 2) { // loop B2
174 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14);
175 }
176 else { // B2 off
177 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14);
178 }
179 break;
180
181 case (HW_DEACTIVATE | RESPONSE):
182 skb_queue_purge(&cs->rq);
183 skb_queue_purge(&cs->sq);
184 if (cs->tx_skb) {
185 dev_kfree_skb_any(cs->tx_skb);
186 cs->tx_skb = NULL;
187 }
188 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
189 del_timer(&cs->dbusytimer);
190 break;
191 191
192 default: 192 default:
193 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr); 193 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
194 break; 194 break;
195 } 195 }
196} 196}
197 197
@@ -206,11 +206,11 @@ dbusy_timer_handler(struct IsdnCardState *cs)
206 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { 206 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
207 rbchd = cs->readisac(cs, IPACX_RBCHD); 207 rbchd = cs->readisac(cs, IPACX_RBCHD);
208 stard = cs->readisac(cs, IPACX_STARD); 208 stard = cs->readisac(cs, IPACX_STARD);
209 if (cs->debug) 209 if (cs->debug)
210 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard); 210 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
211 if (!(stard &0x40)) { // D-Channel Busy 211 if (!(stard & 0x40)) { // D-Channel Busy
212 set_bit(FLG_L1_DBUSY, &cs->HW_Flags); 212 set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
213 for (st = cs->stlist; st; st = st->next) { 213 for (st = cs->stlist; st; st = st->next) {
214 st->l1.l1l2(st, PH_PAUSE | INDICATION, NULL); // flow control on 214 st->l1.l1l2(st, PH_PAUSE | INDICATION, NULL); // flow control on
215 } 215 }
216 } else { 216 } else {
@@ -232,30 +232,30 @@ dbusy_timer_handler(struct IsdnCardState *cs)
232//---------------------------------------------------------- 232//----------------------------------------------------------
233// Fill buffer from receive FIFO 233// Fill buffer from receive FIFO
234//---------------------------------------------------------- 234//----------------------------------------------------------
235static void 235static void
236dch_empty_fifo(struct IsdnCardState *cs, int count) 236dch_empty_fifo(struct IsdnCardState *cs, int count)
237{ 237{
238 u_char *ptr; 238 u_char *ptr;
239 239
240 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO)) 240 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
241 debugl1(cs, "dch_empty_fifo()"); 241 debugl1(cs, "dch_empty_fifo()");
242 242
243 // message too large, remove 243 // message too large, remove
244 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { 244 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
245 if (cs->debug &L1_DEB_WARN) 245 if (cs->debug & L1_DEB_WARN)
246 debugl1(cs, "dch_empty_fifo() incoming message too large"); 246 debugl1(cs, "dch_empty_fifo() incoming message too large");
247 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC 247 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
248 cs->rcvidx = 0; 248 cs->rcvidx = 0;
249 return; 249 return;
250 } 250 }
251 251
252 ptr = cs->rcvbuf + cs->rcvidx; 252 ptr = cs->rcvbuf + cs->rcvidx;
253 cs->rcvidx += count; 253 cs->rcvidx += count;
254 254
255 cs->readisacfifo(cs, ptr, count); 255 cs->readisacfifo(cs, ptr, count);
256 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC 256 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
257 257
258 if (cs->debug &L1_DEB_ISAC_FIFO) { 258 if (cs->debug & L1_DEB_ISAC_FIFO) {
259 char *t = cs->dlog; 259 char *t = cs->dlog;
260 260
261 t += sprintf(t, "dch_empty_fifo() cnt %d", count); 261 t += sprintf(t, "dch_empty_fifo() cnt %d", count);
@@ -267,15 +267,15 @@ dch_empty_fifo(struct IsdnCardState *cs, int count)
267//---------------------------------------------------------- 267//----------------------------------------------------------
268// Fill transmit FIFO 268// Fill transmit FIFO
269//---------------------------------------------------------- 269//----------------------------------------------------------
270static void 270static void
271dch_fill_fifo(struct IsdnCardState *cs) 271dch_fill_fifo(struct IsdnCardState *cs)
272{ 272{
273 int count; 273 int count;
274 u_char cmd, *ptr; 274 u_char cmd, *ptr;
275 275
276 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO)) 276 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
277 debugl1(cs, "dch_fill_fifo()"); 277 debugl1(cs, "dch_fill_fifo()");
278 278
279 if (!cs->tx_skb) return; 279 if (!cs->tx_skb) return;
280 count = cs->tx_skb->len; 280 count = cs->tx_skb->len;
281 if (count <= 0) return; 281 if (count <= 0) return;
@@ -286,14 +286,14 @@ dch_fill_fifo(struct IsdnCardState *cs)
286 } else { 286 } else {
287 cmd = 0x0A; // XTF | XME 287 cmd = 0x0A; // XTF | XME
288 } 288 }
289 289
290 ptr = cs->tx_skb->data; 290 ptr = cs->tx_skb->data;
291 skb_pull(cs->tx_skb, count); 291 skb_pull(cs->tx_skb, count);
292 cs->tx_cnt += count; 292 cs->tx_cnt += count;
293 cs->writeisacfifo(cs, ptr, count); 293 cs->writeisacfifo(cs, ptr, count);
294 cs->writeisac(cs, IPACX_CMDRD, cmd); 294 cs->writeisac(cs, IPACX_CMDRD, cmd);
295 295
296 // set timeout for transmission contol 296 // set timeout for transmission contol
297 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { 297 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
298 debugl1(cs, "dch_fill_fifo dbusytimer running"); 298 debugl1(cs, "dch_fill_fifo dbusytimer running");
299 del_timer(&cs->dbusytimer); 299 del_timer(&cs->dbusytimer);
@@ -301,8 +301,8 @@ dch_fill_fifo(struct IsdnCardState *cs)
301 init_timer(&cs->dbusytimer); 301 init_timer(&cs->dbusytimer);
302 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); 302 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
303 add_timer(&cs->dbusytimer); 303 add_timer(&cs->dbusytimer);
304 304
305 if (cs->debug &L1_DEB_ISAC_FIFO) { 305 if (cs->debug & L1_DEB_ISAC_FIFO) {
306 char *t = cs->dlog; 306 char *t = cs->dlog;
307 307
308 t += sprintf(t, "dch_fill_fifo() cnt %d", count); 308 t += sprintf(t, "dch_fill_fifo() cnt %d", count);
@@ -314,7 +314,7 @@ dch_fill_fifo(struct IsdnCardState *cs)
314//---------------------------------------------------------- 314//----------------------------------------------------------
315// D channel interrupt handler 315// D channel interrupt handler
316//---------------------------------------------------------- 316//----------------------------------------------------------
317static inline void 317static inline void
318dch_int(struct IsdnCardState *cs) 318dch_int(struct IsdnCardState *cs)
319{ 319{
320 struct sk_buff *skb; 320 struct sk_buff *skb;
@@ -322,31 +322,31 @@ dch_int(struct IsdnCardState *cs)
322 int count; 322 int count;
323 323
324 istad = cs->readisac(cs, IPACX_ISTAD); 324 istad = cs->readisac(cs, IPACX_ISTAD);
325//############################################## 325//##############################################
326// printk(KERN_WARNING "dch_int(istad=%02x)\n", istad); 326// printk(KERN_WARNING "dch_int(istad=%02x)\n", istad);
327//############################################## 327//##############################################
328 328
329 if (istad &0x80) { // RME 329 if (istad & 0x80) { // RME
330 rstad = cs->readisac(cs, IPACX_RSTAD); 330 rstad = cs->readisac(cs, IPACX_RSTAD);
331 if ((rstad &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB) 331 if ((rstad & 0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
332 if (!(rstad &0x80)) 332 if (!(rstad & 0x80))
333 if (cs->debug &L1_DEB_WARN) 333 if (cs->debug & L1_DEB_WARN)
334 debugl1(cs, "dch_int(): invalid frame"); 334 debugl1(cs, "dch_int(): invalid frame");
335 if ((rstad &0x40)) 335 if ((rstad & 0x40))
336 if (cs->debug &L1_DEB_WARN) 336 if (cs->debug & L1_DEB_WARN)
337 debugl1(cs, "dch_int(): RDO"); 337 debugl1(cs, "dch_int(): RDO");
338 if (!(rstad &0x20)) 338 if (!(rstad & 0x20))
339 if (cs->debug &L1_DEB_WARN) 339 if (cs->debug & L1_DEB_WARN)
340 debugl1(cs, "dch_int(): CRC error"); 340 debugl1(cs, "dch_int(): CRC error");
341 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC 341 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
342 } else { // received frame ok 342 } else { // received frame ok
343 count = cs->readisac(cs, IPACX_RBCLD); 343 count = cs->readisac(cs, IPACX_RBCLD);
344 if (count) count--; // RSTAB is last byte 344 if (count) count--; // RSTAB is last byte
345 count &= D_FIFO_SIZE-1; 345 count &= D_FIFO_SIZE - 1;
346 if (count == 0) count = D_FIFO_SIZE; 346 if (count == 0) count = D_FIFO_SIZE;
347 dch_empty_fifo(cs, count); 347 dch_empty_fifo(cs, count);
348 if ((count = cs->rcvidx) > 0) { 348 if ((count = cs->rcvidx) > 0) {
349 cs->rcvidx = 0; 349 cs->rcvidx = 0;
350 if (!(skb = dev_alloc_skb(count))) 350 if (!(skb = dev_alloc_skb(count)))
351 printk(KERN_WARNING "HiSax dch_int(): receive out of memory\n"); 351 printk(KERN_WARNING "HiSax dch_int(): receive out of memory\n");
352 else { 352 else {
@@ -354,57 +354,57 @@ dch_int(struct IsdnCardState *cs)
354 skb_queue_tail(&cs->rq, skb); 354 skb_queue_tail(&cs->rq, skb);
355 } 355 }
356 } 356 }
357 } 357 }
358 cs->rcvidx = 0; 358 cs->rcvidx = 0;
359 schedule_event(cs, D_RCVBUFREADY); 359 schedule_event(cs, D_RCVBUFREADY);
360 } 360 }
361 361
362 if (istad &0x40) { // RPF 362 if (istad & 0x40) { // RPF
363 dch_empty_fifo(cs, D_FIFO_SIZE); 363 dch_empty_fifo(cs, D_FIFO_SIZE);
364 } 364 }
365 365
366 if (istad &0x20) { // RFO 366 if (istad & 0x20) { // RFO
367 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO"); 367 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
368 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES 368 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
369 } 369 }
370 370
371 if (istad &0x10) { // XPR 371 if (istad & 0x10) { // XPR
372 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) 372 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
373 del_timer(&cs->dbusytimer); 373 del_timer(&cs->dbusytimer);
374 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) 374 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
375 schedule_event(cs, D_CLEARBUSY); 375 schedule_event(cs, D_CLEARBUSY);
376 if (cs->tx_skb) { 376 if (cs->tx_skb) {
377 if (cs->tx_skb->len) { 377 if (cs->tx_skb->len) {
378 dch_fill_fifo(cs); 378 dch_fill_fifo(cs);
379 goto afterXPR; 379 goto afterXPR;
380 } 380 }
381 else { 381 else {
382 dev_kfree_skb_irq(cs->tx_skb); 382 dev_kfree_skb_irq(cs->tx_skb);
383 cs->tx_skb = NULL; 383 cs->tx_skb = NULL;
384 cs->tx_cnt = 0; 384 cs->tx_cnt = 0;
385 } 385 }
386 } 386 }
387 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { 387 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
388 cs->tx_cnt = 0; 388 cs->tx_cnt = 0;
389 dch_fill_fifo(cs); 389 dch_fill_fifo(cs);
390 } 390 }
391 else { 391 else {
392 schedule_event(cs, D_XMTBUFREADY); 392 schedule_event(cs, D_XMTBUFREADY);
393 } 393 }
394 } 394 }
395 afterXPR: 395afterXPR:
396 396
397 if (istad &0x0C) { // XDU or XMR 397 if (istad & 0x0C) { // XDU or XMR
398 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): XDU"); 398 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
399 if (cs->tx_skb) { 399 if (cs->tx_skb) {
400 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit 400 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
401 cs->tx_cnt = 0; 401 cs->tx_cnt = 0;
402 dch_fill_fifo(cs); 402 dch_fill_fifo(cs);
403 } else { 403 } else {
404 printk(KERN_WARNING "HiSax: ISAC XDU no skb\n"); 404 printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
405 debugl1(cs, "ISAC XDU no skb"); 405 debugl1(cs, "ISAC XDU no skb");
406 } 406 }
407 } 407 }
408} 408}
409 409
410//---------------------------------------------------------- 410//----------------------------------------------------------
@@ -423,15 +423,15 @@ dch_init(struct IsdnCardState *cs)
423 printk(KERN_INFO "HiSax: IPACX ISDN driver v0.1.0\n"); 423 printk(KERN_INFO "HiSax: IPACX ISDN driver v0.1.0\n");
424 424
425 cs->setstack_d = dch_setstack; 425 cs->setstack_d = dch_setstack;
426 426
427 cs->dbusytimer.function = (void *) dbusy_timer_handler; 427 cs->dbusytimer.function = (void *) dbusy_timer_handler;
428 cs->dbusytimer.data = (long) cs; 428 cs->dbusytimer.data = (long) cs;
429 init_timer(&cs->dbusytimer); 429 init_timer(&cs->dbusytimer);
430 430
431 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD 431 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
432 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter 432 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
433 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go 433 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
434 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel 434 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
435} 435}
436 436
437 437
@@ -450,55 +450,55 @@ bch_l2l1(struct PStack *st, int pr, void *arg)
450 u_long flags; 450 u_long flags;
451 451
452 switch (pr) { 452 switch (pr) {
453 case (PH_DATA | REQUEST): 453 case (PH_DATA | REQUEST):
454 spin_lock_irqsave(&bcs->cs->lock, flags); 454 spin_lock_irqsave(&bcs->cs->lock, flags);
455 if (bcs->tx_skb) { 455 if (bcs->tx_skb) {
456 skb_queue_tail(&bcs->squeue, skb); 456 skb_queue_tail(&bcs->squeue, skb);
457 } else { 457 } else {
458 bcs->tx_skb = skb; 458 bcs->tx_skb = skb;
459 set_bit(BC_FLG_BUSY, &bcs->Flag); 459 set_bit(BC_FLG_BUSY, &bcs->Flag);
460 bcs->hw.hscx.count = 0; 460 bcs->hw.hscx.count = 0;
461 bch_fill_fifo(bcs); 461 bch_fill_fifo(bcs);
462 } 462 }
463 spin_unlock_irqrestore(&bcs->cs->lock, flags); 463 spin_unlock_irqrestore(&bcs->cs->lock, flags);
464 break; 464 break;
465 case (PH_PULL | INDICATION): 465 case (PH_PULL | INDICATION):
466 spin_lock_irqsave(&bcs->cs->lock, flags); 466 spin_lock_irqsave(&bcs->cs->lock, flags);
467 if (bcs->tx_skb) { 467 if (bcs->tx_skb) {
468 printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n"); 468 printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n");
469 } else { 469 } else {
470 set_bit(BC_FLG_BUSY, &bcs->Flag); 470 set_bit(BC_FLG_BUSY, &bcs->Flag);
471 bcs->tx_skb = skb; 471 bcs->tx_skb = skb;
472 bcs->hw.hscx.count = 0; 472 bcs->hw.hscx.count = 0;
473 bch_fill_fifo(bcs); 473 bch_fill_fifo(bcs);
474 } 474 }
475 spin_unlock_irqrestore(&bcs->cs->lock, flags); 475 spin_unlock_irqrestore(&bcs->cs->lock, flags);
476 break; 476 break;
477 case (PH_PULL | REQUEST): 477 case (PH_PULL | REQUEST):
478 if (!bcs->tx_skb) { 478 if (!bcs->tx_skb) {
479 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 479 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
480 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 480 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
481 } else 481 } else
482 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 482 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
483 break; 483 break;
484 case (PH_ACTIVATE | REQUEST): 484 case (PH_ACTIVATE | REQUEST):
485 spin_lock_irqsave(&bcs->cs->lock, flags); 485 spin_lock_irqsave(&bcs->cs->lock, flags);
486 set_bit(BC_FLG_ACTIV, &bcs->Flag); 486 set_bit(BC_FLG_ACTIV, &bcs->Flag);
487 bch_mode(bcs, st->l1.mode, st->l1.bc); 487 bch_mode(bcs, st->l1.mode, st->l1.bc);
488 spin_unlock_irqrestore(&bcs->cs->lock, flags); 488 spin_unlock_irqrestore(&bcs->cs->lock, flags);
489 l1_msg_b(st, pr, arg); 489 l1_msg_b(st, pr, arg);
490 break; 490 break;
491 case (PH_DEACTIVATE | REQUEST): 491 case (PH_DEACTIVATE | REQUEST):
492 l1_msg_b(st, pr, arg); 492 l1_msg_b(st, pr, arg);
493 break; 493 break;
494 case (PH_DEACTIVATE | CONFIRM): 494 case (PH_DEACTIVATE | CONFIRM):
495 spin_lock_irqsave(&bcs->cs->lock, flags); 495 spin_lock_irqsave(&bcs->cs->lock, flags);
496 clear_bit(BC_FLG_ACTIV, &bcs->Flag); 496 clear_bit(BC_FLG_ACTIV, &bcs->Flag);
497 clear_bit(BC_FLG_BUSY, &bcs->Flag); 497 clear_bit(BC_FLG_BUSY, &bcs->Flag);
498 bch_mode(bcs, 0, st->l1.bc); 498 bch_mode(bcs, 0, st->l1.bc);
499 spin_unlock_irqrestore(&bcs->cs->lock, flags); 499 spin_unlock_irqrestore(&bcs->cs->lock, flags);
500 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); 500 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
501 break; 501 break;
502 } 502 }
503} 503}
504 504
@@ -513,28 +513,28 @@ bch_empty_fifo(struct BCState *bcs, int count)
513 int cnt; 513 int cnt;
514 514
515 cs = bcs->cs; 515 cs = bcs->cs;
516 hscx = bcs->hw.hscx.hscx; 516 hscx = bcs->hw.hscx.hscx;
517 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO)) 517 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
518 debugl1(cs, "bch_empty_fifo()"); 518 debugl1(cs, "bch_empty_fifo()");
519 519
520 // message too large, remove 520 // message too large, remove
521 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) { 521 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
522 if (cs->debug &L1_DEB_WARN) 522 if (cs->debug & L1_DEB_WARN)
523 debugl1(cs, "bch_empty_fifo() incoming packet too large"); 523 debugl1(cs, "bch_empty_fifo() incoming packet too large");
524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC 524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
525 bcs->hw.hscx.rcvidx = 0; 525 bcs->hw.hscx.rcvidx = 0;
526 return; 526 return;
527 } 527 }
528 528
529 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; 529 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
530 cnt = count; 530 cnt = count;
531 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB); 531 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
532 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC 532 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
533 533
534 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx; 534 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
535 bcs->hw.hscx.rcvidx += count; 535 bcs->hw.hscx.rcvidx += count;
536 536
537 if (cs->debug &L1_DEB_HSCX_FIFO) { 537 if (cs->debug & L1_DEB_HSCX_FIFO) {
538 char *t = bcs->blog; 538 char *t = bcs->blog;
539 539
540 t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count); 540 t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);
@@ -554,7 +554,7 @@ bch_fill_fifo(struct BCState *bcs)
554 u_char *ptr, *p, hscx; 554 u_char *ptr, *p, hscx;
555 555
556 cs = bcs->cs; 556 cs = bcs->cs;
557 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO)) 557 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
558 debugl1(cs, "bch_fill_fifo()"); 558 debugl1(cs, "bch_fill_fifo()");
559 559
560 if (!bcs->tx_skb) return; 560 if (!bcs->tx_skb) return;
@@ -567,17 +567,17 @@ bch_fill_fifo(struct BCState *bcs)
567 count = B_FIFO_SIZE; 567 count = B_FIFO_SIZE;
568 } else { 568 } else {
569 count = bcs->tx_skb->len; 569 count = bcs->tx_skb->len;
570 } 570 }
571 cnt = count; 571 cnt = count;
572 572
573 p = ptr = bcs->tx_skb->data; 573 p = ptr = bcs->tx_skb->data;
574 skb_pull(bcs->tx_skb, count); 574 skb_pull(bcs->tx_skb, count);
575 bcs->tx_cnt -= count; 575 bcs->tx_cnt -= count;
576 bcs->hw.hscx.count += count; 576 bcs->hw.hscx.count += count;
577 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); 577 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
578 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); 578 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
579 579
580 if (cs->debug &L1_DEB_HSCX_FIFO) { 580 if (cs->debug & L1_DEB_HSCX_FIFO) {
581 char *t = bcs->blog; 581 char *t = bcs->blog;
582 582
583 t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count); 583 t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count);
@@ -600,31 +600,31 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
600 600
601 bcs = cs->bcs + hscx; 601 bcs = cs->bcs + hscx;
602 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB); 602 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
603//############################################## 603//##############################################
604// printk(KERN_WARNING "bch_int(istab=%02x)\n", istab); 604// printk(KERN_WARNING "bch_int(istab=%02x)\n", istab);
605//############################################## 605//##############################################
606 if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return; 606 if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return;
607 607
608 if (istab &0x80) { // RME 608 if (istab & 0x80) { // RME
609 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB); 609 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
610 if ((rstab &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB) 610 if ((rstab & 0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
611 if (!(rstab &0x80)) 611 if (!(rstab & 0x80))
612 if (cs->debug &L1_DEB_WARN) 612 if (cs->debug & L1_DEB_WARN)
613 debugl1(cs, "bch_int() B-%d: invalid frame", hscx); 613 debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
614 if ((rstab &0x40) && (bcs->mode != L1_MODE_NULL)) 614 if ((rstab & 0x40) && (bcs->mode != L1_MODE_NULL))
615 if (cs->debug &L1_DEB_WARN) 615 if (cs->debug & L1_DEB_WARN)
616 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode); 616 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
617 if (!(rstab &0x20)) 617 if (!(rstab & 0x20))
618 if (cs->debug &L1_DEB_WARN) 618 if (cs->debug & L1_DEB_WARN)
619 debugl1(cs, "bch_int() B-%d: CRC error", hscx); 619 debugl1(cs, "bch_int() B-%d: CRC error", hscx);
620 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC 620 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
621 } 621 }
622 else { // received frame ok 622 else { // received frame ok
623 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1); 623 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1);
624 if (count == 0) count = B_FIFO_SIZE; 624 if (count == 0) count = B_FIFO_SIZE;
625 bch_empty_fifo(bcs, count); 625 bch_empty_fifo(bcs, count);
626 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) { 626 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
627 if (cs->debug &L1_DEB_HSCX_FIFO) 627 if (cs->debug & L1_DEB_HSCX_FIFO)
628 debugl1(cs, "bch_int Frame %d", count); 628 debugl1(cs, "bch_int Frame %d", count);
629 if (!(skb = dev_alloc_skb(count))) 629 if (!(skb = dev_alloc_skb(count)))
630 printk(KERN_WARNING "HiSax bch_int(): receive frame out of memory\n"); 630 printk(KERN_WARNING "HiSax bch_int(): receive frame out of memory\n");
@@ -637,8 +637,8 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
637 bcs->hw.hscx.rcvidx = 0; 637 bcs->hw.hscx.rcvidx = 0;
638 schedule_event(bcs, B_RCVBUFREADY); 638 schedule_event(bcs, B_RCVBUFREADY);
639 } 639 }
640 640
641 if (istab &0x40) { // RPF 641 if (istab & 0x40) { // RPF
642 bch_empty_fifo(bcs, B_FIFO_SIZE); 642 bch_empty_fifo(bcs, B_FIFO_SIZE);
643 643
644 if (bcs->mode == L1_MODE_TRANS) { // queue every chunk 644 if (bcs->mode == L1_MODE_TRANS) { // queue every chunk
@@ -653,21 +653,21 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
653 schedule_event(bcs, B_RCVBUFREADY); 653 schedule_event(bcs, B_RCVBUFREADY);
654 } 654 }
655 } 655 }
656 656
657 if (istab &0x20) { // RFO 657 if (istab & 0x20) { // RFO
658 if (cs->debug &L1_DEB_WARN) 658 if (cs->debug & L1_DEB_WARN)
659 debugl1(cs, "bch_int() B-%d: RFO error", hscx); 659 debugl1(cs, "bch_int() B-%d: RFO error", hscx);
660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES 660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
661 } 661 }
662 662
663 if (istab &0x10) { // XPR 663 if (istab & 0x10) { // XPR
664 if (bcs->tx_skb) { 664 if (bcs->tx_skb) {
665 if (bcs->tx_skb->len) { 665 if (bcs->tx_skb->len) {
666 bch_fill_fifo(bcs); 666 bch_fill_fifo(bcs);
667 goto afterXPR; 667 goto afterXPR;
668 } else { 668 } else {
669 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) && 669 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
670 (PACKET_NOACK != bcs->tx_skb->pkt_type)) { 670 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
671 u_long flags; 671 u_long flags;
672 spin_lock_irqsave(&bcs->aclock, flags); 672 spin_lock_irqsave(&bcs->aclock, flags);
673 bcs->ackcnt += bcs->hw.hscx.count; 673 bcs->ackcnt += bcs->hw.hscx.count;
@@ -678,7 +678,7 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
678 dev_kfree_skb_irq(bcs->tx_skb); 678 dev_kfree_skb_irq(bcs->tx_skb);
679 bcs->hw.hscx.count = 0; 679 bcs->hw.hscx.count = 0;
680 bcs->tx_skb = NULL; 680 bcs->tx_skb = NULL;
681 } 681 }
682 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { 682 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
683 bcs->hw.hscx.count = 0; 683 bcs->hw.hscx.count = 0;
684 set_bit(BC_FLG_BUSY, &bcs->Flag); 684 set_bit(BC_FLG_BUSY, &bcs->Flag);
@@ -688,22 +688,22 @@ bch_int(struct IsdnCardState *cs, u_char hscx)
688 schedule_event(bcs, B_XMTBUFREADY); 688 schedule_event(bcs, B_XMTBUFREADY);
689 } 689 }
690 } 690 }
691 afterXPR: 691afterXPR:
692 692
693 if (istab &0x04) { // XDU 693 if (istab & 0x04) { // XDU
694 if (bcs->mode == L1_MODE_TRANS) { 694 if (bcs->mode == L1_MODE_TRANS) {
695 bch_fill_fifo(bcs); 695 bch_fill_fifo(bcs);
696 } 696 }
697 else { 697 else {
698 if (bcs->tx_skb) { // restart transmitting the whole frame 698 if (bcs->tx_skb) { // restart transmitting the whole frame
699 skb_push(bcs->tx_skb, bcs->hw.hscx.count); 699 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
700 bcs->tx_cnt += bcs->hw.hscx.count; 700 bcs->tx_cnt += bcs->hw.hscx.count;
701 bcs->hw.hscx.count = 0; 701 bcs->hw.hscx.count = 0;
702 } 702 }
703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES 703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES
704 if (cs->debug &L1_DEB_WARN) 704 if (cs->debug & L1_DEB_WARN)
705 debugl1(cs, "bch_int() B-%d XDU error", hscx); 705 debugl1(cs, "bch_int() B-%d XDU error", hscx);
706 } 706 }
707 } 707 }
708} 708}
709 709
@@ -715,43 +715,43 @@ bch_mode(struct BCState *bcs, int mode, int bc)
715 struct IsdnCardState *cs = bcs->cs; 715 struct IsdnCardState *cs = bcs->cs;
716 int hscx = bcs->hw.hscx.hscx; 716 int hscx = bcs->hw.hscx.hscx;
717 717
718 bc = bc ? 1 : 0; // in case bc is greater than 1 718 bc = bc ? 1 : 0; // in case bc is greater than 1
719 if (cs->debug & L1_DEB_HSCX) 719 if (cs->debug & L1_DEB_HSCX)
720 debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc); 720 debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc);
721 bcs->mode = mode; 721 bcs->mode = mode;
722 bcs->channel = bc; 722 bcs->channel = bc;
723 723
724 // map controller to according timeslot 724 // map controller to according timeslot
725 if (!hscx) 725 if (!hscx)
726 { 726 {
727 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc); 727 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
728 cs->writeisac(cs, IPACX_BCHA_CR, 0x88); 728 cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
729 } 729 }
730 else 730 else
731 { 731 {
732 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc); 732 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
733 cs->writeisac(cs, IPACX_BCHB_CR, 0x88); 733 cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
734 } 734 }
735 735
736 switch (mode) { 736 switch (mode) {
737 case (L1_MODE_NULL): 737 case (L1_MODE_NULL):
738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off 738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. 739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off 740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments 741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
742 break; 742 break;
743 case (L1_MODE_TRANS): 743 case (L1_MODE_TRANS):
744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode 744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments 746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); 747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
748 break; 748 break;
749 case (L1_MODE_HDLC): 749 case (L1_MODE_HDLC):
750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled 751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments 752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); 753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
754 break; 754 break;
755 } 755 }
756} 756}
757 757
@@ -784,13 +784,13 @@ bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
784 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) { 784 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
785 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) { 785 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
786 printk(KERN_WARNING 786 printk(KERN_WARNING
787 "HiSax open_bchstate(): No memory for hscx.rcvbuf\n"); 787 "HiSax open_bchstate(): No memory for hscx.rcvbuf\n");
788 clear_bit(BC_FLG_INIT, &bcs->Flag); 788 clear_bit(BC_FLG_INIT, &bcs->Flag);
789 return (1); 789 return (1);
790 } 790 }
791 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) { 791 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
792 printk(KERN_WARNING 792 printk(KERN_WARNING
793 "HiSax open_bchstate: No memory for bcs->blog\n"); 793 "HiSax open_bchstate: No memory for bcs->blog\n");
794 clear_bit(BC_FLG_INIT, &bcs->Flag); 794 clear_bit(BC_FLG_INIT, &bcs->Flag);
795 kfree(bcs->hw.hscx.rcvbuf); 795 kfree(bcs->hw.hscx.rcvbuf);
796 bcs->hw.hscx.rcvbuf = NULL; 796 bcs->hw.hscx.rcvbuf = NULL;
@@ -842,21 +842,21 @@ bch_init(struct IsdnCardState *cs, int hscx)
842//---------------------------------------------------------- 842//----------------------------------------------------------
843// Main interrupt handler 843// Main interrupt handler
844//---------------------------------------------------------- 844//----------------------------------------------------------
845void 845void
846interrupt_ipacx(struct IsdnCardState *cs) 846interrupt_ipacx(struct IsdnCardState *cs)
847{ 847{
848 u_char ista; 848 u_char ista;
849 849
850 while ((ista = cs->readisac(cs, IPACX_ISTA))) { 850 while ((ista = cs->readisac(cs, IPACX_ISTA))) {
851//################################################# 851//#################################################
852// printk(KERN_WARNING "interrupt_ipacx(ista=%02x)\n", ista); 852// printk(KERN_WARNING "interrupt_ipacx(ista=%02x)\n", ista);
853//################################################# 853//#################################################
854 if (ista &0x80) bch_int(cs, 0); // B channel interrupts 854 if (ista & 0x80) bch_int(cs, 0); // B channel interrupts
855 if (ista &0x40) bch_int(cs, 1); 855 if (ista & 0x40) bch_int(cs, 1);
856 856
857 if (ista &0x01) dch_int(cs); // D channel 857 if (ista & 0x01) dch_int(cs); // D channel
858 if (ista &0x10) cic_int(cs); // Layer 1 state 858 if (ista & 0x10) cic_int(cs); // Layer 1 state
859 } 859 }
860} 860}
861 861
862//---------------------------------------------------------- 862//----------------------------------------------------------
@@ -867,17 +867,17 @@ clear_pending_ints(struct IsdnCardState *cs)
867{ 867{
868 int ista; 868 int ista;
869 869
870 // all interrupts off 870 // all interrupts off
871 cs->writeisac(cs, IPACX_MASK, 0xff); 871 cs->writeisac(cs, IPACX_MASK, 0xff);
872 cs->writeisac(cs, IPACX_MASKD, 0xff); 872 cs->writeisac(cs, IPACX_MASKD, 0xff);
873 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff); 873 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
874 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff); 874 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
875 875
876 ista = cs->readisac(cs, IPACX_ISTA); 876 ista = cs->readisac(cs, IPACX_ISTA);
877 if (ista &0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB); 877 if (ista & 0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
878 if (ista &0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB); 878 if (ista & 0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
879 if (ista &0x10) cs->readisac(cs, IPACX_CIR0); 879 if (ista & 0x10) cs->readisac(cs, IPACX_CIR0);
880 if (ista &0x01) cs->readisac(cs, IPACX_ISTAD); 880 if (ista & 0x01) cs->readisac(cs, IPACX_ISTAD);
881} 881}
882 882
883//---------------------------------------------------------- 883//----------------------------------------------------------
@@ -887,23 +887,23 @@ clear_pending_ints(struct IsdnCardState *cs)
887void 887void
888init_ipacx(struct IsdnCardState *cs, int part) 888init_ipacx(struct IsdnCardState *cs, int part)
889{ 889{
890 if (part &1) { // initialise chip 890 if (part & 1) { // initialise chip
891//################################################## 891//##################################################
892// printk(KERN_INFO "init_ipacx(%x)\n", part); 892// printk(KERN_INFO "init_ipacx(%x)\n", part);
893//################################################## 893//##################################################
894 clear_pending_ints(cs); 894 clear_pending_ints(cs);
895 bch_init(cs, 0); 895 bch_init(cs, 0);
896 bch_init(cs, 1); 896 bch_init(cs, 1);
897 dch_init(cs); 897 dch_init(cs);
898 } 898 }
899 if (part &2) { // reenable all interrupts and start chip 899 if (part & 2) { // reenable all interrupts and start chip
900 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK); 900 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
901 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK); 901 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
902 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK); 902 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
903 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register 903 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
904 904
905 // reset HDLC Transmitters/receivers 905 // reset HDLC Transmitters/receivers
906 cs->writeisac(cs, IPACX_CMDRD, 0x41); 906 cs->writeisac(cs, IPACX_CMDRD, 0x41);
907 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41); 907 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
908 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41); 908 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
909 ph_command(cs, IPACX_CMD_RES); 909 ph_command(cs, IPACX_CMD_RES);
@@ -911,4 +911,3 @@ init_ipacx(struct IsdnCardState *cs, int part)
911} 911}
912 912
913//----------------- end of file ----------------------- 913//----------------- end of file -----------------------
914
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 16:29:16 -0500