diff options
author | Hannes Eder <hannes@hanneseder.net> | 2008-12-13 00:20:03 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-12-13 00:20:03 -0500 |
commit | c31655fcf2c61f209aab8f4169b0e4afe49b581d (patch) | |
tree | f2b7c3a953f691817bf43575d6440573f94a698b /drivers/isdn/hardware | |
parent | c46f0a2d40f7ceb5fb696309bcd088ac75d0fe20 (diff) |
mISDN: hfcmulti: use __iomem address space modifier
Impact: make use of the __iomem address space modifier, and change u_char *,
u_short * and u_int * to void *
Fix more than 30 sparse warnings of this or similar type:
drivers/isdn/hardware/mISDN/hfcmulti.c:261:31: warning: incorrect type in argument 2 (different address spaces)
drivers/isdn/hardware/mISDN/hfcmulti.c:261:31: got unsigned char [usertype] *
drivers/isdn/hardware/mISDN/hfcmulti.c:261:31: expected void volatile [noderef] <asn:2>*addr
Signed-off-by: Hannes Eder <hannes@hanneseder.net>
Acked-by: Karsten Keil <kkeil@suse.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/isdn/hardware')
-rw-r--r-- | drivers/isdn/hardware/mISDN/hfc_multi.h | 4 | ||||
-rw-r--r-- | drivers/isdn/hardware/mISDN/hfcmulti.c | 44 |
2 files changed, 25 insertions, 23 deletions
diff --git a/drivers/isdn/hardware/mISDN/hfc_multi.h b/drivers/isdn/hardware/mISDN/hfc_multi.h index a33d87afc843..7bbf7300593d 100644 --- a/drivers/isdn/hardware/mISDN/hfc_multi.h +++ b/drivers/isdn/hardware/mISDN/hfc_multi.h | |||
@@ -162,8 +162,8 @@ struct hfc_multi { | |||
162 | void (*write_fifo)(struct hfc_multi *hc, u_char *data, | 162 | void (*write_fifo)(struct hfc_multi *hc, u_char *data, |
163 | int len); | 163 | int len); |
164 | u_long pci_origmembase, plx_origmembase, dsp_origmembase; | 164 | u_long pci_origmembase, plx_origmembase, dsp_origmembase; |
165 | u_char *pci_membase; /* PCI memory (MUST BE BYTE POINTER) */ | 165 | void __iomem *pci_membase; /* PCI memory */ |
166 | u_char *plx_membase; /* PLX memory */ | 166 | void __iomem *plx_membase; /* PLX memory */ |
167 | u_char *dsp_membase; /* DSP on PLX */ | 167 | u_char *dsp_membase; /* DSP on PLX */ |
168 | u_long pci_iobase; /* PCI IO */ | 168 | u_long pci_iobase; /* PCI IO */ |
169 | struct hfcm_hw hw; /* remember data of write-only-registers */ | 169 | struct hfcm_hw hw; /* remember data of write-only-registers */ |
diff --git a/drivers/isdn/hardware/mISDN/hfcmulti.c b/drivers/isdn/hardware/mISDN/hfcmulti.c index 0668072320dd..c63e2f49da8a 100644 --- a/drivers/isdn/hardware/mISDN/hfcmulti.c +++ b/drivers/isdn/hardware/mISDN/hfcmulti.c | |||
@@ -889,7 +889,8 @@ static inline void | |||
889 | hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) | 889 | hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) |
890 | { | 890 | { |
891 | struct hfc_multi *hc, *next, *pcmmaster = NULL; | 891 | struct hfc_multi *hc, *next, *pcmmaster = NULL; |
892 | u_int *plx_acc_32, pv; | 892 | void __iomem *plx_acc_32; |
893 | u_int pv; | ||
893 | u_long flags; | 894 | u_long flags; |
894 | 895 | ||
895 | spin_lock_irqsave(&HFClock, flags); | 896 | spin_lock_irqsave(&HFClock, flags); |
@@ -917,7 +918,7 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) | |||
917 | /* Disable sync of all cards */ | 918 | /* Disable sync of all cards */ |
918 | list_for_each_entry_safe(hc, next, &HFClist, list) { | 919 | list_for_each_entry_safe(hc, next, &HFClist, list) { |
919 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | 920 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { |
920 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 921 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
921 | pv = readl(plx_acc_32); | 922 | pv = readl(plx_acc_32); |
922 | pv &= ~PLX_SYNC_O_EN; | 923 | pv &= ~PLX_SYNC_O_EN; |
923 | writel(pv, plx_acc_32); | 924 | writel(pv, plx_acc_32); |
@@ -939,7 +940,7 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) | |||
939 | printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " | 940 | printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " |
940 | "interface.\n", hc->id, hc); | 941 | "interface.\n", hc->id, hc); |
941 | /* Enable new sync master */ | 942 | /* Enable new sync master */ |
942 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 943 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
943 | pv = readl(plx_acc_32); | 944 | pv = readl(plx_acc_32); |
944 | pv |= PLX_SYNC_O_EN; | 945 | pv |= PLX_SYNC_O_EN; |
945 | writel(pv, plx_acc_32); | 946 | writel(pv, plx_acc_32); |
@@ -969,7 +970,7 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) | |||
969 | "QUARTZ is automatically " | 970 | "QUARTZ is automatically " |
970 | "enabled by HFC-%dS\n", hc->type); | 971 | "enabled by HFC-%dS\n", hc->type); |
971 | } | 972 | } |
972 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 973 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
973 | pv = readl(plx_acc_32); | 974 | pv = readl(plx_acc_32); |
974 | pv |= PLX_SYNC_O_EN; | 975 | pv |= PLX_SYNC_O_EN; |
975 | writel(pv, plx_acc_32); | 976 | writel(pv, plx_acc_32); |
@@ -1014,7 +1015,8 @@ plxsd_checksync(struct hfc_multi *hc, int rm) | |||
1014 | static void | 1015 | static void |
1015 | release_io_hfcmulti(struct hfc_multi *hc) | 1016 | release_io_hfcmulti(struct hfc_multi *hc) |
1016 | { | 1017 | { |
1017 | u_int *plx_acc_32, pv; | 1018 | void __iomem *plx_acc_32; |
1019 | u_int pv; | ||
1018 | u_long plx_flags; | 1020 | u_long plx_flags; |
1019 | 1021 | ||
1020 | if (debug & DEBUG_HFCMULTI_INIT) | 1022 | if (debug & DEBUG_HFCMULTI_INIT) |
@@ -1034,7 +1036,7 @@ release_io_hfcmulti(struct hfc_multi *hc) | |||
1034 | printk(KERN_DEBUG "%s: release PLXSD card %d\n", | 1036 | printk(KERN_DEBUG "%s: release PLXSD card %d\n", |
1035 | __func__, hc->id + 1); | 1037 | __func__, hc->id + 1); |
1036 | spin_lock_irqsave(&plx_lock, plx_flags); | 1038 | spin_lock_irqsave(&plx_lock, plx_flags); |
1037 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 1039 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
1038 | writel(PLX_GPIOC_INIT, plx_acc_32); | 1040 | writel(PLX_GPIOC_INIT, plx_acc_32); |
1039 | pv = readl(plx_acc_32); | 1041 | pv = readl(plx_acc_32); |
1040 | /* Termination off */ | 1042 | /* Termination off */ |
@@ -1056,9 +1058,9 @@ release_io_hfcmulti(struct hfc_multi *hc) | |||
1056 | test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ | 1058 | test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ |
1057 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); | 1059 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); |
1058 | if (hc->pci_membase) | 1060 | if (hc->pci_membase) |
1059 | iounmap((void *)hc->pci_membase); | 1061 | iounmap(hc->pci_membase); |
1060 | if (hc->plx_membase) | 1062 | if (hc->plx_membase) |
1061 | iounmap((void *)hc->plx_membase); | 1063 | iounmap(hc->plx_membase); |
1062 | if (hc->pci_iobase) | 1064 | if (hc->pci_iobase) |
1063 | release_region(hc->pci_iobase, 8); | 1065 | release_region(hc->pci_iobase, 8); |
1064 | 1066 | ||
@@ -1081,7 +1083,8 @@ init_chip(struct hfc_multi *hc) | |||
1081 | u_long flags, val, val2 = 0, rev; | 1083 | u_long flags, val, val2 = 0, rev; |
1082 | int i, err = 0; | 1084 | int i, err = 0; |
1083 | u_char r_conf_en, rval; | 1085 | u_char r_conf_en, rval; |
1084 | u_int *plx_acc_32, pv; | 1086 | void __iomem *plx_acc_32; |
1087 | u_int pv; | ||
1085 | u_long plx_flags, hfc_flags; | 1088 | u_long plx_flags, hfc_flags; |
1086 | int plx_count; | 1089 | int plx_count; |
1087 | struct hfc_multi *pos, *next, *plx_last_hc; | 1090 | struct hfc_multi *pos, *next, *plx_last_hc; |
@@ -1155,7 +1158,7 @@ init_chip(struct hfc_multi *hc) | |||
1155 | printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", | 1158 | printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", |
1156 | __func__, hc->id + 1); | 1159 | __func__, hc->id + 1); |
1157 | spin_lock_irqsave(&plx_lock, plx_flags); | 1160 | spin_lock_irqsave(&plx_lock, plx_flags); |
1158 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 1161 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
1159 | writel(PLX_GPIOC_INIT, plx_acc_32); | 1162 | writel(PLX_GPIOC_INIT, plx_acc_32); |
1160 | pv = readl(plx_acc_32); | 1163 | pv = readl(plx_acc_32); |
1161 | /* The first and the last cards are terminating the PCM bus */ | 1164 | /* The first and the last cards are terminating the PCM bus */ |
@@ -1191,8 +1194,7 @@ init_chip(struct hfc_multi *hc) | |||
1191 | "we disable termination\n", | 1194 | "we disable termination\n", |
1192 | __func__, plx_last_hc->id + 1); | 1195 | __func__, plx_last_hc->id + 1); |
1193 | spin_lock_irqsave(&plx_lock, plx_flags); | 1196 | spin_lock_irqsave(&plx_lock, plx_flags); |
1194 | plx_acc_32 = (u_int *)(plx_last_hc->plx_membase | 1197 | plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC; |
1195 | + PLX_GPIOC); | ||
1196 | pv = readl(plx_acc_32); | 1198 | pv = readl(plx_acc_32); |
1197 | pv &= ~PLX_TERM_ON; | 1199 | pv &= ~PLX_TERM_ON; |
1198 | writel(pv, plx_acc_32); | 1200 | writel(pv, plx_acc_32); |
@@ -1241,7 +1243,7 @@ init_chip(struct hfc_multi *hc) | |||
1241 | /* Speech Design PLX bridge pcm and sync mode */ | 1243 | /* Speech Design PLX bridge pcm and sync mode */ |
1242 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | 1244 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { |
1243 | spin_lock_irqsave(&plx_lock, plx_flags); | 1245 | spin_lock_irqsave(&plx_lock, plx_flags); |
1244 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 1246 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
1245 | pv = readl(plx_acc_32); | 1247 | pv = readl(plx_acc_32); |
1246 | /* Connect PCM */ | 1248 | /* Connect PCM */ |
1247 | if (hc->hw.r_pcm_md0 & V_PCM_MD) { | 1249 | if (hc->hw.r_pcm_md0 & V_PCM_MD) { |
@@ -1353,8 +1355,7 @@ controller_fail: | |||
1353 | /* retry with master clock */ | 1355 | /* retry with master clock */ |
1354 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | 1356 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { |
1355 | spin_lock_irqsave(&plx_lock, plx_flags); | 1357 | spin_lock_irqsave(&plx_lock, plx_flags); |
1356 | plx_acc_32 = (u_int *)(hc->plx_membase + | 1358 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
1357 | PLX_GPIOC); | ||
1358 | pv = readl(plx_acc_32); | 1359 | pv = readl(plx_acc_32); |
1359 | pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; | 1360 | pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; |
1360 | pv |= PLX_SYNC_O_EN; | 1361 | pv |= PLX_SYNC_O_EN; |
@@ -1390,7 +1391,7 @@ controller_fail: | |||
1390 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) | 1391 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) |
1391 | plxsd_master = 1; | 1392 | plxsd_master = 1; |
1392 | spin_lock_irqsave(&plx_lock, plx_flags); | 1393 | spin_lock_irqsave(&plx_lock, plx_flags); |
1393 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | 1394 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
1394 | pv = readl(plx_acc_32); | 1395 | pv = readl(plx_acc_32); |
1395 | pv |= PLX_DSP_RES_N; | 1396 | pv |= PLX_DSP_RES_N; |
1396 | writel(pv, plx_acc_32); | 1397 | writel(pv, plx_acc_32); |
@@ -2587,7 +2588,8 @@ hfcmulti_interrupt(int intno, void *dev_id) | |||
2587 | struct dchannel *dch; | 2588 | struct dchannel *dch; |
2588 | u_char r_irq_statech, status, r_irq_misc, r_irq_oview; | 2589 | u_char r_irq_statech, status, r_irq_misc, r_irq_oview; |
2589 | int i; | 2590 | int i; |
2590 | u_short *plx_acc, wval; | 2591 | void __iomem *plx_acc; |
2592 | u_short wval; | ||
2591 | u_char e1_syncsta, temp; | 2593 | u_char e1_syncsta, temp; |
2592 | u_long flags; | 2594 | u_long flags; |
2593 | 2595 | ||
@@ -2607,7 +2609,7 @@ hfcmulti_interrupt(int intno, void *dev_id) | |||
2607 | 2609 | ||
2608 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | 2610 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { |
2609 | spin_lock_irqsave(&plx_lock, flags); | 2611 | spin_lock_irqsave(&plx_lock, flags); |
2610 | plx_acc = (u_short *)(hc->plx_membase + PLX_INTCSR); | 2612 | plx_acc = hc->plx_membase + PLX_INTCSR; |
2611 | wval = readw(plx_acc); | 2613 | wval = readw(plx_acc); |
2612 | spin_unlock_irqrestore(&plx_lock, flags); | 2614 | spin_unlock_irqrestore(&plx_lock, flags); |
2613 | if (!(wval & PLX_INTCSR_LINTI1_STATUS)) | 2615 | if (!(wval & PLX_INTCSR_LINTI1_STATUS)) |
@@ -4092,7 +4094,7 @@ init_card(struct hfc_multi *hc) | |||
4092 | { | 4094 | { |
4093 | int err = -EIO; | 4095 | int err = -EIO; |
4094 | u_long flags; | 4096 | u_long flags; |
4095 | u_short *plx_acc; | 4097 | void __iomem *plx_acc; |
4096 | u_long plx_flags; | 4098 | u_long plx_flags; |
4097 | 4099 | ||
4098 | if (debug & DEBUG_HFCMULTI_INIT) | 4100 | if (debug & DEBUG_HFCMULTI_INIT) |
@@ -4114,7 +4116,7 @@ init_card(struct hfc_multi *hc) | |||
4114 | 4116 | ||
4115 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | 4117 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { |
4116 | spin_lock_irqsave(&plx_lock, plx_flags); | 4118 | spin_lock_irqsave(&plx_lock, plx_flags); |
4117 | plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR); | 4119 | plx_acc = hc->plx_membase + PLX_INTCSR; |
4118 | writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), | 4120 | writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), |
4119 | plx_acc); /* enable PCI & LINT1 irq */ | 4121 | plx_acc); /* enable PCI & LINT1 irq */ |
4120 | spin_unlock_irqrestore(&plx_lock, plx_flags); | 4122 | spin_unlock_irqrestore(&plx_lock, plx_flags); |
@@ -4163,7 +4165,7 @@ init_card(struct hfc_multi *hc) | |||
4163 | error: | 4165 | error: |
4164 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | 4166 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { |
4165 | spin_lock_irqsave(&plx_lock, plx_flags); | 4167 | spin_lock_irqsave(&plx_lock, plx_flags); |
4166 | plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR); | 4168 | plx_acc = hc->plx_membase + PLX_INTCSR; |
4167 | writew(0x00, plx_acc); /*disable IRQs*/ | 4169 | writew(0x00, plx_acc); /*disable IRQs*/ |
4168 | spin_unlock_irqrestore(&plx_lock, plx_flags); | 4170 | spin_unlock_irqrestore(&plx_lock, plx_flags); |
4169 | } | 4171 | } |