irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed

There's no DMA at all, the device type memory attribute can ensure the
operations order and relaxed version imply compiler barrier, so we are safe
to use relaxed version to improve the performance a bit.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1415773374-4629-2-git-send-email-jszhang@marvell.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
index 31e231e1f566..fcc338584bda 100644
--- a/drivers/irqchip/irq-dw-apb-ictl.c
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -94,16 +94,16 @@ static int __init dw_apb_ictl_init(struct device_node *np,
          */
 
         /* mask and enable all interrupts */
-        writel(~0, iobase + APB_INT_MASK_L);
-        writel(~0, iobase + APB_INT_MASK_H);
-        writel(~0, iobase + APB_INT_ENABLE_L);
-        writel(~0, iobase + APB_INT_ENABLE_H);
+        writel_relaxed(~0, iobase + APB_INT_MASK_L);
+        writel_relaxed(~0, iobase + APB_INT_MASK_H);
+        writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
+        writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
 
-        reg = readl(iobase + APB_INT_ENABLE_H);
+        reg = readl_relaxed(iobase + APB_INT_ENABLE_H);
         if (reg)
                 nrirqs = 32 + fls(reg);
         else
-                nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+                nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
 
         domain = irq_domain_add_linear(np, nrirqs,
                                        &irq_generic_chip_ops, NULL);