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authorOlof Johansson <olof@lixom.net>2013-04-11 06:39:00 -0400
committerOlof Johansson <olof@lixom.net>2013-04-11 06:39:00 -0400
commitb9d5868e342a9802db7b299be511ac547ff1034d (patch)
tree49c8fe5467b817bcaf2afa6468c2e362f50e4770 /drivers/irqchip
parent83c15f4c05757b3c5fe1551a474458fd16d27bae (diff)
parentbc34b5f27cd33f4213bc5c8df0099dd11408d29d (diff)
Merge tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux into next/cleanup
From Maxime Ripard: Cleanups for Allwinner sunXi architecture: - Remove sunxi.dtsi - Switch to clocksource/irqchip device tree handlers - Cleanup the watchdog code * tag 'sunxi-cleanup-for-3.10' of git://github.com/mripard/linux: ARM: sunxi: Rework the restart code irqchip: sunxi: Rename sunxi to sun4i irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro clocksource: sunxi: Rename sunxi to sun4i clocksource: sunxi: make use of CLKSRC_OF clocksource: sunxi: Cleanup the timer code clocksource: make CLOCKSOURCE_OF_DECLARE type safe Signed-off-by: Olof Johansson <olof@lixom.net> Add/change conflict in drivers/clocksource/Makefile resolved.
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/Makefile2
-rw-r--r--drivers/irqchip/irq-sun4i.c149
-rw-r--r--drivers/irqchip/irq-sunxi.c151
3 files changed, 150 insertions, 152 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 9d8f4f1c6e39..d5e119ca9425 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -5,7 +5,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
5obj-$(CONFIG_ARCH_MXS) += irq-mxs.o 5obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
6obj-$(CONFIG_METAG) += irq-metag-ext.o 6obj-$(CONFIG_METAG) += irq-metag-ext.o
7obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o 7obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
8obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o 8obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
9obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 9obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
10obj-$(CONFIG_ARM_GIC) += irq-gic.o 10obj-$(CONFIG_ARM_GIC) += irq-gic.o
11obj-$(CONFIG_ARM_VIC) += irq-vic.o 11obj-$(CONFIG_ARM_VIC) += irq-vic.o
diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
new file mode 100644
index 000000000000..b66d4ae06898
--- /dev/null
+++ b/drivers/irqchip/irq-sun4i.c
@@ -0,0 +1,149 @@
1/*
2 * Allwinner A1X SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <asm/exception.h>
24#include <asm/mach/irq.h>
25
26#include "irqchip.h"
27
28#define SUN4I_IRQ_VECTOR_REG 0x00
29#define SUN4I_IRQ_PROTECTION_REG 0x08
30#define SUN4I_IRQ_NMI_CTRL_REG 0x0c
31#define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
32#define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
33#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
34#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
35
36static void __iomem *sun4i_irq_base;
37static struct irq_domain *sun4i_irq_domain;
38
39static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
40
41void sun4i_irq_ack(struct irq_data *irqd)
42{
43 unsigned int irq = irqd_to_hwirq(irqd);
44 unsigned int irq_off = irq % 32;
45 int reg = irq / 32;
46 u32 val;
47
48 val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
49 writel(val | (1 << irq_off),
50 sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
51}
52
53static void sun4i_irq_mask(struct irq_data *irqd)
54{
55 unsigned int irq = irqd_to_hwirq(irqd);
56 unsigned int irq_off = irq % 32;
57 int reg = irq / 32;
58 u32 val;
59
60 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
61 writel(val & ~(1 << irq_off),
62 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
63}
64
65static void sun4i_irq_unmask(struct irq_data *irqd)
66{
67 unsigned int irq = irqd_to_hwirq(irqd);
68 unsigned int irq_off = irq % 32;
69 int reg = irq / 32;
70 u32 val;
71
72 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
73 writel(val | (1 << irq_off),
74 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
75}
76
77static struct irq_chip sun4i_irq_chip = {
78 .name = "sun4i_irq",
79 .irq_ack = sun4i_irq_ack,
80 .irq_mask = sun4i_irq_mask,
81 .irq_unmask = sun4i_irq_unmask,
82};
83
84static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
85 irq_hw_number_t hw)
86{
87 irq_set_chip_and_handler(virq, &sun4i_irq_chip,
88 handle_level_irq);
89 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
90
91 return 0;
92}
93
94static struct irq_domain_ops sun4i_irq_ops = {
95 .map = sun4i_irq_map,
96 .xlate = irq_domain_xlate_onecell,
97};
98
99static int __init sun4i_of_init(struct device_node *node,
100 struct device_node *parent)
101{
102 sun4i_irq_base = of_iomap(node, 0);
103 if (!sun4i_irq_base)
104 panic("%s: unable to map IC registers\n",
105 node->full_name);
106
107 /* Disable all interrupts */
108 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
109 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
110 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
111
112 /* Mask all the interrupts */
113 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
114 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
115 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
116
117 /* Clear all the pending interrupts */
118 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
119 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
120 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
121
122 /* Enable protection mode */
123 writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
124
125 /* Configure the external interrupt source type */
126 writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
127
128 sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
129 &sun4i_irq_ops, NULL);
130 if (!sun4i_irq_domain)
131 panic("%s: unable to create IRQ domain\n", node->full_name);
132
133 set_handle_irq(sun4i_handle_irq);
134
135 return 0;
136}
137IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-ic", sun4i_of_init);
138
139static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
140{
141 u32 irq, hwirq;
142
143 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
144 while (hwirq != 0) {
145 irq = irq_find_mapping(sun4i_irq_domain, hwirq);
146 handle_IRQ(irq, regs);
147 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
148 }
149}
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
deleted file mode 100644
index 10974fa42653..000000000000
--- a/drivers/irqchip/irq-sunxi.c
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Allwinner A1X SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <linux/irqchip/sunxi.h>
24
25#define SUNXI_IRQ_VECTOR_REG 0x00
26#define SUNXI_IRQ_PROTECTION_REG 0x08
27#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
28#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
29#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
30#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
31#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
32
33static void __iomem *sunxi_irq_base;
34static struct irq_domain *sunxi_irq_domain;
35
36void sunxi_irq_ack(struct irq_data *irqd)
37{
38 unsigned int irq = irqd_to_hwirq(irqd);
39 unsigned int irq_off = irq % 32;
40 int reg = irq / 32;
41 u32 val;
42
43 val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
44 writel(val | (1 << irq_off),
45 sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
46}
47
48static void sunxi_irq_mask(struct irq_data *irqd)
49{
50 unsigned int irq = irqd_to_hwirq(irqd);
51 unsigned int irq_off = irq % 32;
52 int reg = irq / 32;
53 u32 val;
54
55 val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
56 writel(val & ~(1 << irq_off),
57 sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
58}
59
60static void sunxi_irq_unmask(struct irq_data *irqd)
61{
62 unsigned int irq = irqd_to_hwirq(irqd);
63 unsigned int irq_off = irq % 32;
64 int reg = irq / 32;
65 u32 val;
66
67 val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
68 writel(val | (1 << irq_off),
69 sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
70}
71
72static struct irq_chip sunxi_irq_chip = {
73 .name = "sunxi_irq",
74 .irq_ack = sunxi_irq_ack,
75 .irq_mask = sunxi_irq_mask,
76 .irq_unmask = sunxi_irq_unmask,
77};
78
79static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
80 irq_hw_number_t hw)
81{
82 irq_set_chip_and_handler(virq, &sunxi_irq_chip,
83 handle_level_irq);
84 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
85
86 return 0;
87}
88
89static struct irq_domain_ops sunxi_irq_ops = {
90 .map = sunxi_irq_map,
91 .xlate = irq_domain_xlate_onecell,
92};
93
94static int __init sunxi_of_init(struct device_node *node,
95 struct device_node *parent)
96{
97 sunxi_irq_base = of_iomap(node, 0);
98 if (!sunxi_irq_base)
99 panic("%s: unable to map IC registers\n",
100 node->full_name);
101
102 /* Disable all interrupts */
103 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
104 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
105 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
106
107 /* Mask all the interrupts */
108 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
109 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
110 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
111
112 /* Clear all the pending interrupts */
113 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
114 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
115 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
116
117 /* Enable protection mode */
118 writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
119
120 /* Configure the external interrupt source type */
121 writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
122
123 sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
124 &sunxi_irq_ops, NULL);
125 if (!sunxi_irq_domain)
126 panic("%s: unable to create IRQ domain\n", node->full_name);
127
128 return 0;
129}
130
131static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
132 { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init },
133 { }
134};
135
136void __init sunxi_init_irq(void)
137{
138 of_irq_init(sunxi_irq_dt_ids);
139}
140
141asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
142{
143 u32 irq, hwirq;
144
145 hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
146 while (hwirq != 0) {
147 irq = irq_find_mapping(sunxi_irq_domain, hwirq);
148 handle_IRQ(irq, regs);
149 hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
150 }
151}
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