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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:49:36 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:49:36 -0500
commit0ba3307a8ec35252f7b1e222e32889a6f3d9ceb3 (patch)
tree26126ed7a2080a706f0488c215549fc9f5f76a59 /drivers/irqchip
parent903a9f77d1d00c8621bc37afd959ac45a4b3ebec (diff)
parentcd2f43a1f7400a74a084094502f70df2e169c6e8 (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM driver updates from Olof Johansson: "Updates of SoC-near drivers and other driver updates that makes more sense to take through our tree. The largest part of this is a conversion of device registration for some renesas shmobile/sh devices over to use resources. This has required coordination with the corresponding arch/sh changes, and we've agreed to merge the arch/sh changes through our tree. Added in this branch is support for Trusted Foundations secure firmware, which is what is used on many of the commercial Nvidia Tegra products that are in the market, including the Nvidia Shield. The code is local to arch/arm at this time since it's uncertain whether it will be shared with arm64 longer-term, if needed we will refactor later. A couple of new RTC drivers used on ARM boards, merged through our tree on request by the RTC maintainer. ... plus a bunch of smaller updates across the board, gpio conversions for davinci, etc" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits) watchdog: davinci: rename platform driver to davinci-wdt tty: serial: Limit msm_serial_hs driver to platforms that use it mmc: msm_sdcc: Limit driver to platforms that use it usb: phy: msm: Move mach dependent code to platform data clk: versatile: fixup IM-PD1 clock implementation clk: versatile: pass a name to ICST clock provider ARM: integrator: pass parent IRQ to the SIC irqchip: versatile FPGA: support cascaded interrupts from DT gpio: davinci: don't create irq_domain in case of unbanked irqs gpio: davinci: use chained_irq_enter/chained_irq_exit API gpio: davinci: add OF support gpio: davinci: remove unused variable intc_irq_num gpio: davinci: convert to use irqdomain support. gpio: introduce GPIO_DAVINCI kconfig option gpio: davinci: get rid of DAVINCI_N_GPIO gpio: davinci: use {readl|writel}_relaxed() instead of __raw_* serial: sh-sci: Add OF support serial: sh-sci: Add device tree bindings documentation serial: sh-sci: Remove platform data mapbase and irqs fields serial: sh-sci: Remove platform data scbrr_algo_id field ...
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/exynos-combiner.c15
-rw-r--r--drivers/irqchip/irq-renesas-irqc.c21
-rw-r--r--drivers/irqchip/irq-versatile-fpga.c15
3 files changed, 24 insertions, 27 deletions
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 868ed40cb6bf..40e6440348ff 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -171,8 +171,7 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
171 171
172static void __init combiner_init(void __iomem *combiner_base, 172static void __init combiner_init(void __iomem *combiner_base,
173 struct device_node *np, 173 struct device_node *np,
174 unsigned int max_nr, 174 unsigned int max_nr)
175 int irq_base)
176{ 175{
177 int i, irq; 176 int i, irq;
178 unsigned int nr_irq; 177 unsigned int nr_irq;
@@ -186,7 +185,7 @@ static void __init combiner_init(void __iomem *combiner_base,
186 return; 185 return;
187 } 186 }
188 187
189 combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base, 188 combiner_irq_domain = irq_domain_add_linear(np, nr_irq,
190 &combiner_irq_domain_ops, combiner_data); 189 &combiner_irq_domain_ops, combiner_data);
191 if (WARN_ON(!combiner_irq_domain)) { 190 if (WARN_ON(!combiner_irq_domain)) {
192 pr_warning("%s: irq domain init failed\n", __func__); 191 pr_warning("%s: irq domain init failed\n", __func__);
@@ -207,7 +206,6 @@ static int __init combiner_of_init(struct device_node *np,
207{ 206{
208 void __iomem *combiner_base; 207 void __iomem *combiner_base;
209 unsigned int max_nr = 20; 208 unsigned int max_nr = 20;
210 int irq_base = -1;
211 209
212 combiner_base = of_iomap(np, 0); 210 combiner_base = of_iomap(np, 0);
213 if (!combiner_base) { 211 if (!combiner_base) {
@@ -221,14 +219,7 @@ static int __init combiner_of_init(struct device_node *np,
221 __func__, max_nr); 219 __func__, max_nr);
222 } 220 }
223 221
224 /* 222 combiner_init(combiner_base, np, max_nr);
225 * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
226 * get their IRQ from DT, remove this in order to get dynamic
227 * allocation.
228 */
229 irq_base = 160;
230
231 combiner_init(combiner_base, np, max_nr, irq_base);
232 223
233 return 0; 224 return 0;
234} 225}
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
index 2f404ba61c6c..8777065012a5 100644
--- a/drivers/irqchip/irq-renesas-irqc.c
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -81,15 +81,12 @@ static void irqc_irq_disable(struct irq_data *d)
81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); 81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
82} 82}
83 83
84#define INTC_IRQ_SENSE_VALID 0x10
85#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
86
87static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { 84static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
88 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), 85 [IRQ_TYPE_LEVEL_LOW] = 0x01,
89 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), 86 [IRQ_TYPE_LEVEL_HIGH] = 0x02,
90 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ 87 [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
91 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ 88 [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
92 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ 89 [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
93}; 90};
94 91
95static int irqc_irq_set_type(struct irq_data *d, unsigned int type) 92static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
@@ -101,12 +98,12 @@ static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
101 98
102 irqc_dbg(&p->irq[hw_irq], "sense"); 99 irqc_dbg(&p->irq[hw_irq], "sense");
103 100
104 if (!(value & INTC_IRQ_SENSE_VALID)) 101 if (!value)
105 return -EINVAL; 102 return -EINVAL;
106 103
107 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); 104 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
108 tmp &= ~0x3f; 105 tmp &= ~0x3f;
109 tmp |= value ^ INTC_IRQ_SENSE_VALID; 106 tmp |= value;
110 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); 107 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
111 return 0; 108 return 0;
112} 109}
@@ -212,10 +209,8 @@ static int irqc_probe(struct platform_device *pdev)
212 irq_chip->name = name; 209 irq_chip->name = name;
213 irq_chip->irq_mask = irqc_irq_disable; 210 irq_chip->irq_mask = irqc_irq_disable;
214 irq_chip->irq_unmask = irqc_irq_enable; 211 irq_chip->irq_unmask = irqc_irq_enable;
215 irq_chip->irq_enable = irqc_irq_enable;
216 irq_chip->irq_disable = irqc_irq_disable;
217 irq_chip->irq_set_type = irqc_irq_set_type; 212 irq_chip->irq_set_type = irqc_irq_set_type;
218 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 213 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
219 214
220 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 215 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
221 p->number_of_irqs, 216 p->number_of_irqs,
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
index 47a52ab580d8..3ae2bb8d9cf2 100644
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -9,6 +9,7 @@
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/of.h> 10#include <linux/of.h>
11#include <linux/of_address.h> 11#include <linux/of_address.h>
12#include <linux/of_irq.h>
12 13
13#include <asm/exception.h> 14#include <asm/exception.h>
14#include <asm/mach/irq.h> 15#include <asm/mach/irq.h>
@@ -167,8 +168,12 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
167 f->used_irqs++; 168 f->used_irqs++;
168 } 169 }
169 170
170 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n", 171 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
171 fpga_irq_id, name, base, f->used_irqs); 172 fpga_irq_id, name, base, f->used_irqs);
173 if (parent_irq != -1)
174 pr_cont(", parent IRQ: %d\n", parent_irq);
175 else
176 pr_cont("\n");
172 177
173 fpga_irq_id++; 178 fpga_irq_id++;
174} 179}
@@ -180,6 +185,7 @@ int __init fpga_irq_of_init(struct device_node *node,
180 void __iomem *base; 185 void __iomem *base;
181 u32 clear_mask; 186 u32 clear_mask;
182 u32 valid_mask; 187 u32 valid_mask;
188 int parent_irq;
183 189
184 if (WARN_ON(!node)) 190 if (WARN_ON(!node))
185 return -ENODEV; 191 return -ENODEV;
@@ -193,7 +199,12 @@ int __init fpga_irq_of_init(struct device_node *node,
193 if (of_property_read_u32(node, "valid-mask", &valid_mask)) 199 if (of_property_read_u32(node, "valid-mask", &valid_mask))
194 valid_mask = 0; 200 valid_mask = 0;
195 201
196 fpga_irq_init(base, node->name, 0, -1, valid_mask, node); 202 /* Some chips are cascaded from a parent IRQ */
203 parent_irq = irq_of_parse_and_map(node, 0);
204 if (!parent_irq)
205 parent_irq = -1;
206
207 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
197 208
198 writel(clear_mask, base + IRQ_ENABLE_CLEAR); 209 writel(clear_mask, base + IRQ_ENABLE_CLEAR);
199 writel(clear_mask, base + FIQ_ENABLE_CLEAR); 210 writel(clear_mask, base + FIQ_ENABLE_CLEAR);