irqchip: mips-gic: Add new functions to start/stop the GIC counter

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: <linux-kernel@vger.kernel.org>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Link: https://lkml.kernel.org/r/1427113923-9840-2-git-send-email-markos.chandras@imgtec.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 21 insertions, 0 deletions

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9acdc080e7ec..f2d269bca789 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -166,6 +166,27 @@ cycle_t gic_read_compare(void)
 
         return (((cycle_t) hi) << 32) + lo;
 }
+
+void gic_start_count(void)
+{
+        u32 gicconfig;
+
+        /* Start the counter */
+        gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+        gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
+        gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
+void gic_stop_count(void)
+{
+        u32 gicconfig;
+
+        /* Stop the counter */
+        gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
+        gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
+        gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
+}
+
 #endif
 
 static bool gic_local_irq_is_routable(int intr)