iommu/amd: Setup PPR log when supported by IOMMU

Allocate and enable a log buffer for peripheral page faults
when the IOMMU supports this feature.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

2 files changed, 65 insertions, 0 deletions

diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index fb4afd6d357d..60716cefa7af 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -583,6 +583,46 @@ static void __init free_event_buffer(struct amd_iommu *iommu)
         free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
 }
 
+/* allocates the memory where the IOMMU will log its events to */
+static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
+{
+        iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
+                                                get_order(PPR_LOG_SIZE));
+
+        if (iommu->ppr_log == NULL)
+                return NULL;
+
+        return iommu->ppr_log;
+}
+
+static void iommu_enable_ppr_log(struct amd_iommu *iommu)
+{
+        u64 entry;
+
+        if (iommu->ppr_log == NULL)
+                return;
+
+        entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
+
+        memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
+                    &entry, sizeof(entry));
+
+        /* set head and tail to zero manually */
+        writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
+        writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
+
+        iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
+        iommu_feature_enable(iommu, CONTROL_PPR_EN);
+}
+
+static void __init free_ppr_log(struct amd_iommu *iommu)
+{
+        if (iommu->ppr_log == NULL)
+                return;
+
+        free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
+}
+
 /* sets a specific bit in the device table entry. */
 static void set_dev_entry_bit(u16 devid, u8 bit)
 {
@@ -914,6 +954,7 @@ static void __init free_iommu_one(struct amd_iommu *iommu)
 {
         free_command_buffer(iommu);
         free_event_buffer(iommu);
+        free_ppr_log(iommu);
         iommu_unmap_mmio_space(iommu);
 }
 
@@ -977,6 +1018,12 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
         init_iommu_from_acpi(iommu, h);
         init_iommu_devices(iommu);
 
+        if (iommu_feature(iommu, FEATURE_PPR)) {
+                iommu->ppr_log = alloc_ppr_log(iommu);
+                if (!iommu->ppr_log)
+                        return -ENOMEM;
+        }
+
         if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
                 amd_iommu_np_cache = true;
 
@@ -1063,6 +1110,9 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
         iommu->int_enabled = true;
         iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
 
+        if (iommu->ppr_log != NULL)
+                iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
+
         return 0;
 }
 
@@ -1287,6 +1337,7 @@ static void enable_iommus(void)
                 iommu_set_device_table(iommu);
                 iommu_enable_command_buffer(iommu);
                 iommu_enable_event_buffer(iommu);
+                iommu_enable_ppr_log(iommu);
                 iommu_set_exclusion_range(iommu);
                 iommu_init_msi(iommu);
                 iommu_enable(iommu);
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 0d984ca925be..4dc230904fe9 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -69,11 +69,14 @@
 #define MMIO_EXCL_BASE_OFFSET   0x0020
 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
 #define MMIO_EXT_FEATURES       0x0030
+#define MMIO_PPR_LOG_OFFSET     0x0038
 #define MMIO_CMD_HEAD_OFFSET    0x2000
 #define MMIO_CMD_TAIL_OFFSET    0x2008
 #define MMIO_EVT_HEAD_OFFSET    0x2010
 #define MMIO_EVT_TAIL_OFFSET    0x2018
 #define MMIO_STATUS_OFFSET      0x2020
+#define MMIO_PPR_HEAD_OFFSET    0x2030
+#define MMIO_PPR_TAIL_OFFSET    0x2038
 
 
 /* Extended Feature Bits */
@@ -125,6 +128,7 @@
 #define CONTROL_CMDBUF_EN       0x0cULL
 #define CONTROL_PPFLOG_EN       0x0dULL
 #define CONTROL_PPFINT_EN       0x0eULL
+#define CONTROL_PPR_EN          0x0fULL
 
 /* command specific defines */
 #define CMD_COMPL_WAIT          0x01
@@ -168,6 +172,13 @@
 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 #define EVT_LEN_MASK            (0x9ULL << 56)
 
+/* Constants for PPR Log handling */
+#define PPR_LOG_ENTRIES         512
+#define PPR_LOG_SIZE_SHIFT      56
+#define PPR_LOG_SIZE_512        (0x9ULL << PPR_LOG_SIZE_SHIFT)
+#define PPR_ENTRY_SIZE          16
+#define PPR_LOG_SIZE            (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
+
 #define PAGE_MODE_NONE    0x00
 #define PAGE_MODE_1_LEVEL 0x01
 #define PAGE_MODE_2_LEVEL 0x02
@@ -434,6 +445,9 @@ struct amd_iommu {
         /* MSI number for event interrupt */
         u16 evt_msi_num;
 
+        /* Base of the PPR log, if present */
+        u8 *ppr_log;
+
         /* true if interrupts for this IOMMU are already enabled */
         bool int_enabled;