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authorWill Deacon <will.deacon@arm.com>2013-11-05 11:32:00 -0500
committerWill Deacon <will.deacon@arm.com>2013-12-16 14:30:32 -0500
commitcf2d45b19ddb361241f36d8c9f3d0b234a18459b (patch)
tree3ba3e912a2b32f0c168f6b464ad8739eccc735b5 /drivers/iommu
parentca13bb3d4e54f5c30089e55d5b8f4bb80c8f05e2 (diff)
iommu/arm-smmu: add support for IOMMU_EXEC
Previously, all of our mappings were marked as executable, which isn't usually required. Now that we have the IOMMU_EXEC flag, use that to determine whether or not a mapping should be marked as executable. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/arm-smmu.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index fa3371adea4f..8911850c9444 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -61,12 +61,13 @@
61#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) 61#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
62 62
63/* Page table bits */ 63/* Page table bits */
64#define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) 64#define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
65#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) 65#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
66#define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) 66#define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
67#define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) 67#define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
68#define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) 68#define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
69#define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) 69#define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
70#define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
70 71
71#if PAGE_SIZE == SZ_4K 72#if PAGE_SIZE == SZ_4K
72#define ARM_SMMU_PTE_CONT_ENTRIES 16 73#define ARM_SMMU_PTE_CONT_ENTRIES 16
@@ -1205,7 +1206,7 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1205 unsigned long pfn, int flags, int stage) 1206 unsigned long pfn, int flags, int stage)
1206{ 1207{
1207 pte_t *pte, *start; 1208 pte_t *pte, *start;
1208 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF; 1209 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1209 1210
1210 if (pmd_none(*pmd)) { 1211 if (pmd_none(*pmd)) {
1211 /* Allocate a new set of tables */ 1212 /* Allocate a new set of tables */
@@ -1244,7 +1245,9 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1244 } 1245 }
1245 1246
1246 /* If no access, create a faulting entry to avoid TLB fills */ 1247 /* If no access, create a faulting entry to avoid TLB fills */
1247 if (!(flags & (IOMMU_READ | IOMMU_WRITE))) 1248 if (flags & IOMMU_EXEC)
1249 pteval &= ~ARM_SMMU_PTE_XN;
1250 else if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
1248 pteval &= ~ARM_SMMU_PTE_PAGE; 1251 pteval &= ~ARM_SMMU_PTE_PAGE;
1249 1252
1250 pteval |= ARM_SMMU_PTE_SH_IS; 1253 pteval |= ARM_SMMU_PTE_SH_IS;