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authorArnd Bergmann <arnd@arndb.de>2015-01-30 16:55:55 -0500
committerJoerg Roedel <jroedel@suse.de>2015-02-03 12:53:27 -0500
commita4188beee59763b3507939968677776561adbba5 (patch)
tree1050db4e7ed8898fa6b23fd9e0ee01834201377e /drivers/iommu
parent16753322983bcca0eca6d81f20d23277df0d6cf7 (diff)
iommu/arm-smmu: Avoid build warning
ARM allmodconfig gained a new warning when dma_addr_t is 32-bit wide: drivers/iommu/arm-smmu.c: In function 'arm_smmu_iova_to_phys_hard': drivers/iommu/arm-smmu.c:1255:3: warning: right shift count >= width of type This changes the calculation so that the effective type is always 64-bit. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 859a732e4f713 ("iommu/arm-smmu: add support for iova_to_phys through ATS1PR") Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/arm-smmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 1d6d43bb3395..fc13dd56953e 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1252,7 +1252,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1252 } else { 1252 } else {
1253 u32 reg = iova & ~0xfff; 1253 u32 reg = iova & ~0xfff;
1254 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); 1254 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
1255 reg = (iova & ~0xfff) >> 32; 1255 reg = ((u64)iova & ~0xfff) >> 32;
1256 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI); 1256 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
1257 } 1257 }
1258 1258