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authorWill Deacon <will.deacon@arm.com>2015-03-04 07:21:03 -0500
committerWill Deacon <will.deacon@arm.com>2015-03-27 09:39:35 -0400
commit4a1c93cbe9b2cf559fee3316ee287bb042eb1aba (patch)
tree914e6a32d939e96d3bd19e7a45ea9ade264058a5 /drivers/iommu
parent06e5801b8cb3fc057d88cb4dc03c0b64b2744cda (diff)
iommu/arm-smmu: ensure CBA2R is initialised before CBAR on SMMUv2
The VMID16 (8.1) extension to SMMUv2 added a 16-bit VMID16 field to the CBA2R registers. Unfortunately, if software writes this field as zero after setting an 8-bit VMID in a stage-2 CBAR, then the VMID may also be overwritten with zero on some early implementations (the architecture was later updated to fix this issue). This patch ensures that we initialise CBA2R before CBAR, therefore ensuring that the VMID is set correctly. Tested-by: Manish Jaggi <mjaggi@caviumnetworks.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/arm-smmu.c24
1 files changed, 14 insertions, 10 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index fc13dd56953e..4abb831e24f0 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -730,6 +730,20 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
730 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; 730 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
731 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); 731 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
732 732
733 if (smmu->version > ARM_SMMU_V1) {
734 /*
735 * CBA2R.
736 * *Must* be initialised before CBAR thanks to VMID16
737 * architectural oversight affected some implementations.
738 */
739#ifdef CONFIG_64BIT
740 reg = CBA2R_RW64_64BIT;
741#else
742 reg = CBA2R_RW64_32BIT;
743#endif
744 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
745 }
746
733 /* CBAR */ 747 /* CBAR */
734 reg = cfg->cbar; 748 reg = cfg->cbar;
735 if (smmu->version == ARM_SMMU_V1) 749 if (smmu->version == ARM_SMMU_V1)
@@ -747,16 +761,6 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
747 } 761 }
748 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); 762 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
749 763
750 if (smmu->version > ARM_SMMU_V1) {
751 /* CBA2R */
752#ifdef CONFIG_64BIT
753 reg = CBA2R_RW64_64BIT;
754#else
755 reg = CBA2R_RW64_32BIT;
756#endif
757 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
758 }
759
760 /* TTBRs */ 764 /* TTBRs */
761 if (stage1) { 765 if (stage1) {
762 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; 766 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];