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authorJoerg Roedel <joro@8bytes.org>2013-04-09 09:39:16 -0400
committerJoerg Roedel <joro@8bytes.org>2013-04-18 11:21:15 -0400
commit0dfedd619442f3a64de4fcd8a735664d18e86ee7 (patch)
treef3011635ab3b05be998e77cc19f60717e2976bbe /drivers/iommu
parenta0e191b23d93464bf8726eba8da081d23c08e185 (diff)
iommu/amd: Use AMD specific data structure for irq remapping
For compatibility reasons the irq remapping code for the AMD IOMMU used the same per-irq data structure as the Intel implementation. Now that support for the AMD specific data structure is upstream we can use this one instead. Reviewed-by: Shuah Khan <shuahkhan@gmail.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/amd_iommu.c54
1 files changed, 27 insertions, 27 deletions
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 93b18746d711..b05599dd2c43 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -3990,7 +3990,7 @@ static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3990 c = 0; 3990 c = 0;
3991 3991
3992 if (c == count) { 3992 if (c == count) {
3993 struct irq_2_iommu *irte_info; 3993 struct irq_2_irte *irte_info;
3994 3994
3995 for (; c != 0; --c) 3995 for (; c != 0; --c)
3996 table->table[index - c + 1] = IRTE_ALLOCATED; 3996 table->table[index - c + 1] = IRTE_ALLOCATED;
@@ -3998,9 +3998,9 @@ static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3998 index -= count - 1; 3998 index -= count - 1;
3999 3999
4000 cfg->remapped = 1; 4000 cfg->remapped = 1;
4001 irte_info = &cfg->irq_2_iommu; 4001 irte_info = &cfg->irq_2_irte;
4002 irte_info->sub_handle = devid; 4002 irte_info->devid = devid;
4003 irte_info->irte_index = index; 4003 irte_info->index = index;
4004 4004
4005 goto out; 4005 goto out;
4006 } 4006 }
@@ -4081,7 +4081,7 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4081 struct io_apic_irq_attr *attr) 4081 struct io_apic_irq_attr *attr)
4082{ 4082{
4083 struct irq_remap_table *table; 4083 struct irq_remap_table *table;
4084 struct irq_2_iommu *irte_info; 4084 struct irq_2_irte *irte_info;
4085 struct irq_cfg *cfg; 4085 struct irq_cfg *cfg;
4086 union irte irte; 4086 union irte irte;
4087 int ioapic_id; 4087 int ioapic_id;
@@ -4093,7 +4093,7 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4093 if (!cfg) 4093 if (!cfg)
4094 return -EINVAL; 4094 return -EINVAL;
4095 4095
4096 irte_info = &cfg->irq_2_iommu; 4096 irte_info = &cfg->irq_2_irte;
4097 ioapic_id = mpc_ioapic_id(attr->ioapic); 4097 ioapic_id = mpc_ioapic_id(attr->ioapic);
4098 devid = get_ioapic_devid(ioapic_id); 4098 devid = get_ioapic_devid(ioapic_id);
4099 4099
@@ -4108,8 +4108,8 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4108 4108
4109 /* Setup IRQ remapping info */ 4109 /* Setup IRQ remapping info */
4110 cfg->remapped = 1; 4110 cfg->remapped = 1;
4111 irte_info->sub_handle = devid; 4111 irte_info->devid = devid;
4112 irte_info->irte_index = index; 4112 irte_info->index = index;
4113 4113
4114 /* Setup IRTE for IOMMU */ 4114 /* Setup IRTE for IOMMU */
4115 irte.val = 0; 4115 irte.val = 0;
@@ -4143,7 +4143,7 @@ static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4143static int set_affinity(struct irq_data *data, const struct cpumask *mask, 4143static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4144 bool force) 4144 bool force)
4145{ 4145{
4146 struct irq_2_iommu *irte_info; 4146 struct irq_2_irte *irte_info;
4147 unsigned int dest, irq; 4147 unsigned int dest, irq;
4148 struct irq_cfg *cfg; 4148 struct irq_cfg *cfg;
4149 union irte irte; 4149 union irte irte;
@@ -4154,12 +4154,12 @@ static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4154 4154
4155 cfg = data->chip_data; 4155 cfg = data->chip_data;
4156 irq = data->irq; 4156 irq = data->irq;
4157 irte_info = &cfg->irq_2_iommu; 4157 irte_info = &cfg->irq_2_irte;
4158 4158
4159 if (!cpumask_intersects(mask, cpu_online_mask)) 4159 if (!cpumask_intersects(mask, cpu_online_mask))
4160 return -EINVAL; 4160 return -EINVAL;
4161 4161
4162 if (get_irte(irte_info->sub_handle, irte_info->irte_index, &irte)) 4162 if (get_irte(irte_info->devid, irte_info->index, &irte))
4163 return -EBUSY; 4163 return -EBUSY;
4164 4164
4165 if (assign_irq_vector(irq, cfg, mask)) 4165 if (assign_irq_vector(irq, cfg, mask))
@@ -4175,7 +4175,7 @@ static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4175 irte.fields.vector = cfg->vector; 4175 irte.fields.vector = cfg->vector;
4176 irte.fields.destination = dest; 4176 irte.fields.destination = dest;
4177 4177
4178 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte); 4178 modify_irte(irte_info->devid, irte_info->index, irte);
4179 4179
4180 if (cfg->move_in_progress) 4180 if (cfg->move_in_progress)
4181 send_cleanup_vector(cfg); 4181 send_cleanup_vector(cfg);
@@ -4187,16 +4187,16 @@ static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4187 4187
4188static int free_irq(int irq) 4188static int free_irq(int irq)
4189{ 4189{
4190 struct irq_2_iommu *irte_info; 4190 struct irq_2_irte *irte_info;
4191 struct irq_cfg *cfg; 4191 struct irq_cfg *cfg;
4192 4192
4193 cfg = irq_get_chip_data(irq); 4193 cfg = irq_get_chip_data(irq);
4194 if (!cfg) 4194 if (!cfg)
4195 return -EINVAL; 4195 return -EINVAL;
4196 4196
4197 irte_info = &cfg->irq_2_iommu; 4197 irte_info = &cfg->irq_2_irte;
4198 4198
4199 free_irte(irte_info->sub_handle, irte_info->irte_index); 4199 free_irte(irte_info->devid, irte_info->index);
4200 4200
4201 return 0; 4201 return 0;
4202} 4202}
@@ -4205,7 +4205,7 @@ static void compose_msi_msg(struct pci_dev *pdev,
4205 unsigned int irq, unsigned int dest, 4205 unsigned int irq, unsigned int dest,
4206 struct msi_msg *msg, u8 hpet_id) 4206 struct msi_msg *msg, u8 hpet_id)
4207{ 4207{
4208 struct irq_2_iommu *irte_info; 4208 struct irq_2_irte *irte_info;
4209 struct irq_cfg *cfg; 4209 struct irq_cfg *cfg;
4210 union irte irte; 4210 union irte irte;
4211 4211
@@ -4213,7 +4213,7 @@ static void compose_msi_msg(struct pci_dev *pdev,
4213 if (!cfg) 4213 if (!cfg)
4214 return; 4214 return;
4215 4215
4216 irte_info = &cfg->irq_2_iommu; 4216 irte_info = &cfg->irq_2_irte;
4217 4217
4218 irte.val = 0; 4218 irte.val = 0;
4219 irte.fields.vector = cfg->vector; 4219 irte.fields.vector = cfg->vector;
@@ -4222,11 +4222,11 @@ static void compose_msi_msg(struct pci_dev *pdev,
4222 irte.fields.dm = apic->irq_dest_mode; 4222 irte.fields.dm = apic->irq_dest_mode;
4223 irte.fields.valid = 1; 4223 irte.fields.valid = 1;
4224 4224
4225 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte); 4225 modify_irte(irte_info->devid, irte_info->index, irte);
4226 4226
4227 msg->address_hi = MSI_ADDR_BASE_HI; 4227 msg->address_hi = MSI_ADDR_BASE_HI;
4228 msg->address_lo = MSI_ADDR_BASE_LO; 4228 msg->address_lo = MSI_ADDR_BASE_LO;
4229 msg->data = irte_info->irte_index; 4229 msg->data = irte_info->index;
4230} 4230}
4231 4231
4232static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) 4232static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
@@ -4251,7 +4251,7 @@ static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4251static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, 4251static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4252 int index, int offset) 4252 int index, int offset)
4253{ 4253{
4254 struct irq_2_iommu *irte_info; 4254 struct irq_2_irte *irte_info;
4255 struct irq_cfg *cfg; 4255 struct irq_cfg *cfg;
4256 u16 devid; 4256 u16 devid;
4257 4257
@@ -4266,18 +4266,18 @@ static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4266 return 0; 4266 return 0;
4267 4267
4268 devid = get_device_id(&pdev->dev); 4268 devid = get_device_id(&pdev->dev);
4269 irte_info = &cfg->irq_2_iommu; 4269 irte_info = &cfg->irq_2_irte;
4270 4270
4271 cfg->remapped = 1; 4271 cfg->remapped = 1;
4272 irte_info->sub_handle = devid; 4272 irte_info->devid = devid;
4273 irte_info->irte_index = index + offset; 4273 irte_info->index = index + offset;
4274 4274
4275 return 0; 4275 return 0;
4276} 4276}
4277 4277
4278static int setup_hpet_msi(unsigned int irq, unsigned int id) 4278static int setup_hpet_msi(unsigned int irq, unsigned int id)
4279{ 4279{
4280 struct irq_2_iommu *irte_info; 4280 struct irq_2_irte *irte_info;
4281 struct irq_cfg *cfg; 4281 struct irq_cfg *cfg;
4282 int index, devid; 4282 int index, devid;
4283 4283
@@ -4285,7 +4285,7 @@ static int setup_hpet_msi(unsigned int irq, unsigned int id)
4285 if (!cfg) 4285 if (!cfg)
4286 return -EINVAL; 4286 return -EINVAL;
4287 4287
4288 irte_info = &cfg->irq_2_iommu; 4288 irte_info = &cfg->irq_2_irte;
4289 devid = get_hpet_devid(id); 4289 devid = get_hpet_devid(id);
4290 if (devid < 0) 4290 if (devid < 0)
4291 return devid; 4291 return devid;
@@ -4295,8 +4295,8 @@ static int setup_hpet_msi(unsigned int irq, unsigned int id)
4295 return index; 4295 return index;
4296 4296
4297 cfg->remapped = 1; 4297 cfg->remapped = 1;
4298 irte_info->sub_handle = devid; 4298 irte_info->devid = devid;
4299 irte_info->irte_index = index; 4299 irte_info->index = index;
4300 4300
4301 return 0; 4301 return 0;
4302} 4302}