diff options
author | Stephen Warren <swarren@nvidia.com> | 2012-09-04 18:36:15 -0400 |
---|---|---|
committer | Joerg Roedel <joerg.roedel@amd.com> | 2012-09-18 06:40:57 -0400 |
commit | e6bc59330e34626082a6b2e4733802e372781c8d (patch) | |
tree | 75c6c73bb719a3e117900550ddd36e5532830084 /drivers/iommu | |
parent | 5a2c937a8be8c9c5a6d23308b5ee841b6394a1cf (diff) |
dma: tegra: move smmu.h into SMMU driver
There's no need to place these defines into arch/arm/mach-tegra/include/.
Move them into the SMMU driver to clean up mach-tegra, as a pre-requisite
for single-zImage.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: Hiroshi Doyu <hdoyu@nvidia.com>
Acked-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r-- | drivers/iommu/tegra-smmu.c | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 7e42c71c1ffc..e1d17feb52b8 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c | |||
@@ -39,9 +39,48 @@ | |||
39 | #include <asm/cacheflush.h> | 39 | #include <asm/cacheflush.h> |
40 | 40 | ||
41 | #include <mach/iomap.h> | 41 | #include <mach/iomap.h> |
42 | #include <mach/smmu.h> | ||
43 | #include <mach/tegra-ahb.h> | 42 | #include <mach/tegra-ahb.h> |
44 | 43 | ||
44 | enum smmu_hwgrp { | ||
45 | HWGRP_AFI, | ||
46 | HWGRP_AVPC, | ||
47 | HWGRP_DC, | ||
48 | HWGRP_DCB, | ||
49 | HWGRP_EPP, | ||
50 | HWGRP_G2, | ||
51 | HWGRP_HC, | ||
52 | HWGRP_HDA, | ||
53 | HWGRP_ISP, | ||
54 | HWGRP_MPE, | ||
55 | HWGRP_NV, | ||
56 | HWGRP_NV2, | ||
57 | HWGRP_PPCS, | ||
58 | HWGRP_SATA, | ||
59 | HWGRP_VDE, | ||
60 | HWGRP_VI, | ||
61 | |||
62 | HWGRP_COUNT, | ||
63 | |||
64 | HWGRP_END = ~0, | ||
65 | }; | ||
66 | |||
67 | #define HWG_AFI (1 << HWGRP_AFI) | ||
68 | #define HWG_AVPC (1 << HWGRP_AVPC) | ||
69 | #define HWG_DC (1 << HWGRP_DC) | ||
70 | #define HWG_DCB (1 << HWGRP_DCB) | ||
71 | #define HWG_EPP (1 << HWGRP_EPP) | ||
72 | #define HWG_G2 (1 << HWGRP_G2) | ||
73 | #define HWG_HC (1 << HWGRP_HC) | ||
74 | #define HWG_HDA (1 << HWGRP_HDA) | ||
75 | #define HWG_ISP (1 << HWGRP_ISP) | ||
76 | #define HWG_MPE (1 << HWGRP_MPE) | ||
77 | #define HWG_NV (1 << HWGRP_NV) | ||
78 | #define HWG_NV2 (1 << HWGRP_NV2) | ||
79 | #define HWG_PPCS (1 << HWGRP_PPCS) | ||
80 | #define HWG_SATA (1 << HWGRP_SATA) | ||
81 | #define HWG_VDE (1 << HWGRP_VDE) | ||
82 | #define HWG_VI (1 << HWGRP_VI) | ||
83 | |||
45 | /* bitmap of the page sizes currently supported */ | 84 | /* bitmap of the page sizes currently supported */ |
46 | #define SMMU_IOMMU_PGSIZES (SZ_4K) | 85 | #define SMMU_IOMMU_PGSIZES (SZ_4K) |
47 | 86 | ||