iommu/arm-smmu: fix calculation of TCR.T0SZ

T0SZ controls the input address range for TTBR0, so use the input
address range rather than the output address range for the calculation.
For stage-2, this means using the output size of stage-1.

Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 1599354e974d..81e8ec290756 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -800,6 +800,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
                         reg = TTBCR_TG0_64K;
 
                 if (!stage1) {
+                        reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
+
                         switch (smmu->s2_output_size) {
                         case 32:
                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
@@ -821,7 +823,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
                                 break;
                         }
                 } else {
-                        reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
+                        reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
                 }
         } else {
                 reg = 0;