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authorJoerg Roedel <joerg.roedel@amd.com>2012-05-31 11:38:11 -0400
committerJoerg Roedel <joerg.roedel@amd.com>2012-06-04 06:47:44 -0400
commitc1bf94ec1e12d76838ad485158aecf208ebd8fb9 (patch)
treee554cd3ac5103745366cdf139e5ccf0f2619cde4 /drivers/iommu/amd_iommu_init.c
parentf8f5701bdaf9134b1f90e5044a82c66324d2073f (diff)
iommu/amd: Cache pdev pointer to root-bridge
At some point pci_get_bus_and_slot started to enable interrupts. Since this function is used in the amd_iommu_resume path it will enable interrupts on resume which causes a warning. The fix will use a cached pointer to the root-bridge to re-enable the IOMMU in case the BIOS is broken. Cc: stable@vger.kernel.org Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu/amd_iommu_init.c')
-rw-r--r--drivers/iommu/amd_iommu_init.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index c56790375e0f..542024ba6dba 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -1029,6 +1029,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1029 if (!iommu->dev) 1029 if (!iommu->dev)
1030 return 1; 1030 return 1;
1031 1031
1032 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1033 PCI_DEVFN(0, 0));
1034
1032 iommu->cap_ptr = h->cap_ptr; 1035 iommu->cap_ptr = h->cap_ptr;
1033 iommu->pci_seg = h->pci_seg; 1036 iommu->pci_seg = h->pci_seg;
1034 iommu->mmio_phys = h->mmio_phys; 1037 iommu->mmio_phys = h->mmio_phys;
@@ -1323,20 +1326,16 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1323{ 1326{
1324 int i, j; 1327 int i, j;
1325 u32 ioc_feature_control; 1328 u32 ioc_feature_control;
1326 struct pci_dev *pdev = NULL; 1329 struct pci_dev *pdev = iommu->root_pdev;
1327 1330
1328 /* RD890 BIOSes may not have completely reconfigured the iommu */ 1331 /* RD890 BIOSes may not have completely reconfigured the iommu */
1329 if (!is_rd890_iommu(iommu->dev)) 1332 if (!is_rd890_iommu(iommu->dev) || !pdev)
1330 return; 1333 return;
1331 1334
1332 /* 1335 /*
1333 * First, we need to ensure that the iommu is enabled. This is 1336 * First, we need to ensure that the iommu is enabled. This is
1334 * controlled by a register in the northbridge 1337 * controlled by a register in the northbridge
1335 */ 1338 */
1336 pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
1337
1338 if (!pdev)
1339 return;
1340 1339
1341 /* Select Northbridge indirect register 0x75 and enable writing */ 1340 /* Select Northbridge indirect register 0x75 and enable writing */
1342 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 1341 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
@@ -1346,8 +1345,6 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1346 if (!(ioc_feature_control & 0x1)) 1345 if (!(ioc_feature_control & 0x1))
1347 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 1346 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1348 1347
1349 pci_dev_put(pdev);
1350
1351 /* Restore the iommu BAR */ 1348 /* Restore the iommu BAR */
1352 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 1349 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1353 iommu->stored_addr_lo); 1350 iommu->stored_addr_lo);