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authorOskar Schirmer <os@emlix.com>2010-05-13 03:42:23 -0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2010-05-13 03:43:32 -0400
commit3843384a055496dfed3c93ae883d964d8290fdab (patch)
treee60dfe169cd2a6bf83c7cb6d362c39a336b3798e /drivers/input
parentef110b24e28f36620f63dab94708a17c7e267358 (diff)
Input: ad7877 - keep dma rx buffers in seperate cache lines
With dma based spi transmission, data corruption is observed occasionally. With dma buffers located right next to msg and xfer fields, cache lines correctly flushed in preparation for dma usage may be polluted again when writing to fields in the same cache line. Make sure cache fields used with dma do not share cache lines with fields changed during dma handling. As both fields are part of a struct that is allocated via kzalloc, thus cache aligned, moving the fields to the 1st position and insert padding for alignment does the job. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Oliver Schneidewind <osw@emlix.com> Signed-off-by: Johannes Weiner <jw@emlix.com> Acked-by: Mike Frysinger <vapier@gentoo.org> [dtor@mail.ru - changed to use ___cacheline_aligned as suggested by akpm] Signed-off-by: Dmitry Torokhov <dtor@mail.ru>
Diffstat (limited to 'drivers/input')
-rw-r--r--drivers/input/touchscreen/ad7877.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/input/touchscreen/ad7877.c b/drivers/input/touchscreen/ad7877.c
index e019d53d1ab4..0d2d7e54b465 100644
--- a/drivers/input/touchscreen/ad7877.c
+++ b/drivers/input/touchscreen/ad7877.c
@@ -156,9 +156,14 @@ struct ser_req {
156 u16 reset; 156 u16 reset;
157 u16 ref_on; 157 u16 ref_on;
158 u16 command; 158 u16 command;
159 u16 sample;
160 struct spi_message msg; 159 struct spi_message msg;
161 struct spi_transfer xfer[6]; 160 struct spi_transfer xfer[6];
161
162 /*
163 * DMA (thus cache coherency maintenance) requires the
164 * transfer buffers to live in their own cache lines.
165 */
166 u16 sample ____cacheline_aligned;
162}; 167};
163 168
164struct ad7877 { 169struct ad7877 {
@@ -182,8 +187,6 @@ struct ad7877 {
182 u8 averaging; 187 u8 averaging;
183 u8 pen_down_acc_interval; 188 u8 pen_down_acc_interval;
184 189
185 u16 conversion_data[AD7877_NR_SENSE];
186
187 struct spi_transfer xfer[AD7877_NR_SENSE + 2]; 190 struct spi_transfer xfer[AD7877_NR_SENSE + 2];
188 struct spi_message msg; 191 struct spi_message msg;
189 192
@@ -195,6 +198,12 @@ struct ad7877 {
195 spinlock_t lock; 198 spinlock_t lock;
196 struct timer_list timer; /* P: lock */ 199 struct timer_list timer; /* P: lock */
197 unsigned pending:1; /* P: lock */ 200 unsigned pending:1; /* P: lock */
201
202 /*
203 * DMA (thus cache coherency maintenance) requires the
204 * transfer buffers to live in their own cache lines.
205 */
206 u16 conversion_data[AD7877_NR_SENSE] ____cacheline_aligned;
198}; 207};
199 208
200static int gpio3; 209static int gpio3;