diff options
author | Roland Dreier <rolandd@cisco.com> | 2010-03-02 02:51:57 -0500 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2010-03-02 02:51:57 -0500 |
commit | 3bbddbada87f30da8bcc5de7b9d06d8f2495aba5 (patch) | |
tree | 742f35cee7d5bf52ccf6797631ec3cd06439c247 /drivers/infiniband | |
parent | a835fb30954fe92a569206f9f684a755fbed395c (diff) | |
parent | 09124e1913cf2140941f60ab4fdf8576e1e8fd8d (diff) |
Merge branch 'nes' into for-next
Diffstat (limited to 'drivers/infiniband')
-rw-r--r-- | drivers/infiniband/hw/nes/nes.c | 1 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes.h | 9 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_cm.c | 11 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.c | 484 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_hw.h | 2 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_nic.c | 61 | ||||
-rw-r--r-- | drivers/infiniband/hw/nes/nes_verbs.c | 6 |
7 files changed, 284 insertions, 290 deletions
diff --git a/drivers/infiniband/hw/nes/nes.c b/drivers/infiniband/hw/nes/nes.c index b9d09bafd6c1..4272c52e38a4 100644 --- a/drivers/infiniband/hw/nes/nes.c +++ b/drivers/infiniband/hw/nes/nes.c | |||
@@ -110,6 +110,7 @@ static unsigned int sysfs_idx_addr; | |||
110 | 110 | ||
111 | static struct pci_device_id nes_pci_table[] = { | 111 | static struct pci_device_id nes_pci_table[] = { |
112 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020, PCI_ANY_ID, PCI_ANY_ID}, | 112 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020, PCI_ANY_ID, PCI_ANY_ID}, |
113 | {PCI_VENDOR_ID_NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020_KR, PCI_ANY_ID, PCI_ANY_ID}, | ||
113 | {0} | 114 | {0} |
114 | }; | 115 | }; |
115 | 116 | ||
diff --git a/drivers/infiniband/hw/nes/nes.h b/drivers/infiniband/hw/nes/nes.h index 98840564bb2f..cc78fee1dd51 100644 --- a/drivers/infiniband/hw/nes/nes.h +++ b/drivers/infiniband/hw/nes/nes.h | |||
@@ -64,8 +64,9 @@ | |||
64 | * NetEffect PCI vendor id and NE010 PCI device id. | 64 | * NetEffect PCI vendor id and NE010 PCI device id. |
65 | */ | 65 | */ |
66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ | 66 | #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */ |
67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 | 67 | #define PCI_VENDOR_ID_NETEFFECT 0x1678 |
68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 | 68 | #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100 |
69 | #define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110 | ||
69 | #endif | 70 | #endif |
70 | 71 | ||
71 | #define NE020_REV 4 | 72 | #define NE020_REV 4 |
@@ -193,8 +194,8 @@ extern u32 cm_packets_created; | |||
193 | extern u32 cm_packets_received; | 194 | extern u32 cm_packets_received; |
194 | extern u32 cm_packets_dropped; | 195 | extern u32 cm_packets_dropped; |
195 | extern u32 cm_packets_retrans; | 196 | extern u32 cm_packets_retrans; |
196 | extern u32 cm_listens_created; | 197 | extern atomic_t cm_listens_created; |
197 | extern u32 cm_listens_destroyed; | 198 | extern atomic_t cm_listens_destroyed; |
198 | extern u32 cm_backlog_drops; | 199 | extern u32 cm_backlog_drops; |
199 | extern atomic_t cm_loopbacks; | 200 | extern atomic_t cm_loopbacks; |
200 | extern atomic_t cm_nodes_created; | 201 | extern atomic_t cm_nodes_created; |
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c index 39468c277036..2a49ee40b520 100644 --- a/drivers/infiniband/hw/nes/nes_cm.c +++ b/drivers/infiniband/hw/nes/nes_cm.c | |||
@@ -67,8 +67,8 @@ u32 cm_packets_dropped; | |||
67 | u32 cm_packets_retrans; | 67 | u32 cm_packets_retrans; |
68 | u32 cm_packets_created; | 68 | u32 cm_packets_created; |
69 | u32 cm_packets_received; | 69 | u32 cm_packets_received; |
70 | u32 cm_listens_created; | 70 | atomic_t cm_listens_created; |
71 | u32 cm_listens_destroyed; | 71 | atomic_t cm_listens_destroyed; |
72 | u32 cm_backlog_drops; | 72 | u32 cm_backlog_drops; |
73 | atomic_t cm_loopbacks; | 73 | atomic_t cm_loopbacks; |
74 | atomic_t cm_nodes_created; | 74 | atomic_t cm_nodes_created; |
@@ -1011,9 +1011,10 @@ static int mini_cm_dec_refcnt_listen(struct nes_cm_core *cm_core, | |||
1011 | event.cm_info.loc_port = | 1011 | event.cm_info.loc_port = |
1012 | loopback->loc_port; | 1012 | loopback->loc_port; |
1013 | event.cm_info.cm_id = loopback->cm_id; | 1013 | event.cm_info.cm_id = loopback->cm_id; |
1014 | add_ref_cm_node(loopback); | ||
1015 | loopback->state = NES_CM_STATE_CLOSED; | ||
1014 | cm_event_connect_error(&event); | 1016 | cm_event_connect_error(&event); |
1015 | cm_node->state = NES_CM_STATE_LISTENER_DESTROYED; | 1017 | cm_node->state = NES_CM_STATE_LISTENER_DESTROYED; |
1016 | loopback->state = NES_CM_STATE_CLOSED; | ||
1017 | 1018 | ||
1018 | rem_ref_cm_node(cm_node->cm_core, | 1019 | rem_ref_cm_node(cm_node->cm_core, |
1019 | cm_node); | 1020 | cm_node); |
@@ -1042,7 +1043,7 @@ static int mini_cm_dec_refcnt_listen(struct nes_cm_core *cm_core, | |||
1042 | kfree(listener); | 1043 | kfree(listener); |
1043 | listener = NULL; | 1044 | listener = NULL; |
1044 | ret = 0; | 1045 | ret = 0; |
1045 | cm_listens_destroyed++; | 1046 | atomic_inc(&cm_listens_destroyed); |
1046 | } else { | 1047 | } else { |
1047 | spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); | 1048 | spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); |
1048 | } | 1049 | } |
@@ -3172,7 +3173,7 @@ int nes_create_listen(struct iw_cm_id *cm_id, int backlog) | |||
3172 | g_cm_core->api->stop_listener(g_cm_core, (void *)cm_node); | 3173 | g_cm_core->api->stop_listener(g_cm_core, (void *)cm_node); |
3173 | return err; | 3174 | return err; |
3174 | } | 3175 | } |
3175 | cm_listens_created++; | 3176 | atomic_inc(&cm_listens_created); |
3176 | } | 3177 | } |
3177 | 3178 | ||
3178 | cm_id->add_ref(cm_id); | 3179 | cm_id->add_ref(cm_id); |
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c index b1c2cbb88f09..ce7f53833577 100644 --- a/drivers/infiniband/hw/nes/nes_hw.c +++ b/drivers/infiniband/hw/nes/nes_hw.c | |||
@@ -748,16 +748,28 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
748 | 748 | ||
749 | if (hw_rev != NE020_REV) { | 749 | if (hw_rev != NE020_REV) { |
750 | /* init serdes 0 */ | 750 | /* init serdes 0 */ |
751 | if (wide_ppm_offset && (nesadapter->phy_type[0] == NES_PHY_TYPE_CX4)) | 751 | switch (nesadapter->phy_type[0]) { |
752 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA); | 752 | case NES_PHY_TYPE_CX4: |
753 | else | 753 | if (wide_ppm_offset) |
754 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA); | ||
755 | else | ||
756 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
757 | break; | ||
758 | case NES_PHY_TYPE_KR: | ||
759 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
760 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000); | ||
761 | break; | ||
762 | case NES_PHY_TYPE_PUMA_1G: | ||
754 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | 763 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); |
755 | |||
756 | if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { | ||
757 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); | 764 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); |
758 | sds |= 0x00000100; | 765 | sds |= 0x00000100; |
759 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds); | 766 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds); |
767 | break; | ||
768 | default: | ||
769 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF); | ||
770 | break; | ||
760 | } | 771 | } |
772 | |||
761 | if (!OneG_Mode) | 773 | if (!OneG_Mode) |
762 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000); | 774 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000); |
763 | 775 | ||
@@ -778,6 +790,9 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count, | |||
778 | if (wide_ppm_offset) | 790 | if (wide_ppm_offset) |
779 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); | 791 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA); |
780 | break; | 792 | break; |
793 | case NES_PHY_TYPE_KR: | ||
794 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000); | ||
795 | break; | ||
781 | case NES_PHY_TYPE_PUMA_1G: | 796 | case NES_PHY_TYPE_PUMA_1G: |
782 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); | 797 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1); |
783 | sds |= 0x000000100; | 798 | sds |= 0x000000100; |
@@ -1279,115 +1294,115 @@ int nes_destroy_cqp(struct nes_device *nesdev) | |||
1279 | 1294 | ||
1280 | 1295 | ||
1281 | /** | 1296 | /** |
1282 | * nes_init_phy | 1297 | * nes_init_1g_phy |
1283 | */ | 1298 | */ |
1284 | int nes_init_phy(struct nes_device *nesdev) | 1299 | int nes_init_1g_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index) |
1285 | { | 1300 | { |
1286 | struct nes_adapter *nesadapter = nesdev->nesadapter; | ||
1287 | u32 counter = 0; | 1301 | u32 counter = 0; |
1288 | u32 sds; | ||
1289 | u32 mac_index = nesdev->mac_index; | ||
1290 | u32 tx_config = 0; | ||
1291 | u16 phy_data; | 1302 | u16 phy_data; |
1292 | u32 temp_phy_data = 0; | 1303 | int ret = 0; |
1293 | u32 temp_phy_data2 = 0; | ||
1294 | u8 phy_type = nesadapter->phy_type[mac_index]; | ||
1295 | u8 phy_index = nesadapter->phy_index[mac_index]; | ||
1296 | |||
1297 | if ((nesadapter->OneG_Mode) && | ||
1298 | (phy_type != NES_PHY_TYPE_PUMA_1G)) { | ||
1299 | nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index); | ||
1300 | if (phy_type == NES_PHY_TYPE_1G) { | ||
1301 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); | ||
1302 | tx_config &= 0xFFFFFFE3; | ||
1303 | tx_config |= 0x04; | ||
1304 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); | ||
1305 | } | ||
1306 | 1304 | ||
1307 | nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data); | 1305 | nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data); |
1308 | nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000); | 1306 | nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000); |
1309 | 1307 | ||
1310 | /* Reset the PHY */ | 1308 | /* Reset the PHY */ |
1311 | nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000); | 1309 | nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000); |
1312 | udelay(100); | 1310 | udelay(100); |
1313 | counter = 0; | 1311 | counter = 0; |
1314 | do { | 1312 | do { |
1315 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
1316 | if (counter++ > 100) | ||
1317 | break; | ||
1318 | } while (phy_data & 0x8000); | ||
1319 | |||
1320 | /* Setting no phy loopback */ | ||
1321 | phy_data &= 0xbfff; | ||
1322 | phy_data |= 0x1140; | ||
1323 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data); | ||
1324 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | 1313 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); |
1325 | nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data); | 1314 | if (counter++ > 100) { |
1326 | nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data); | 1315 | ret = -1; |
1327 | 1316 | break; | |
1328 | /* Setting the interrupt mask */ | 1317 | } |
1329 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | 1318 | } while (phy_data & 0x8000); |
1330 | nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee); | 1319 | |
1331 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | 1320 | /* Setting no phy loopback */ |
1321 | phy_data &= 0xbfff; | ||
1322 | phy_data |= 0x1140; | ||
1323 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data); | ||
1324 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
1325 | nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data); | ||
1326 | nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data); | ||
1327 | |||
1328 | /* Setting the interrupt mask */ | ||
1329 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | ||
1330 | nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee); | ||
1331 | nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data); | ||
1332 | |||
1333 | /* turning on flow control */ | ||
1334 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1335 | nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00); | ||
1336 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1337 | |||
1338 | /* Clear Half duplex */ | ||
1339 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | ||
1340 | nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100)); | ||
1341 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | ||
1342 | |||
1343 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | ||
1344 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300); | ||
1345 | |||
1346 | return ret; | ||
1347 | } | ||
1332 | 1348 | ||
1333 | /* turning on flow control */ | ||
1334 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1335 | nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00); | ||
1336 | nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data); | ||
1337 | 1349 | ||
1338 | /* Clear Half duplex */ | 1350 | /** |
1339 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | 1351 | * nes_init_2025_phy |
1340 | nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100)); | 1352 | */ |
1341 | nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data); | 1353 | int nes_init_2025_phy(struct nes_device *nesdev, u8 phy_type, u8 phy_index) |
1354 | { | ||
1355 | u32 temp_phy_data = 0; | ||
1356 | u32 temp_phy_data2 = 0; | ||
1357 | u32 counter = 0; | ||
1358 | u32 sds; | ||
1359 | u32 mac_index = nesdev->mac_index; | ||
1360 | int ret = 0; | ||
1361 | unsigned int first_attempt = 1; | ||
1342 | 1362 | ||
1343 | nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); | 1363 | /* Check firmware heartbeat */ |
1344 | nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300); | 1364 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); |
1365 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1366 | udelay(1500); | ||
1367 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | ||
1368 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1345 | 1369 | ||
1346 | return 0; | 1370 | if (temp_phy_data != temp_phy_data2) { |
1371 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | ||
1372 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1373 | if ((temp_phy_data & 0xff) > 0x20) | ||
1374 | return 0; | ||
1375 | printk(PFX "Reinitialize external PHY\n"); | ||
1347 | } | 1376 | } |
1348 | 1377 | ||
1349 | if ((phy_type == NES_PHY_TYPE_IRIS) || | 1378 | /* no heartbeat, configure the PHY */ |
1350 | (phy_type == NES_PHY_TYPE_ARGUS) || | 1379 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000); |
1351 | (phy_type == NES_PHY_TYPE_SFP_D)) { | 1380 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000); |
1352 | /* setup 10G MDIO operation */ | 1381 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); |
1353 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); | 1382 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); |
1354 | tx_config &= 0xFFFFFFE3; | ||
1355 | tx_config |= 0x15; | ||
1356 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); | ||
1357 | } | ||
1358 | if ((phy_type == NES_PHY_TYPE_ARGUS) || | ||
1359 | (phy_type == NES_PHY_TYPE_SFP_D)) { | ||
1360 | u32 first_time = 1; | ||
1361 | 1383 | ||
1362 | /* Check firmware heartbeat */ | 1384 | switch (phy_type) { |
1363 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1385 | case NES_PHY_TYPE_ARGUS: |
1364 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1386 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); |
1365 | udelay(1500); | 1387 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); |
1366 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1388 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); |
1367 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1389 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008); |
1390 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001); | ||
1391 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); | ||
1392 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); | ||
1368 | 1393 | ||
1369 | if (temp_phy_data != temp_phy_data2) { | 1394 | /* setup LEDs */ |
1370 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | 1395 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); |
1371 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1396 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A); |
1372 | if ((temp_phy_data & 0xff) > 0x20) | 1397 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009); |
1373 | return 0; | 1398 | break; |
1374 | printk(PFX "Reinitializing PHY\n"); | ||
1375 | } | ||
1376 | 1399 | ||
1377 | /* no heartbeat, configure the PHY */ | 1400 | case NES_PHY_TYPE_SFP_D: |
1378 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000); | ||
1379 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000); | ||
1380 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); | 1401 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); |
1381 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); | 1402 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); |
1382 | if (phy_type == NES_PHY_TYPE_ARGUS) { | 1403 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004); |
1383 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); | 1404 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038); |
1384 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008); | 1405 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013); |
1385 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001); | ||
1386 | } else { | ||
1387 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004); | ||
1388 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038); | ||
1389 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013); | ||
1390 | } | ||
1391 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); | 1406 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098); |
1392 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); | 1407 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); |
1393 | 1408 | ||
@@ -1395,71 +1410,136 @@ int nes_init_phy(struct nes_device *nesdev) | |||
1395 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); | 1410 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007); |
1396 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A); | 1411 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A); |
1397 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009); | 1412 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009); |
1413 | break; | ||
1414 | |||
1415 | case NES_PHY_TYPE_KR: | ||
1416 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A); | ||
1417 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052); | ||
1418 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C); | ||
1419 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0010); | ||
1420 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0013); | ||
1421 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0080); | ||
1422 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00); | ||
1423 | |||
1424 | /* setup LEDs */ | ||
1425 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x000B); | ||
1426 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x0003); | ||
1427 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0004); | ||
1398 | 1428 | ||
1399 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528); | 1429 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0022, 0x406D); |
1430 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0023, 0x0020); | ||
1431 | break; | ||
1432 | } | ||
1433 | |||
1434 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528); | ||
1400 | 1435 | ||
1401 | /* Bring PHY out of reset */ | 1436 | /* Bring PHY out of reset */ |
1402 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002); | 1437 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002); |
1403 | 1438 | ||
1404 | /* Check for heartbeat */ | 1439 | /* Check for heartbeat */ |
1405 | counter = 0; | 1440 | counter = 0; |
1406 | mdelay(690); | 1441 | mdelay(690); |
1442 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | ||
1443 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1444 | do { | ||
1445 | if (counter++ > 150) { | ||
1446 | printk(PFX "No PHY heartbeat\n"); | ||
1447 | break; | ||
1448 | } | ||
1449 | mdelay(1); | ||
1407 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1450 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); |
1451 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
1452 | } while ((temp_phy_data2 == temp_phy_data)); | ||
1453 | |||
1454 | /* wait for tracking */ | ||
1455 | counter = 0; | ||
1456 | do { | ||
1457 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | ||
1408 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1458 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); |
1409 | do { | 1459 | if (counter++ > 300) { |
1410 | if (counter++ > 150) { | 1460 | if (((temp_phy_data & 0xff) == 0x0) && first_attempt) { |
1411 | printk(PFX "No PHY heartbeat\n"); | 1461 | first_attempt = 0; |
1462 | counter = 0; | ||
1463 | /* reset AMCC PHY and try again */ | ||
1464 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0); | ||
1465 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040); | ||
1466 | continue; | ||
1467 | } else { | ||
1468 | ret = 1; | ||
1412 | break; | 1469 | break; |
1413 | } | 1470 | } |
1414 | mdelay(1); | 1471 | } |
1415 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee); | 1472 | mdelay(10); |
1416 | temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1473 | } while ((temp_phy_data & 0xff) < 0x30); |
1417 | } while ((temp_phy_data2 == temp_phy_data)); | 1474 | |
1418 | 1475 | /* setup signal integrity */ | |
1419 | /* wait for tracking */ | 1476 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000); |
1420 | counter = 0; | 1477 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE); |
1421 | do { | 1478 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032); |
1422 | nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd); | 1479 | if (phy_type == NES_PHY_TYPE_KR) { |
1423 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | 1480 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x000C); |
1424 | if (counter++ > 300) { | 1481 | } else { |
1425 | if (((temp_phy_data & 0xff) == 0x0) && first_time) { | ||
1426 | first_time = 0; | ||
1427 | counter = 0; | ||
1428 | /* reset AMCC PHY and try again */ | ||
1429 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x00c0); | ||
1430 | nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0xe854, 0x0040); | ||
1431 | continue; | ||
1432 | } else { | ||
1433 | printk(PFX "PHY did not track\n"); | ||
1434 | break; | ||
1435 | } | ||
1436 | } | ||
1437 | mdelay(10); | ||
1438 | } while ((temp_phy_data & 0xff) < 0x30); | ||
1439 | |||
1440 | /* setup signal integrity */ | ||
1441 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000); | ||
1442 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE); | ||
1443 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032); | ||
1444 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002); | 1482 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002); |
1445 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063); | 1483 | nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063); |
1484 | } | ||
1485 | |||
1486 | /* reset serdes */ | ||
1487 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200); | ||
1488 | sds |= 0x1; | ||
1489 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds); | ||
1490 | sds &= 0xfffffffe; | ||
1491 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + mac_index * 0x200, sds); | ||
1492 | |||
1493 | counter = 0; | ||
1494 | while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) | ||
1495 | && (counter++ < 5000)) | ||
1496 | ; | ||
1497 | |||
1498 | return ret; | ||
1499 | } | ||
1500 | |||
1446 | 1501 | ||
1447 | /* reset serdes */ | 1502 | /** |
1448 | sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + | 1503 | * nes_init_phy |
1449 | mac_index * 0x200); | 1504 | */ |
1450 | sds |= 0x1; | 1505 | int nes_init_phy(struct nes_device *nesdev) |
1451 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + | 1506 | { |
1452 | mac_index * 0x200, sds); | 1507 | struct nes_adapter *nesadapter = nesdev->nesadapter; |
1453 | sds &= 0xfffffffe; | 1508 | u32 mac_index = nesdev->mac_index; |
1454 | nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 + | 1509 | u32 tx_config = 0; |
1455 | mac_index * 0x200, sds); | 1510 | unsigned long flags; |
1456 | 1511 | u8 phy_type = nesadapter->phy_type[mac_index]; | |
1457 | counter = 0; | 1512 | u8 phy_index = nesadapter->phy_index[mac_index]; |
1458 | while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) | 1513 | int ret = 0; |
1459 | && (counter++ < 5000)) | 1514 | |
1460 | ; | 1515 | tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); |
1516 | if (phy_type == NES_PHY_TYPE_1G) { | ||
1517 | /* setup 1G MDIO operation */ | ||
1518 | tx_config &= 0xFFFFFFE3; | ||
1519 | tx_config |= 0x04; | ||
1520 | } else { | ||
1521 | /* setup 10G MDIO operation */ | ||
1522 | tx_config &= 0xFFFFFFE3; | ||
1523 | tx_config |= 0x15; | ||
1461 | } | 1524 | } |
1462 | return 0; | 1525 | nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); |
1526 | |||
1527 | spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags); | ||
1528 | |||
1529 | switch (phy_type) { | ||
1530 | case NES_PHY_TYPE_1G: | ||
1531 | ret = nes_init_1g_phy(nesdev, phy_type, phy_index); | ||
1532 | break; | ||
1533 | case NES_PHY_TYPE_ARGUS: | ||
1534 | case NES_PHY_TYPE_SFP_D: | ||
1535 | case NES_PHY_TYPE_KR: | ||
1536 | ret = nes_init_2025_phy(nesdev, phy_type, phy_index); | ||
1537 | break; | ||
1538 | } | ||
1539 | |||
1540 | spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags); | ||
1541 | |||
1542 | return ret; | ||
1463 | } | 1543 | } |
1464 | 1544 | ||
1465 | 1545 | ||
@@ -2460,23 +2540,9 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number) | |||
2460 | } | 2540 | } |
2461 | } else { | 2541 | } else { |
2462 | switch (nesadapter->phy_type[mac_index]) { | 2542 | switch (nesadapter->phy_type[mac_index]) { |
2463 | case NES_PHY_TYPE_IRIS: | ||
2464 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); | ||
2465 | temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
2466 | u32temp = 20; | ||
2467 | do { | ||
2468 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); | ||
2469 | phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); | ||
2470 | if ((phy_data == temp_phy_data) || (!(--u32temp))) | ||
2471 | break; | ||
2472 | temp_phy_data = phy_data; | ||
2473 | } while (1); | ||
2474 | nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n", | ||
2475 | __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP"); | ||
2476 | break; | ||
2477 | |||
2478 | case NES_PHY_TYPE_ARGUS: | 2543 | case NES_PHY_TYPE_ARGUS: |
2479 | case NES_PHY_TYPE_SFP_D: | 2544 | case NES_PHY_TYPE_SFP_D: |
2545 | case NES_PHY_TYPE_KR: | ||
2480 | /* clear the alarms */ | 2546 | /* clear the alarms */ |
2481 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008); | 2547 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008); |
2482 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001); | 2548 | nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001); |
@@ -3352,8 +3418,6 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3352 | u16 async_event_id; | 3418 | u16 async_event_id; |
3353 | u8 tcp_state; | 3419 | u8 tcp_state; |
3354 | u8 iwarp_state; | 3420 | u8 iwarp_state; |
3355 | int must_disconn = 1; | ||
3356 | int must_terminate = 0; | ||
3357 | struct ib_event ibevent; | 3421 | struct ib_event ibevent; |
3358 | 3422 | ||
3359 | nes_debug(NES_DBG_AEQ, "\n"); | 3423 | nes_debug(NES_DBG_AEQ, "\n"); |
@@ -3367,6 +3431,8 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3367 | BUG_ON(!context); | 3431 | BUG_ON(!context); |
3368 | } | 3432 | } |
3369 | 3433 | ||
3434 | /* context is nesqp unless async_event_id == CQ ERROR */ | ||
3435 | nesqp = (struct nes_qp *)(unsigned long)context; | ||
3370 | async_event_id = (u16)aeq_info; | 3436 | async_event_id = (u16)aeq_info; |
3371 | tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT; | 3437 | tcp_state = (aeq_info & NES_AEQE_TCP_STATE_MASK) >> NES_AEQE_TCP_STATE_SHIFT; |
3372 | iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT; | 3438 | iwarp_state = (aeq_info & NES_AEQE_IWARP_STATE_MASK) >> NES_AEQE_IWARP_STATE_SHIFT; |
@@ -3378,8 +3444,6 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3378 | 3444 | ||
3379 | switch (async_event_id) { | 3445 | switch (async_event_id) { |
3380 | case NES_AEQE_AEID_LLP_FIN_RECEIVED: | 3446 | case NES_AEQE_AEID_LLP_FIN_RECEIVED: |
3381 | nesqp = (struct nes_qp *)(unsigned long)context; | ||
3382 | |||
3383 | if (nesqp->term_flags) | 3447 | if (nesqp->term_flags) |
3384 | return; /* Ignore it, wait for close complete */ | 3448 | return; /* Ignore it, wait for close complete */ |
3385 | 3449 | ||
@@ -3394,79 +3458,48 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3394 | async_event_id, nesqp->last_aeq, tcp_state); | 3458 | async_event_id, nesqp->last_aeq, tcp_state); |
3395 | } | 3459 | } |
3396 | 3460 | ||
3397 | if ((tcp_state != NES_AEQE_TCP_STATE_CLOSE_WAIT) || | 3461 | break; |
3398 | (nesqp->ibqp_state != IB_QPS_RTS)) { | ||
3399 | /* FIN Received but tcp state or IB state moved on, | ||
3400 | should expect a close complete */ | ||
3401 | return; | ||
3402 | } | ||
3403 | |||
3404 | case NES_AEQE_AEID_LLP_CLOSE_COMPLETE: | 3462 | case NES_AEQE_AEID_LLP_CLOSE_COMPLETE: |
3405 | nesqp = (struct nes_qp *)(unsigned long)context; | ||
3406 | if (nesqp->term_flags) { | 3463 | if (nesqp->term_flags) { |
3407 | nes_terminate_done(nesqp, 0); | 3464 | nes_terminate_done(nesqp, 0); |
3408 | return; | 3465 | return; |
3409 | } | 3466 | } |
3467 | spin_lock_irqsave(&nesqp->lock, flags); | ||
3468 | nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_CLOSING; | ||
3469 | spin_unlock_irqrestore(&nesqp->lock, flags); | ||
3470 | nes_hw_modify_qp(nesdev, nesqp, NES_CQP_QP_IWARP_STATE_CLOSING, 0, 0); | ||
3471 | nes_cm_disconn(nesqp); | ||
3472 | break; | ||
3410 | 3473 | ||
3411 | case NES_AEQE_AEID_LLP_CONNECTION_RESET: | ||
3412 | case NES_AEQE_AEID_RESET_SENT: | 3474 | case NES_AEQE_AEID_RESET_SENT: |
3413 | nesqp = (struct nes_qp *)(unsigned long)context; | 3475 | tcp_state = NES_AEQE_TCP_STATE_CLOSED; |
3414 | if (async_event_id == NES_AEQE_AEID_RESET_SENT) { | ||
3415 | tcp_state = NES_AEQE_TCP_STATE_CLOSED; | ||
3416 | } | ||
3417 | spin_lock_irqsave(&nesqp->lock, flags); | 3476 | spin_lock_irqsave(&nesqp->lock, flags); |
3418 | nesqp->hw_iwarp_state = iwarp_state; | 3477 | nesqp->hw_iwarp_state = iwarp_state; |
3419 | nesqp->hw_tcp_state = tcp_state; | 3478 | nesqp->hw_tcp_state = tcp_state; |
3420 | nesqp->last_aeq = async_event_id; | 3479 | nesqp->last_aeq = async_event_id; |
3421 | 3480 | nesqp->hte_added = 0; | |
3422 | if ((tcp_state == NES_AEQE_TCP_STATE_CLOSED) || | ||
3423 | (tcp_state == NES_AEQE_TCP_STATE_TIME_WAIT)) { | ||
3424 | nesqp->hte_added = 0; | ||
3425 | next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_DEL_HTE; | ||
3426 | } | ||
3427 | |||
3428 | if ((nesqp->ibqp_state == IB_QPS_RTS) && | ||
3429 | ((tcp_state == NES_AEQE_TCP_STATE_CLOSE_WAIT) || | ||
3430 | (async_event_id == NES_AEQE_AEID_LLP_CONNECTION_RESET))) { | ||
3431 | switch (nesqp->hw_iwarp_state) { | ||
3432 | case NES_AEQE_IWARP_STATE_RTS: | ||
3433 | next_iwarp_state = NES_CQP_QP_IWARP_STATE_CLOSING; | ||
3434 | nesqp->hw_iwarp_state = NES_AEQE_IWARP_STATE_CLOSING; | ||
3435 | break; | ||
3436 | case NES_AEQE_IWARP_STATE_TERMINATE: | ||
3437 | must_disconn = 0; /* terminate path takes care of disconn */ | ||
3438 | if (nesqp->term_flags == 0) | ||
3439 | must_terminate = 1; | ||
3440 | break; | ||
3441 | } | ||
3442 | } else { | ||
3443 | if (async_event_id == NES_AEQE_AEID_LLP_FIN_RECEIVED) { | ||
3444 | /* FIN Received but ib state not RTS, | ||
3445 | close complete will be on its way */ | ||
3446 | must_disconn = 0; | ||
3447 | } | ||
3448 | } | ||
3449 | spin_unlock_irqrestore(&nesqp->lock, flags); | 3481 | spin_unlock_irqrestore(&nesqp->lock, flags); |
3482 | next_iwarp_state = NES_CQP_QP_IWARP_STATE_ERROR | NES_CQP_QP_DEL_HTE; | ||
3483 | nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0); | ||
3484 | nes_cm_disconn(nesqp); | ||
3485 | break; | ||
3450 | 3486 | ||
3451 | if (must_terminate) | 3487 | case NES_AEQE_AEID_LLP_CONNECTION_RESET: |
3452 | nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL); | 3488 | if (atomic_read(&nesqp->close_timer_started)) |
3453 | else if (must_disconn) { | 3489 | return; |
3454 | if (next_iwarp_state) { | 3490 | spin_lock_irqsave(&nesqp->lock, flags); |
3455 | nes_debug(NES_DBG_AEQ, "issuing hw modifyqp for QP%u. next state = 0x%08X\n", | 3491 | nesqp->hw_iwarp_state = iwarp_state; |
3456 | nesqp->hwqp.qp_id, next_iwarp_state); | 3492 | nesqp->hw_tcp_state = tcp_state; |
3457 | nes_hw_modify_qp(nesdev, nesqp, next_iwarp_state, 0, 0); | 3493 | nesqp->last_aeq = async_event_id; |
3458 | } | 3494 | spin_unlock_irqrestore(&nesqp->lock, flags); |
3459 | nes_cm_disconn(nesqp); | 3495 | nes_cm_disconn(nesqp); |
3460 | } | ||
3461 | break; | 3496 | break; |
3462 | 3497 | ||
3463 | case NES_AEQE_AEID_TERMINATE_SENT: | 3498 | case NES_AEQE_AEID_TERMINATE_SENT: |
3464 | nesqp = (struct nes_qp *)(unsigned long)context; | ||
3465 | nes_terminate_send_fin(nesdev, nesqp, aeqe); | 3499 | nes_terminate_send_fin(nesdev, nesqp, aeqe); |
3466 | break; | 3500 | break; |
3467 | 3501 | ||
3468 | case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED: | 3502 | case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED: |
3469 | nesqp = (struct nes_qp *)(unsigned long)context; | ||
3470 | nes_terminate_received(nesdev, nesqp, aeqe); | 3503 | nes_terminate_received(nesdev, nesqp, aeqe); |
3471 | break; | 3504 | break; |
3472 | 3505 | ||
@@ -3480,7 +3513,8 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3480 | case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: | 3513 | case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: |
3481 | case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION: | 3514 | case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION: |
3482 | case NES_AEQE_AEID_AMP_TO_WRAP: | 3515 | case NES_AEQE_AEID_AMP_TO_WRAP: |
3483 | nesqp = (struct nes_qp *)(unsigned long)context; | 3516 | printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_ACCESS_ERR\n", |
3517 | nesqp->hwqp.qp_id, async_event_id); | ||
3484 | nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_ACCESS_ERR); | 3518 | nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_ACCESS_ERR); |
3485 | break; | 3519 | break; |
3486 | 3520 | ||
@@ -3488,7 +3522,6 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3488 | case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL: | 3522 | case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL: |
3489 | case NES_AEQE_AEID_DDP_UBE_INVALID_MO: | 3523 | case NES_AEQE_AEID_DDP_UBE_INVALID_MO: |
3490 | case NES_AEQE_AEID_DDP_UBE_INVALID_QN: | 3524 | case NES_AEQE_AEID_DDP_UBE_INVALID_QN: |
3491 | nesqp = (struct nes_qp *)(unsigned long)context; | ||
3492 | if (iwarp_opcode(nesqp, aeq_info) > IWARP_OPCODE_TERM) { | 3525 | if (iwarp_opcode(nesqp, aeq_info) > IWARP_OPCODE_TERM) { |
3493 | aeq_info &= 0xffff0000; | 3526 | aeq_info &= 0xffff0000; |
3494 | aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE; | 3527 | aeq_info |= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE; |
@@ -3530,7 +3563,8 @@ static void nes_process_iwarp_aeqe(struct nes_device *nesdev, | |||
3530 | case NES_AEQE_AEID_STAG_ZERO_INVALID: | 3563 | case NES_AEQE_AEID_STAG_ZERO_INVALID: |
3531 | case NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST: | 3564 | case NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST: |
3532 | case NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: | 3565 | case NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: |
3533 | nesqp = (struct nes_qp *)(unsigned long)context; | 3566 | printk(KERN_ERR PFX "QP[%u] async_event_id=0x%04X IB_EVENT_QP_FATAL\n", |
3567 | nesqp->hwqp.qp_id, async_event_id); | ||
3534 | nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL); | 3568 | nes_terminate_connection(nesdev, nesqp, aeqe, IB_EVENT_QP_FATAL); |
3535 | break; | 3569 | break; |
3536 | 3570 | ||
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h index 084be0ee689b..9b1e7f869d83 100644 --- a/drivers/infiniband/hw/nes/nes_hw.h +++ b/drivers/infiniband/hw/nes/nes_hw.h | |||
@@ -37,12 +37,12 @@ | |||
37 | 37 | ||
38 | #define NES_PHY_TYPE_CX4 1 | 38 | #define NES_PHY_TYPE_CX4 1 |
39 | #define NES_PHY_TYPE_1G 2 | 39 | #define NES_PHY_TYPE_1G 2 |
40 | #define NES_PHY_TYPE_IRIS 3 | ||
41 | #define NES_PHY_TYPE_ARGUS 4 | 40 | #define NES_PHY_TYPE_ARGUS 4 |
42 | #define NES_PHY_TYPE_PUMA_1G 5 | 41 | #define NES_PHY_TYPE_PUMA_1G 5 |
43 | #define NES_PHY_TYPE_PUMA_10G 6 | 42 | #define NES_PHY_TYPE_PUMA_10G 6 |
44 | #define NES_PHY_TYPE_GLADIUS 7 | 43 | #define NES_PHY_TYPE_GLADIUS 7 |
45 | #define NES_PHY_TYPE_SFP_D 8 | 44 | #define NES_PHY_TYPE_SFP_D 8 |
45 | #define NES_PHY_TYPE_KR 9 | ||
46 | 46 | ||
47 | #define NES_MULTICAST_PF_MAX 8 | 47 | #define NES_MULTICAST_PF_MAX 8 |
48 | 48 | ||
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c index ab1102780186..7dd6ce6e7b99 100644 --- a/drivers/infiniband/hw/nes/nes_nic.c +++ b/drivers/infiniband/hw/nes/nes_nic.c | |||
@@ -1230,8 +1230,8 @@ static void nes_netdev_get_ethtool_stats(struct net_device *netdev, | |||
1230 | target_stat_values[++index] = cm_packets_received; | 1230 | target_stat_values[++index] = cm_packets_received; |
1231 | target_stat_values[++index] = cm_packets_dropped; | 1231 | target_stat_values[++index] = cm_packets_dropped; |
1232 | target_stat_values[++index] = cm_packets_retrans; | 1232 | target_stat_values[++index] = cm_packets_retrans; |
1233 | target_stat_values[++index] = cm_listens_created; | 1233 | target_stat_values[++index] = atomic_read(&cm_listens_created); |
1234 | target_stat_values[++index] = cm_listens_destroyed; | 1234 | target_stat_values[++index] = atomic_read(&cm_listens_destroyed); |
1235 | target_stat_values[++index] = cm_backlog_drops; | 1235 | target_stat_values[++index] = cm_backlog_drops; |
1236 | target_stat_values[++index] = atomic_read(&cm_loopbacks); | 1236 | target_stat_values[++index] = atomic_read(&cm_loopbacks); |
1237 | target_stat_values[++index] = atomic_read(&cm_nodes_created); | 1237 | target_stat_values[++index] = atomic_read(&cm_nodes_created); |
@@ -1461,9 +1461,9 @@ static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd | |||
1461 | } | 1461 | } |
1462 | return 0; | 1462 | return 0; |
1463 | } | 1463 | } |
1464 | if ((phy_type == NES_PHY_TYPE_IRIS) || | 1464 | if ((phy_type == NES_PHY_TYPE_ARGUS) || |
1465 | (phy_type == NES_PHY_TYPE_ARGUS) || | 1465 | (phy_type == NES_PHY_TYPE_SFP_D) || |
1466 | (phy_type == NES_PHY_TYPE_SFP_D)) { | 1466 | (phy_type == NES_PHY_TYPE_KR)) { |
1467 | et_cmd->transceiver = XCVR_EXTERNAL; | 1467 | et_cmd->transceiver = XCVR_EXTERNAL; |
1468 | et_cmd->port = PORT_FIBRE; | 1468 | et_cmd->port = PORT_FIBRE; |
1469 | et_cmd->supported = SUPPORTED_FIBRE; | 1469 | et_cmd->supported = SUPPORTED_FIBRE; |
@@ -1583,8 +1583,7 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, | |||
1583 | struct net_device *netdev; | 1583 | struct net_device *netdev; |
1584 | struct nic_qp_map *curr_qp_map; | 1584 | struct nic_qp_map *curr_qp_map; |
1585 | u32 u32temp; | 1585 | u32 u32temp; |
1586 | u16 phy_data; | 1586 | u8 phy_type = nesdev->nesadapter->phy_type[nesdev->mac_index]; |
1587 | u16 temp_phy_data; | ||
1588 | 1587 | ||
1589 | netdev = alloc_etherdev(sizeof(struct nes_vnic)); | 1588 | netdev = alloc_etherdev(sizeof(struct nes_vnic)); |
1590 | if (!netdev) { | 1589 | if (!netdev) { |
@@ -1692,65 +1691,23 @@ struct net_device *nes_netdev_init(struct nes_device *nesdev, | |||
1692 | 1691 | ||
1693 | if ((nesdev->netdev_count == 0) && | 1692 | if ((nesdev->netdev_count == 0) && |
1694 | ((PCI_FUNC(nesdev->pcidev->devfn) == nesdev->mac_index) || | 1693 | ((PCI_FUNC(nesdev->pcidev->devfn) == nesdev->mac_index) || |
1695 | ((nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_PUMA_1G) && | 1694 | ((phy_type == NES_PHY_TYPE_PUMA_1G) && |
1696 | (((PCI_FUNC(nesdev->pcidev->devfn) == 1) && (nesdev->mac_index == 2)) || | 1695 | (((PCI_FUNC(nesdev->pcidev->devfn) == 1) && (nesdev->mac_index == 2)) || |
1697 | ((PCI_FUNC(nesdev->pcidev->devfn) == 2) && (nesdev->mac_index == 1)))))) { | 1696 | ((PCI_FUNC(nesdev->pcidev->devfn) == 2) && (nesdev->mac_index == 1)))))) { |
1698 | /* | ||
1699 | * nes_debug(NES_DBG_INIT, "Setting up PHY interrupt mask. Using register index 0x%04X\n", | ||
1700 | * NES_IDX_PHY_PCS_CONTROL_STATUS0 + (0x200 * (nesvnic->logical_port & 1))); | ||
1701 | */ | ||
1702 | u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + | 1697 | u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + |
1703 | (0x200 * (nesdev->mac_index & 1))); | 1698 | (0x200 * (nesdev->mac_index & 1))); |
1704 | if (nesdev->nesadapter->phy_type[nesdev->mac_index] != NES_PHY_TYPE_PUMA_1G) { | 1699 | if (phy_type != NES_PHY_TYPE_PUMA_1G) { |
1705 | u32temp |= 0x00200000; | 1700 | u32temp |= 0x00200000; |
1706 | nes_write_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + | 1701 | nes_write_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + |
1707 | (0x200 * (nesdev->mac_index & 1)), u32temp); | 1702 | (0x200 * (nesdev->mac_index & 1)), u32temp); |
1708 | } | 1703 | } |
1709 | 1704 | ||
1710 | u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + | ||
1711 | (0x200 * (nesdev->mac_index & 1))); | ||
1712 | |||
1713 | if ((u32temp&0x0f1f0000) == 0x0f0f0000) { | ||
1714 | if (nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_IRIS) { | ||
1715 | nes_init_phy(nesdev); | ||
1716 | nes_read_10G_phy_reg(nesdev, nesdev->nesadapter->phy_index[nesdev->mac_index], 1, 1); | ||
1717 | temp_phy_data = (u16)nes_read_indexed(nesdev, | ||
1718 | NES_IDX_MAC_MDIO_CONTROL); | ||
1719 | u32temp = 20; | ||
1720 | do { | ||
1721 | nes_read_10G_phy_reg(nesdev, nesdev->nesadapter->phy_index[nesdev->mac_index], 1, 1); | ||
1722 | phy_data = (u16)nes_read_indexed(nesdev, | ||
1723 | NES_IDX_MAC_MDIO_CONTROL); | ||
1724 | if ((phy_data == temp_phy_data) || (!(--u32temp))) | ||
1725 | break; | ||
1726 | temp_phy_data = phy_data; | ||
1727 | } while (1); | ||
1728 | if (phy_data & 4) { | ||
1729 | nes_debug(NES_DBG_INIT, "The Link is UP!!.\n"); | ||
1730 | nesvnic->linkup = 1; | ||
1731 | } else { | ||
1732 | nes_debug(NES_DBG_INIT, "The Link is DOWN!!.\n"); | ||
1733 | } | ||
1734 | } else { | ||
1735 | nes_debug(NES_DBG_INIT, "The Link is UP!!.\n"); | ||
1736 | nesvnic->linkup = 1; | ||
1737 | } | ||
1738 | } else if (nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_PUMA_1G) { | ||
1739 | nes_debug(NES_DBG_INIT, "mac_index=%d, logical_port=%d, u32temp=0x%04X, PCI_FUNC=%d\n", | ||
1740 | nesdev->mac_index, nesvnic->logical_port, u32temp, PCI_FUNC(nesdev->pcidev->devfn)); | ||
1741 | if (((nesdev->mac_index < 2) && ((u32temp&0x01010000) == 0x01010000)) || | ||
1742 | ((nesdev->mac_index > 1) && ((u32temp&0x02020000) == 0x02020000))) { | ||
1743 | nes_debug(NES_DBG_INIT, "The Link is UP!!.\n"); | ||
1744 | nesvnic->linkup = 1; | ||
1745 | } | ||
1746 | } | ||
1747 | /* clear the MAC interrupt status, assumes direct logical to physical mapping */ | 1705 | /* clear the MAC interrupt status, assumes direct logical to physical mapping */ |
1748 | u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index)); | 1706 | u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index)); |
1749 | nes_debug(NES_DBG_INIT, "Phy interrupt status = 0x%X.\n", u32temp); | 1707 | nes_debug(NES_DBG_INIT, "Phy interrupt status = 0x%X.\n", u32temp); |
1750 | nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index), u32temp); | 1708 | nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index), u32temp); |
1751 | 1709 | ||
1752 | if (nesdev->nesadapter->phy_type[nesdev->mac_index] != NES_PHY_TYPE_IRIS) | 1710 | nes_init_phy(nesdev); |
1753 | nes_init_phy(nesdev); | ||
1754 | 1711 | ||
1755 | } | 1712 | } |
1756 | 1713 | ||
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c index 64d3136e3747..815725f886c4 100644 --- a/drivers/infiniband/hw/nes/nes_verbs.c +++ b/drivers/infiniband/hw/nes/nes_verbs.c | |||
@@ -228,7 +228,7 @@ static int nes_bind_mw(struct ib_qp *ibqp, struct ib_mw *ibmw, | |||
228 | /* Check for SQ overflow */ | 228 | /* Check for SQ overflow */ |
229 | if (((head + (2 * qsize) - nesqp->hwqp.sq_tail) % qsize) == (qsize - 1)) { | 229 | if (((head + (2 * qsize) - nesqp->hwqp.sq_tail) % qsize) == (qsize - 1)) { |
230 | spin_unlock_irqrestore(&nesqp->lock, flags); | 230 | spin_unlock_irqrestore(&nesqp->lock, flags); |
231 | return -EINVAL; | 231 | return -ENOMEM; |
232 | } | 232 | } |
233 | 233 | ||
234 | wqe = &nesqp->hwqp.sq_vbase[head]; | 234 | wqe = &nesqp->hwqp.sq_vbase[head]; |
@@ -3294,7 +3294,7 @@ static int nes_post_send(struct ib_qp *ibqp, struct ib_send_wr *ib_wr, | |||
3294 | 3294 | ||
3295 | /* Check for SQ overflow */ | 3295 | /* Check for SQ overflow */ |
3296 | if (((head + (2 * qsize) - nesqp->hwqp.sq_tail) % qsize) == (qsize - 1)) { | 3296 | if (((head + (2 * qsize) - nesqp->hwqp.sq_tail) % qsize) == (qsize - 1)) { |
3297 | err = -EINVAL; | 3297 | err = -ENOMEM; |
3298 | break; | 3298 | break; |
3299 | } | 3299 | } |
3300 | 3300 | ||
@@ -3577,7 +3577,7 @@ static int nes_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *ib_wr, | |||
3577 | } | 3577 | } |
3578 | /* Check for RQ overflow */ | 3578 | /* Check for RQ overflow */ |
3579 | if (((head + (2 * qsize) - nesqp->hwqp.rq_tail) % qsize) == (qsize - 1)) { | 3579 | if (((head + (2 * qsize) - nesqp->hwqp.rq_tail) % qsize) == (qsize - 1)) { |
3580 | err = -EINVAL; | 3580 | err = -ENOMEM; |
3581 | break; | 3581 | break; |
3582 | } | 3582 | } |
3583 | 3583 | ||