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authorLinus Torvalds <torvalds@linux-foundation.org>2009-04-09 19:42:26 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-09 19:42:26 -0400
commit0534c8cb5c8a8a954751fa01eef7831a475a9ec5 (patch)
tree1ba3037634378966a78a35bbdec66b384fbff20d /drivers/infiniband
parent54f93b74cf8c575bb89f9bf32a40a39b83ace1e9 (diff)
parent07306c0b98a9a0399bff1b91229b4c3b55912189 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: RDMA/nes: Add support for new SFP+ PHY RDMA/nes: Add wide_ppm_offset parm for switch compatibility RDMA/nes: Fix SFP+ PHY initialization RDMA/nes: Fix nes_nic_cm_xmit() error handling RDMA/nes: Fix error handling issues RDMA/nes: Fix incorrect casts on 32-bit architectures IPoIB: Document newish features RDMA/cma: Create cm id even when IB port is down RDMA/cma: Use rate from IPoIB broadcast when joining IPoIB multicast groups IPoIB: Avoid free_netdev() BUG when destroying a child interface mlx4_core: Don't leak mailbox for SET_PORT on Ethernet ports RDMA/cxgb3: Release dependent resources only when endpoint memory is freed. RDMA/cxgb3: Handle EEH events IB/mlx4: Use pgprot_writecombine() for BlueFlame pages
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/core/cma.c45
-rw-r--r--drivers/infiniband/hw/cxgb3/cxio_hal.c10
-rw-r--r--drivers/infiniband/hw/cxgb3/cxio_hal.h6
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch.c11
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch.h5
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_cm.c116
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_cm.h3
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_qp.c4
-rw-r--r--drivers/infiniband/hw/mlx4/main.c3
-rw-r--r--drivers/infiniband/hw/nes/nes.h4
-rw-r--r--drivers/infiniband/hw/nes/nes_cm.c22
-rw-r--r--drivers/infiniband/hw/nes/nes_cm.h1
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c389
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.h2
-rw-r--r--drivers/infiniband/hw/nes/nes_nic.c52
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_vlan.c25
16 files changed, 394 insertions, 304 deletions
diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c
index 2a2e50871b40..851de83ff455 100644
--- a/drivers/infiniband/core/cma.c
+++ b/drivers/infiniband/core/cma.c
@@ -297,21 +297,25 @@ static void cma_detach_from_dev(struct rdma_id_private *id_priv)
297 id_priv->cma_dev = NULL; 297 id_priv->cma_dev = NULL;
298} 298}
299 299
300static int cma_set_qkey(struct ib_device *device, u8 port_num, 300static int cma_set_qkey(struct rdma_id_private *id_priv)
301 enum rdma_port_space ps,
302 struct rdma_dev_addr *dev_addr, u32 *qkey)
303{ 301{
304 struct ib_sa_mcmember_rec rec; 302 struct ib_sa_mcmember_rec rec;
305 int ret = 0; 303 int ret = 0;
306 304
307 switch (ps) { 305 if (id_priv->qkey)
306 return 0;
307
308 switch (id_priv->id.ps) {
308 case RDMA_PS_UDP: 309 case RDMA_PS_UDP:
309 *qkey = RDMA_UDP_QKEY; 310 id_priv->qkey = RDMA_UDP_QKEY;
310 break; 311 break;
311 case RDMA_PS_IPOIB: 312 case RDMA_PS_IPOIB:
312 ib_addr_get_mgid(dev_addr, &rec.mgid); 313 ib_addr_get_mgid(&id_priv->id.route.addr.dev_addr, &rec.mgid);
313 ret = ib_sa_get_mcmember_rec(device, port_num, &rec.mgid, &rec); 314 ret = ib_sa_get_mcmember_rec(id_priv->id.device,
314 *qkey = be32_to_cpu(rec.qkey); 315 id_priv->id.port_num, &rec.mgid,
316 &rec);
317 if (!ret)
318 id_priv->qkey = be32_to_cpu(rec.qkey);
315 break; 319 break;
316 default: 320 default:
317 break; 321 break;
@@ -341,12 +345,7 @@ static int cma_acquire_dev(struct rdma_id_private *id_priv)
341 ret = ib_find_cached_gid(cma_dev->device, &gid, 345 ret = ib_find_cached_gid(cma_dev->device, &gid,
342 &id_priv->id.port_num, NULL); 346 &id_priv->id.port_num, NULL);
343 if (!ret) { 347 if (!ret) {
344 ret = cma_set_qkey(cma_dev->device, 348 cma_attach_to_dev(id_priv, cma_dev);
345 id_priv->id.port_num,
346 id_priv->id.ps, dev_addr,
347 &id_priv->qkey);
348 if (!ret)
349 cma_attach_to_dev(id_priv, cma_dev);
350 break; 349 break;
351 } 350 }
352 } 351 }
@@ -578,6 +577,10 @@ static int cma_ib_init_qp_attr(struct rdma_id_private *id_priv,
578 *qp_attr_mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT; 577 *qp_attr_mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT;
579 578
580 if (cma_is_ud_ps(id_priv->id.ps)) { 579 if (cma_is_ud_ps(id_priv->id.ps)) {
580 ret = cma_set_qkey(id_priv);
581 if (ret)
582 return ret;
583
581 qp_attr->qkey = id_priv->qkey; 584 qp_attr->qkey = id_priv->qkey;
582 *qp_attr_mask |= IB_QP_QKEY; 585 *qp_attr_mask |= IB_QP_QKEY;
583 } else { 586 } else {
@@ -2201,6 +2204,12 @@ static int cma_sidr_rep_handler(struct ib_cm_id *cm_id,
2201 event.status = ib_event->param.sidr_rep_rcvd.status; 2204 event.status = ib_event->param.sidr_rep_rcvd.status;
2202 break; 2205 break;
2203 } 2206 }
2207 ret = cma_set_qkey(id_priv);
2208 if (ret) {
2209 event.event = RDMA_CM_EVENT_ADDR_ERROR;
2210 event.status = -EINVAL;
2211 break;
2212 }
2204 if (id_priv->qkey != rep->qkey) { 2213 if (id_priv->qkey != rep->qkey) {
2205 event.event = RDMA_CM_EVENT_UNREACHABLE; 2214 event.event = RDMA_CM_EVENT_UNREACHABLE;
2206 event.status = -EINVAL; 2215 event.status = -EINVAL;
@@ -2480,10 +2489,14 @@ static int cma_send_sidr_rep(struct rdma_id_private *id_priv,
2480 const void *private_data, int private_data_len) 2489 const void *private_data, int private_data_len)
2481{ 2490{
2482 struct ib_cm_sidr_rep_param rep; 2491 struct ib_cm_sidr_rep_param rep;
2492 int ret;
2483 2493
2484 memset(&rep, 0, sizeof rep); 2494 memset(&rep, 0, sizeof rep);
2485 rep.status = status; 2495 rep.status = status;
2486 if (status == IB_SIDR_SUCCESS) { 2496 if (status == IB_SIDR_SUCCESS) {
2497 ret = cma_set_qkey(id_priv);
2498 if (ret)
2499 return ret;
2487 rep.qp_num = id_priv->qp_num; 2500 rep.qp_num = id_priv->qp_num;
2488 rep.qkey = id_priv->qkey; 2501 rep.qkey = id_priv->qkey;
2489 } 2502 }
@@ -2713,6 +2726,10 @@ static int cma_join_ib_multicast(struct rdma_id_private *id_priv,
2713 IB_SA_MCMEMBER_REC_FLOW_LABEL | 2726 IB_SA_MCMEMBER_REC_FLOW_LABEL |
2714 IB_SA_MCMEMBER_REC_TRAFFIC_CLASS; 2727 IB_SA_MCMEMBER_REC_TRAFFIC_CLASS;
2715 2728
2729 if (id_priv->id.ps == RDMA_PS_IPOIB)
2730 comp_mask |= IB_SA_MCMEMBER_REC_RATE |
2731 IB_SA_MCMEMBER_REC_RATE_SELECTOR;
2732
2716 mc->multicast.ib = ib_sa_join_multicast(&sa_client, id_priv->id.device, 2733 mc->multicast.ib = ib_sa_join_multicast(&sa_client, id_priv->id.device,
2717 id_priv->id.port_num, &rec, 2734 id_priv->id.port_num, &rec,
2718 comp_mask, GFP_KERNEL, 2735 comp_mask, GFP_KERNEL,
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c
index a4a82bff7100..8d71086f5a1c 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.c
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c
@@ -152,7 +152,7 @@ static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
152 sge_cmd = qpid << 8 | 3; 152 sge_cmd = qpid << 8 | 3;
153 wqe->sge_cmd = cpu_to_be64(sge_cmd); 153 wqe->sge_cmd = cpu_to_be64(sge_cmd);
154 skb->priority = CPL_PRIORITY_CONTROL; 154 skb->priority = CPL_PRIORITY_CONTROL;
155 return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); 155 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
156} 156}
157 157
158int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) 158int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
@@ -571,7 +571,7 @@ static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
571 (unsigned long long) rdev_p->ctrl_qp.dma_addr, 571 (unsigned long long) rdev_p->ctrl_qp.dma_addr,
572 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2); 572 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
573 skb->priority = CPL_PRIORITY_CONTROL; 573 skb->priority = CPL_PRIORITY_CONTROL;
574 return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); 574 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
575err: 575err:
576 kfree_skb(skb); 576 kfree_skb(skb);
577 return err; 577 return err;
@@ -701,7 +701,7 @@ static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
701 u32 stag_idx; 701 u32 stag_idx;
702 u32 wptr; 702 u32 wptr;
703 703
704 if (rdev_p->flags) 704 if (cxio_fatal_error(rdev_p))
705 return -EIO; 705 return -EIO;
706 706
707 stag_state = stag_state > 0; 707 stag_state = stag_state > 0;
@@ -858,7 +858,7 @@ int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
858 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size); 858 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
859 wqe->irs = cpu_to_be32(attr->irs); 859 wqe->irs = cpu_to_be32(attr->irs);
860 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */ 860 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */
861 return (cxgb3_ofld_send(rdev_p->t3cdev_p, skb)); 861 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
862} 862}
863 863
864void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb) 864void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
@@ -1041,9 +1041,9 @@ void cxio_rdev_close(struct cxio_rdev *rdev_p)
1041 cxio_hal_pblpool_destroy(rdev_p); 1041 cxio_hal_pblpool_destroy(rdev_p);
1042 cxio_hal_rqtpool_destroy(rdev_p); 1042 cxio_hal_rqtpool_destroy(rdev_p);
1043 list_del(&rdev_p->entry); 1043 list_del(&rdev_p->entry);
1044 rdev_p->t3cdev_p->ulp = NULL;
1045 cxio_hal_destroy_ctrl_qp(rdev_p); 1044 cxio_hal_destroy_ctrl_qp(rdev_p);
1046 cxio_hal_destroy_resource(rdev_p->rscp); 1045 cxio_hal_destroy_resource(rdev_p->rscp);
1046 rdev_p->t3cdev_p->ulp = NULL;
1047 } 1047 }
1048} 1048}
1049 1049
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.h b/drivers/infiniband/hw/cxgb3/cxio_hal.h
index 094a66d1480c..bfd03bf8be54 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.h
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.h
@@ -115,6 +115,11 @@ struct cxio_rdev {
115#define CXIO_ERROR_FATAL 1 115#define CXIO_ERROR_FATAL 1
116}; 116};
117 117
118static inline int cxio_fatal_error(struct cxio_rdev *rdev_p)
119{
120 return rdev_p->flags & CXIO_ERROR_FATAL;
121}
122
118static inline int cxio_num_stags(struct cxio_rdev *rdev_p) 123static inline int cxio_num_stags(struct cxio_rdev *rdev_p)
119{ 124{
120 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5)); 125 return min((int)T3_MAX_NUM_STAG, (int)((rdev_p->rnic_info.tpt_top - rdev_p->rnic_info.tpt_base) >> 5));
@@ -188,6 +193,7 @@ void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count);
188void cxio_flush_hw_cq(struct t3_cq *cq); 193void cxio_flush_hw_cq(struct t3_cq *cq);
189int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe, 194int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
190 u8 *cqe_flushed, u64 *cookie, u32 *credit); 195 u8 *cqe_flushed, u64 *cookie, u32 *credit);
196int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb);
191 197
192#define MOD "iw_cxgb3: " 198#define MOD "iw_cxgb3: "
193#define PDBG(fmt, args...) pr_debug(MOD fmt, ## args) 199#define PDBG(fmt, args...) pr_debug(MOD fmt, ## args)
diff --git a/drivers/infiniband/hw/cxgb3/iwch.c b/drivers/infiniband/hw/cxgb3/iwch.c
index 37a4fc264a07..26fc0a4eaa74 100644
--- a/drivers/infiniband/hw/cxgb3/iwch.c
+++ b/drivers/infiniband/hw/cxgb3/iwch.c
@@ -165,12 +165,19 @@ static void close_rnic_dev(struct t3cdev *tdev)
165static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error) 165static void iwch_err_handler(struct t3cdev *tdev, u32 status, u32 error)
166{ 166{
167 struct cxio_rdev *rdev = tdev->ulp; 167 struct cxio_rdev *rdev = tdev->ulp;
168 struct iwch_dev *rnicp = rdev_to_iwch_dev(rdev);
169 struct ib_event event;
168 170
169 if (status == OFFLOAD_STATUS_DOWN) 171 if (status == OFFLOAD_STATUS_DOWN) {
170 rdev->flags = CXIO_ERROR_FATAL; 172 rdev->flags = CXIO_ERROR_FATAL;
171 173
172 return; 174 event.device = &rnicp->ibdev;
175 event.event = IB_EVENT_DEVICE_FATAL;
176 event.element.port_num = 0;
177 ib_dispatch_event(&event);
178 }
173 179
180 return;
174} 181}
175 182
176static int __init iwch_init_module(void) 183static int __init iwch_init_module(void)
diff --git a/drivers/infiniband/hw/cxgb3/iwch.h b/drivers/infiniband/hw/cxgb3/iwch.h
index 3773453b2cf0..84735506333f 100644
--- a/drivers/infiniband/hw/cxgb3/iwch.h
+++ b/drivers/infiniband/hw/cxgb3/iwch.h
@@ -117,6 +117,11 @@ static inline struct iwch_dev *to_iwch_dev(struct ib_device *ibdev)
117 return container_of(ibdev, struct iwch_dev, ibdev); 117 return container_of(ibdev, struct iwch_dev, ibdev);
118} 118}
119 119
120static inline struct iwch_dev *rdev_to_iwch_dev(struct cxio_rdev *rdev)
121{
122 return container_of(rdev, struct iwch_dev, rdev);
123}
124
120static inline int t3b_device(const struct iwch_dev *rhp) 125static inline int t3b_device(const struct iwch_dev *rhp)
121{ 126{
122 return rhp->rdev.t3cdev_p->type == T3B; 127 return rhp->rdev.t3cdev_p->type == T3B;
diff --git a/drivers/infiniband/hw/cxgb3/iwch_cm.c b/drivers/infiniband/hw/cxgb3/iwch_cm.c
index 8699947aaf6c..fef3f1ae7225 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_cm.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_cm.c
@@ -139,6 +139,38 @@ static void stop_ep_timer(struct iwch_ep *ep)
139 put_ep(&ep->com); 139 put_ep(&ep->com);
140} 140}
141 141
142int iwch_l2t_send(struct t3cdev *tdev, struct sk_buff *skb, struct l2t_entry *l2e)
143{
144 int error = 0;
145 struct cxio_rdev *rdev;
146
147 rdev = (struct cxio_rdev *)tdev->ulp;
148 if (cxio_fatal_error(rdev)) {
149 kfree_skb(skb);
150 return -EIO;
151 }
152 error = l2t_send(tdev, skb, l2e);
153 if (error)
154 kfree_skb(skb);
155 return error;
156}
157
158int iwch_cxgb3_ofld_send(struct t3cdev *tdev, struct sk_buff *skb)
159{
160 int error = 0;
161 struct cxio_rdev *rdev;
162
163 rdev = (struct cxio_rdev *)tdev->ulp;
164 if (cxio_fatal_error(rdev)) {
165 kfree_skb(skb);
166 return -EIO;
167 }
168 error = cxgb3_ofld_send(tdev, skb);
169 if (error)
170 kfree_skb(skb);
171 return error;
172}
173
142static void release_tid(struct t3cdev *tdev, u32 hwtid, struct sk_buff *skb) 174static void release_tid(struct t3cdev *tdev, u32 hwtid, struct sk_buff *skb)
143{ 175{
144 struct cpl_tid_release *req; 176 struct cpl_tid_release *req;
@@ -150,7 +182,7 @@ static void release_tid(struct t3cdev *tdev, u32 hwtid, struct sk_buff *skb)
150 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); 182 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
151 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, hwtid)); 183 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, hwtid));
152 skb->priority = CPL_PRIORITY_SETUP; 184 skb->priority = CPL_PRIORITY_SETUP;
153 cxgb3_ofld_send(tdev, skb); 185 iwch_cxgb3_ofld_send(tdev, skb);
154 return; 186 return;
155} 187}
156 188
@@ -172,8 +204,7 @@ int iwch_quiesce_tid(struct iwch_ep *ep)
172 req->val = cpu_to_be64(1 << S_TCB_RX_QUIESCE); 204 req->val = cpu_to_be64(1 << S_TCB_RX_QUIESCE);
173 205
174 skb->priority = CPL_PRIORITY_DATA; 206 skb->priority = CPL_PRIORITY_DATA;
175 cxgb3_ofld_send(ep->com.tdev, skb); 207 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
176 return 0;
177} 208}
178 209
179int iwch_resume_tid(struct iwch_ep *ep) 210int iwch_resume_tid(struct iwch_ep *ep)
@@ -194,8 +225,7 @@ int iwch_resume_tid(struct iwch_ep *ep)
194 req->val = 0; 225 req->val = 0;
195 226
196 skb->priority = CPL_PRIORITY_DATA; 227 skb->priority = CPL_PRIORITY_DATA;
197 cxgb3_ofld_send(ep->com.tdev, skb); 228 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
198 return 0;
199} 229}
200 230
201static void set_emss(struct iwch_ep *ep, u16 opt) 231static void set_emss(struct iwch_ep *ep, u16 opt)
@@ -252,18 +282,22 @@ static void *alloc_ep(int size, gfp_t gfp)
252 282
253void __free_ep(struct kref *kref) 283void __free_ep(struct kref *kref)
254{ 284{
255 struct iwch_ep_common *epc; 285 struct iwch_ep *ep;
256 epc = container_of(kref, struct iwch_ep_common, kref); 286 ep = container_of(container_of(kref, struct iwch_ep_common, kref),
257 PDBG("%s ep %p state %s\n", __func__, epc, states[state_read(epc)]); 287 struct iwch_ep, com);
258 kfree(epc); 288 PDBG("%s ep %p state %s\n", __func__, ep, states[state_read(&ep->com)]);
289 if (ep->com.flags & RELEASE_RESOURCES) {
290 cxgb3_remove_tid(ep->com.tdev, (void *)ep, ep->hwtid);
291 dst_release(ep->dst);
292 l2t_release(L2DATA(ep->com.tdev), ep->l2t);
293 }
294 kfree(ep);
259} 295}
260 296
261static void release_ep_resources(struct iwch_ep *ep) 297static void release_ep_resources(struct iwch_ep *ep)
262{ 298{
263 PDBG("%s ep %p tid %d\n", __func__, ep, ep->hwtid); 299 PDBG("%s ep %p tid %d\n", __func__, ep, ep->hwtid);
264 cxgb3_remove_tid(ep->com.tdev, (void *)ep, ep->hwtid); 300 ep->com.flags |= RELEASE_RESOURCES;
265 dst_release(ep->dst);
266 l2t_release(L2DATA(ep->com.tdev), ep->l2t);
267 put_ep(&ep->com); 301 put_ep(&ep->com);
268} 302}
269 303
@@ -382,7 +416,7 @@ static void abort_arp_failure(struct t3cdev *dev, struct sk_buff *skb)
382 416
383 PDBG("%s t3cdev %p\n", __func__, dev); 417 PDBG("%s t3cdev %p\n", __func__, dev);
384 req->cmd = CPL_ABORT_NO_RST; 418 req->cmd = CPL_ABORT_NO_RST;
385 cxgb3_ofld_send(dev, skb); 419 iwch_cxgb3_ofld_send(dev, skb);
386} 420}
387 421
388static int send_halfclose(struct iwch_ep *ep, gfp_t gfp) 422static int send_halfclose(struct iwch_ep *ep, gfp_t gfp)
@@ -402,8 +436,7 @@ static int send_halfclose(struct iwch_ep *ep, gfp_t gfp)
402 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_OFLD_CLOSE_CON)); 436 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_OFLD_CLOSE_CON));
403 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid)); 437 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid));
404 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_CON_REQ, ep->hwtid)); 438 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_CON_REQ, ep->hwtid));
405 l2t_send(ep->com.tdev, skb, ep->l2t); 439 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
406 return 0;
407} 440}
408 441
409static int send_abort(struct iwch_ep *ep, struct sk_buff *skb, gfp_t gfp) 442static int send_abort(struct iwch_ep *ep, struct sk_buff *skb, gfp_t gfp)
@@ -424,8 +457,7 @@ static int send_abort(struct iwch_ep *ep, struct sk_buff *skb, gfp_t gfp)
424 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid)); 457 req->wr.wr_lo = htonl(V_WR_TID(ep->hwtid));
425 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ABORT_REQ, ep->hwtid)); 458 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_ABORT_REQ, ep->hwtid));
426 req->cmd = CPL_ABORT_SEND_RST; 459 req->cmd = CPL_ABORT_SEND_RST;
427 l2t_send(ep->com.tdev, skb, ep->l2t); 460 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
428 return 0;
429} 461}
430 462
431static int send_connect(struct iwch_ep *ep) 463static int send_connect(struct iwch_ep *ep)
@@ -469,8 +501,7 @@ static int send_connect(struct iwch_ep *ep)
469 req->opt0l = htonl(opt0l); 501 req->opt0l = htonl(opt0l);
470 req->params = 0; 502 req->params = 0;
471 req->opt2 = htonl(opt2); 503 req->opt2 = htonl(opt2);
472 l2t_send(ep->com.tdev, skb, ep->l2t); 504 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
473 return 0;
474} 505}
475 506
476static void send_mpa_req(struct iwch_ep *ep, struct sk_buff *skb) 507static void send_mpa_req(struct iwch_ep *ep, struct sk_buff *skb)
@@ -527,7 +558,7 @@ static void send_mpa_req(struct iwch_ep *ep, struct sk_buff *skb)
527 req->sndseq = htonl(ep->snd_seq); 558 req->sndseq = htonl(ep->snd_seq);
528 BUG_ON(ep->mpa_skb); 559 BUG_ON(ep->mpa_skb);
529 ep->mpa_skb = skb; 560 ep->mpa_skb = skb;
530 l2t_send(ep->com.tdev, skb, ep->l2t); 561 iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
531 start_ep_timer(ep); 562 start_ep_timer(ep);
532 state_set(&ep->com, MPA_REQ_SENT); 563 state_set(&ep->com, MPA_REQ_SENT);
533 return; 564 return;
@@ -578,8 +609,7 @@ static int send_mpa_reject(struct iwch_ep *ep, const void *pdata, u8 plen)
578 req->sndseq = htonl(ep->snd_seq); 609 req->sndseq = htonl(ep->snd_seq);
579 BUG_ON(ep->mpa_skb); 610 BUG_ON(ep->mpa_skb);
580 ep->mpa_skb = skb; 611 ep->mpa_skb = skb;
581 l2t_send(ep->com.tdev, skb, ep->l2t); 612 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
582 return 0;
583} 613}
584 614
585static int send_mpa_reply(struct iwch_ep *ep, const void *pdata, u8 plen) 615static int send_mpa_reply(struct iwch_ep *ep, const void *pdata, u8 plen)
@@ -630,8 +660,7 @@ static int send_mpa_reply(struct iwch_ep *ep, const void *pdata, u8 plen)
630 req->sndseq = htonl(ep->snd_seq); 660 req->sndseq = htonl(ep->snd_seq);
631 ep->mpa_skb = skb; 661 ep->mpa_skb = skb;
632 state_set(&ep->com, MPA_REP_SENT); 662 state_set(&ep->com, MPA_REP_SENT);
633 l2t_send(ep->com.tdev, skb, ep->l2t); 663 return iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
634 return 0;
635} 664}
636 665
637static int act_establish(struct t3cdev *tdev, struct sk_buff *skb, void *ctx) 666static int act_establish(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
@@ -795,7 +824,7 @@ static int update_rx_credits(struct iwch_ep *ep, u32 credits)
795 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RX_DATA_ACK, ep->hwtid)); 824 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RX_DATA_ACK, ep->hwtid));
796 req->credit_dack = htonl(V_RX_CREDITS(credits) | V_RX_FORCE_ACK(1)); 825 req->credit_dack = htonl(V_RX_CREDITS(credits) | V_RX_FORCE_ACK(1));
797 skb->priority = CPL_PRIORITY_ACK; 826 skb->priority = CPL_PRIORITY_ACK;
798 cxgb3_ofld_send(ep->com.tdev, skb); 827 iwch_cxgb3_ofld_send(ep->com.tdev, skb);
799 return credits; 828 return credits;
800} 829}
801 830
@@ -1127,8 +1156,8 @@ static int abort_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1127 * We get 2 abort replies from the HW. The first one must 1156 * We get 2 abort replies from the HW. The first one must
1128 * be ignored except for scribbling that we need one more. 1157 * be ignored except for scribbling that we need one more.
1129 */ 1158 */
1130 if (!(ep->flags & ABORT_REQ_IN_PROGRESS)) { 1159 if (!(ep->com.flags & ABORT_REQ_IN_PROGRESS)) {
1131 ep->flags |= ABORT_REQ_IN_PROGRESS; 1160 ep->com.flags |= ABORT_REQ_IN_PROGRESS;
1132 return CPL_RET_BUF_DONE; 1161 return CPL_RET_BUF_DONE;
1133 } 1162 }
1134 1163
@@ -1203,8 +1232,7 @@ static int listen_start(struct iwch_listen_ep *ep)
1203 req->opt1 = htonl(V_CONN_POLICY(CPL_CONN_POLICY_ASK)); 1232 req->opt1 = htonl(V_CONN_POLICY(CPL_CONN_POLICY_ASK));
1204 1233
1205 skb->priority = 1; 1234 skb->priority = 1;
1206 cxgb3_ofld_send(ep->com.tdev, skb); 1235 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
1207 return 0;
1208} 1236}
1209 1237
1210static int pass_open_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx) 1238static int pass_open_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
@@ -1237,8 +1265,7 @@ static int listen_stop(struct iwch_listen_ep *ep)
1237 req->cpu_idx = 0; 1265 req->cpu_idx = 0;
1238 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, ep->stid)); 1266 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, ep->stid));
1239 skb->priority = 1; 1267 skb->priority = 1;
1240 cxgb3_ofld_send(ep->com.tdev, skb); 1268 return iwch_cxgb3_ofld_send(ep->com.tdev, skb);
1241 return 0;
1242} 1269}
1243 1270
1244static int close_listsrv_rpl(struct t3cdev *tdev, struct sk_buff *skb, 1271static int close_listsrv_rpl(struct t3cdev *tdev, struct sk_buff *skb,
@@ -1286,7 +1313,7 @@ static void accept_cr(struct iwch_ep *ep, __be32 peer_ip, struct sk_buff *skb)
1286 rpl->opt2 = htonl(opt2); 1313 rpl->opt2 = htonl(opt2);
1287 rpl->rsvd = rpl->opt2; /* workaround for HW bug */ 1314 rpl->rsvd = rpl->opt2; /* workaround for HW bug */
1288 skb->priority = CPL_PRIORITY_SETUP; 1315 skb->priority = CPL_PRIORITY_SETUP;
1289 l2t_send(ep->com.tdev, skb, ep->l2t); 1316 iwch_l2t_send(ep->com.tdev, skb, ep->l2t);
1290 1317
1291 return; 1318 return;
1292} 1319}
@@ -1315,7 +1342,7 @@ static void reject_cr(struct t3cdev *tdev, u32 hwtid, __be32 peer_ip,
1315 rpl->opt0l_status = htonl(CPL_PASS_OPEN_REJECT); 1342 rpl->opt0l_status = htonl(CPL_PASS_OPEN_REJECT);
1316 rpl->opt2 = 0; 1343 rpl->opt2 = 0;
1317 rpl->rsvd = rpl->opt2; 1344 rpl->rsvd = rpl->opt2;
1318 cxgb3_ofld_send(tdev, skb); 1345 iwch_cxgb3_ofld_send(tdev, skb);
1319 } 1346 }
1320} 1347}
1321 1348
@@ -1534,8 +1561,8 @@ static int peer_abort(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1534 * We get 2 peer aborts from the HW. The first one must 1561 * We get 2 peer aborts from the HW. The first one must
1535 * be ignored except for scribbling that we need one more. 1562 * be ignored except for scribbling that we need one more.
1536 */ 1563 */
1537 if (!(ep->flags & PEER_ABORT_IN_PROGRESS)) { 1564 if (!(ep->com.flags & PEER_ABORT_IN_PROGRESS)) {
1538 ep->flags |= PEER_ABORT_IN_PROGRESS; 1565 ep->com.flags |= PEER_ABORT_IN_PROGRESS;
1539 return CPL_RET_BUF_DONE; 1566 return CPL_RET_BUF_DONE;
1540 } 1567 }
1541 1568
@@ -1613,7 +1640,7 @@ static int peer_abort(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
1613 rpl->wr.wr_lo = htonl(V_WR_TID(ep->hwtid)); 1640 rpl->wr.wr_lo = htonl(V_WR_TID(ep->hwtid));
1614 OPCODE_TID(rpl) = htonl(MK_OPCODE_TID(CPL_ABORT_RPL, ep->hwtid)); 1641 OPCODE_TID(rpl) = htonl(MK_OPCODE_TID(CPL_ABORT_RPL, ep->hwtid));
1615 rpl->cmd = CPL_ABORT_NO_RST; 1642 rpl->cmd = CPL_ABORT_NO_RST;
1616 cxgb3_ofld_send(ep->com.tdev, rpl_skb); 1643 iwch_cxgb3_ofld_send(ep->com.tdev, rpl_skb);
1617out: 1644out:
1618 if (release) 1645 if (release)
1619 release_ep_resources(ep); 1646 release_ep_resources(ep);
@@ -2017,8 +2044,11 @@ int iwch_destroy_listen(struct iw_cm_id *cm_id)
2017 ep->com.rpl_done = 0; 2044 ep->com.rpl_done = 0;
2018 ep->com.rpl_err = 0; 2045 ep->com.rpl_err = 0;
2019 err = listen_stop(ep); 2046 err = listen_stop(ep);
2047 if (err)
2048 goto done;
2020 wait_event(ep->com.waitq, ep->com.rpl_done); 2049 wait_event(ep->com.waitq, ep->com.rpl_done);
2021 cxgb3_free_stid(ep->com.tdev, ep->stid); 2050 cxgb3_free_stid(ep->com.tdev, ep->stid);
2051done:
2022 err = ep->com.rpl_err; 2052 err = ep->com.rpl_err;
2023 cm_id->rem_ref(cm_id); 2053 cm_id->rem_ref(cm_id);
2024 put_ep(&ep->com); 2054 put_ep(&ep->com);
@@ -2030,12 +2060,22 @@ int iwch_ep_disconnect(struct iwch_ep *ep, int abrupt, gfp_t gfp)
2030 int ret=0; 2060 int ret=0;
2031 unsigned long flags; 2061 unsigned long flags;
2032 int close = 0; 2062 int close = 0;
2063 int fatal = 0;
2064 struct t3cdev *tdev;
2065 struct cxio_rdev *rdev;
2033 2066
2034 spin_lock_irqsave(&ep->com.lock, flags); 2067 spin_lock_irqsave(&ep->com.lock, flags);
2035 2068
2036 PDBG("%s ep %p state %s, abrupt %d\n", __func__, ep, 2069 PDBG("%s ep %p state %s, abrupt %d\n", __func__, ep,
2037 states[ep->com.state], abrupt); 2070 states[ep->com.state], abrupt);
2038 2071
2072 tdev = (struct t3cdev *)ep->com.tdev;
2073 rdev = (struct cxio_rdev *)tdev->ulp;
2074 if (cxio_fatal_error(rdev)) {
2075 fatal = 1;
2076 close_complete_upcall(ep);
2077 ep->com.state = DEAD;
2078 }
2039 switch (ep->com.state) { 2079 switch (ep->com.state) {
2040 case MPA_REQ_WAIT: 2080 case MPA_REQ_WAIT:
2041 case MPA_REQ_SENT: 2081 case MPA_REQ_SENT:
@@ -2075,7 +2115,11 @@ int iwch_ep_disconnect(struct iwch_ep *ep, int abrupt, gfp_t gfp)
2075 ret = send_abort(ep, NULL, gfp); 2115 ret = send_abort(ep, NULL, gfp);
2076 else 2116 else
2077 ret = send_halfclose(ep, gfp); 2117 ret = send_halfclose(ep, gfp);
2118 if (ret)
2119 fatal = 1;
2078 } 2120 }
2121 if (fatal)
2122 release_ep_resources(ep);
2079 return ret; 2123 return ret;
2080} 2124}
2081 2125
diff --git a/drivers/infiniband/hw/cxgb3/iwch_cm.h b/drivers/infiniband/hw/cxgb3/iwch_cm.h
index d7c7e09f0996..43c0aea7eadc 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_cm.h
+++ b/drivers/infiniband/hw/cxgb3/iwch_cm.h
@@ -147,6 +147,7 @@ enum iwch_ep_state {
147enum iwch_ep_flags { 147enum iwch_ep_flags {
148 PEER_ABORT_IN_PROGRESS = (1 << 0), 148 PEER_ABORT_IN_PROGRESS = (1 << 0),
149 ABORT_REQ_IN_PROGRESS = (1 << 1), 149 ABORT_REQ_IN_PROGRESS = (1 << 1),
150 RELEASE_RESOURCES = (1 << 2),
150}; 151};
151 152
152struct iwch_ep_common { 153struct iwch_ep_common {
@@ -161,6 +162,7 @@ struct iwch_ep_common {
161 wait_queue_head_t waitq; 162 wait_queue_head_t waitq;
162 int rpl_done; 163 int rpl_done;
163 int rpl_err; 164 int rpl_err;
165 u32 flags;
164}; 166};
165 167
166struct iwch_listen_ep { 168struct iwch_listen_ep {
@@ -188,7 +190,6 @@ struct iwch_ep {
188 u16 plen; 190 u16 plen;
189 u32 ird; 191 u32 ird;
190 u32 ord; 192 u32 ord;
191 u32 flags;
192}; 193};
193 194
194static inline struct iwch_ep *to_ep(struct iw_cm_id *cm_id) 195static inline struct iwch_ep *to_ep(struct iw_cm_id *cm_id)
diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c
index c758fbd58478..2f546a625330 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_qp.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c
@@ -751,7 +751,7 @@ int iwch_post_zb_read(struct iwch_qp *qhp)
751 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)| 751 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)|
752 V_FW_RIWR_LEN(flit_cnt)); 752 V_FW_RIWR_LEN(flit_cnt));
753 skb->priority = CPL_PRIORITY_DATA; 753 skb->priority = CPL_PRIORITY_DATA;
754 return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb); 754 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
755} 755}
756 756
757/* 757/*
@@ -783,7 +783,7 @@ int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
783 V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG)); 783 V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
784 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid)); 784 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
785 skb->priority = CPL_PRIORITY_DATA; 785 skb->priority = CPL_PRIORITY_DATA;
786 return cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb); 786 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
787} 787}
788 788
789/* 789/*
diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c
index 2ccb9d31771f..ae3d7590346e 100644
--- a/drivers/infiniband/hw/mlx4/main.c
+++ b/drivers/infiniband/hw/mlx4/main.c
@@ -394,8 +394,7 @@ static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
394 PAGE_SIZE, vma->vm_page_prot)) 394 PAGE_SIZE, vma->vm_page_prot))
395 return -EAGAIN; 395 return -EAGAIN;
396 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) { 396 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
397 /* FIXME want pgprot_writecombine() for BlueFlame pages */ 397 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
398 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
399 398
400 if (io_remap_pfn_range(vma, vma->vm_start, 399 if (io_remap_pfn_range(vma, vma->vm_start,
401 to_mucontext(context)->uar.pfn + 400 to_mucontext(context)->uar.pfn +
diff --git a/drivers/infiniband/hw/nes/nes.h b/drivers/infiniband/hw/nes/nes.h
index 04b12ad23390..17621de54a9f 100644
--- a/drivers/infiniband/hw/nes/nes.h
+++ b/drivers/infiniband/hw/nes/nes.h
@@ -289,8 +289,8 @@ static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
289static inline void 289static inline void
290set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value) 290set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
291{ 291{
292 wqe_words[index] = cpu_to_le32((u32) ((unsigned long)value)); 292 wqe_words[index] = cpu_to_le32((u32) value);
293 wqe_words[index + 1] = cpu_to_le32((u32)(upper_32_bits((unsigned long)value))); 293 wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
294} 294}
295 295
296static inline void 296static inline void
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c
index 52425154acd4..dbd9a75474e3 100644
--- a/drivers/infiniband/hw/nes/nes_cm.c
+++ b/drivers/infiniband/hw/nes/nes_cm.c
@@ -426,6 +426,7 @@ int schedule_nes_timer(struct nes_cm_node *cm_node, struct sk_buff *skb,
426 if (type == NES_TIMER_TYPE_CLOSE) { 426 if (type == NES_TIMER_TYPE_CLOSE) {
427 new_send->timetosend += (HZ/10); 427 new_send->timetosend += (HZ/10);
428 if (cm_node->recv_entry) { 428 if (cm_node->recv_entry) {
429 kfree(new_send);
429 WARN_ON(1); 430 WARN_ON(1);
430 return -EINVAL; 431 return -EINVAL;
431 } 432 }
@@ -445,8 +446,8 @@ int schedule_nes_timer(struct nes_cm_node *cm_node, struct sk_buff *skb,
445 if (ret != NETDEV_TX_OK) { 446 if (ret != NETDEV_TX_OK) {
446 nes_debug(NES_DBG_CM, "Error sending packet %p " 447 nes_debug(NES_DBG_CM, "Error sending packet %p "
447 "(jiffies = %lu)\n", new_send, jiffies); 448 "(jiffies = %lu)\n", new_send, jiffies);
448 atomic_dec(&new_send->skb->users);
449 new_send->timetosend = jiffies; 449 new_send->timetosend = jiffies;
450 ret = NETDEV_TX_OK;
450 } else { 451 } else {
451 cm_packets_sent++; 452 cm_packets_sent++;
452 if (!send_retrans) { 453 if (!send_retrans) {
@@ -630,7 +631,6 @@ static void nes_cm_timer_tick(unsigned long pass)
630 nes_debug(NES_DBG_CM, "rexmit failed for " 631 nes_debug(NES_DBG_CM, "rexmit failed for "
631 "node=%p\n", cm_node); 632 "node=%p\n", cm_node);
632 cm_packets_bounced++; 633 cm_packets_bounced++;
633 atomic_dec(&send_entry->skb->users);
634 send_entry->retrycount--; 634 send_entry->retrycount--;
635 nexttimeout = jiffies + NES_SHORT_TIME; 635 nexttimeout = jiffies + NES_SHORT_TIME;
636 settimer = 1; 636 settimer = 1;
@@ -666,11 +666,6 @@ static void nes_cm_timer_tick(unsigned long pass)
666 666
667 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); 667 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags);
668 rem_ref_cm_node(cm_node->cm_core, cm_node); 668 rem_ref_cm_node(cm_node->cm_core, cm_node);
669 if (ret != NETDEV_TX_OK) {
670 nes_debug(NES_DBG_CM, "rexmit failed for cm_node=%p\n",
671 cm_node);
672 break;
673 }
674 } 669 }
675 670
676 if (settimer) { 671 if (settimer) {
@@ -1262,7 +1257,6 @@ static int rem_ref_cm_node(struct nes_cm_core *cm_core,
1262 cm_node->nesqp = NULL; 1257 cm_node->nesqp = NULL;
1263 } 1258 }
1264 1259
1265 cm_node->freed = 1;
1266 kfree(cm_node); 1260 kfree(cm_node);
1267 return 0; 1261 return 0;
1268} 1262}
@@ -1999,13 +1993,17 @@ static struct nes_cm_node *mini_cm_connect(struct nes_cm_core *cm_core,
1999 if (loopbackremotelistener == NULL) { 1993 if (loopbackremotelistener == NULL) {
2000 create_event(cm_node, NES_CM_EVENT_ABORTED); 1994 create_event(cm_node, NES_CM_EVENT_ABORTED);
2001 } else { 1995 } else {
2002 atomic_inc(&cm_loopbacks);
2003 loopback_cm_info = *cm_info; 1996 loopback_cm_info = *cm_info;
2004 loopback_cm_info.loc_port = cm_info->rem_port; 1997 loopback_cm_info.loc_port = cm_info->rem_port;
2005 loopback_cm_info.rem_port = cm_info->loc_port; 1998 loopback_cm_info.rem_port = cm_info->loc_port;
2006 loopback_cm_info.cm_id = loopbackremotelistener->cm_id; 1999 loopback_cm_info.cm_id = loopbackremotelistener->cm_id;
2007 loopbackremotenode = make_cm_node(cm_core, nesvnic, 2000 loopbackremotenode = make_cm_node(cm_core, nesvnic,
2008 &loopback_cm_info, loopbackremotelistener); 2001 &loopback_cm_info, loopbackremotelistener);
2002 if (!loopbackremotenode) {
2003 rem_ref_cm_node(cm_node->cm_core, cm_node);
2004 return NULL;
2005 }
2006 atomic_inc(&cm_loopbacks);
2009 loopbackremotenode->loopbackpartner = cm_node; 2007 loopbackremotenode->loopbackpartner = cm_node;
2010 loopbackremotenode->tcp_cntxt.rcv_wscale = 2008 loopbackremotenode->tcp_cntxt.rcv_wscale =
2011 NES_CM_DEFAULT_RCV_WND_SCALE; 2009 NES_CM_DEFAULT_RCV_WND_SCALE;
@@ -2690,6 +2688,7 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2690 struct ib_mr *ibmr = NULL; 2688 struct ib_mr *ibmr = NULL;
2691 struct ib_phys_buf ibphysbuf; 2689 struct ib_phys_buf ibphysbuf;
2692 struct nes_pd *nespd; 2690 struct nes_pd *nespd;
2691 u64 tagged_offset;
2693 2692
2694 2693
2695 2694
@@ -2755,10 +2754,11 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2755 ibphysbuf.addr = nesqp->ietf_frame_pbase; 2754 ibphysbuf.addr = nesqp->ietf_frame_pbase;
2756 ibphysbuf.size = conn_param->private_data_len + 2755 ibphysbuf.size = conn_param->private_data_len +
2757 sizeof(struct ietf_mpa_frame); 2756 sizeof(struct ietf_mpa_frame);
2757 tagged_offset = (u64)(unsigned long)nesqp->ietf_frame;
2758 ibmr = nesibdev->ibdev.reg_phys_mr((struct ib_pd *)nespd, 2758 ibmr = nesibdev->ibdev.reg_phys_mr((struct ib_pd *)nespd,
2759 &ibphysbuf, 1, 2759 &ibphysbuf, 1,
2760 IB_ACCESS_LOCAL_WRITE, 2760 IB_ACCESS_LOCAL_WRITE,
2761 (u64 *)&nesqp->ietf_frame); 2761 &tagged_offset);
2762 if (!ibmr) { 2762 if (!ibmr) {
2763 nes_debug(NES_DBG_CM, "Unable to register memory region" 2763 nes_debug(NES_DBG_CM, "Unable to register memory region"
2764 "for lSMM for cm_node = %p \n", 2764 "for lSMM for cm_node = %p \n",
@@ -2782,7 +2782,7 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
2782 sizeof(struct ietf_mpa_frame)); 2782 sizeof(struct ietf_mpa_frame));
2783 set_wqe_64bit_value(wqe->wqe_words, 2783 set_wqe_64bit_value(wqe->wqe_words,
2784 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX, 2784 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX,
2785 (u64)nesqp->ietf_frame); 2785 (u64)(unsigned long)nesqp->ietf_frame);
2786 wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] = 2786 wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] =
2787 cpu_to_le32(conn_param->private_data_len + 2787 cpu_to_le32(conn_param->private_data_len +
2788 sizeof(struct ietf_mpa_frame)); 2788 sizeof(struct ietf_mpa_frame));
diff --git a/drivers/infiniband/hw/nes/nes_cm.h b/drivers/infiniband/hw/nes/nes_cm.h
index d5f778202eb7..80bba1892571 100644
--- a/drivers/infiniband/hw/nes/nes_cm.h
+++ b/drivers/infiniband/hw/nes/nes_cm.h
@@ -298,7 +298,6 @@ struct nes_cm_node {
298 struct nes_vnic *nesvnic; 298 struct nes_vnic *nesvnic;
299 int apbvt_set; 299 int apbvt_set;
300 int accept_pend; 300 int accept_pend;
301 int freed;
302 struct list_head timer_entry; 301 struct list_head timer_entry;
303 struct list_head reset_entry; 302 struct list_head reset_entry;
304 struct nes_qp *nesqp; 303 struct nes_qp *nesqp;
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index 52e734042b8e..d6fc9ae44062 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -46,6 +46,10 @@ static unsigned int nes_lro_max_aggr = NES_LRO_MAX_AGGR;
46module_param(nes_lro_max_aggr, uint, 0444); 46module_param(nes_lro_max_aggr, uint, 0444);
47MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation"); 47MODULE_PARM_DESC(nes_lro_max_aggr, "NIC LRO max packet aggregation");
48 48
49static int wide_ppm_offset;
50module_param(wide_ppm_offset, int, 0644);
51MODULE_PARM_DESC(wide_ppm_offset, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
52
49static u32 crit_err_count; 53static u32 crit_err_count;
50u32 int_mod_timer_init; 54u32 int_mod_timer_init;
51u32 int_mod_cq_depth_256; 55u32 int_mod_cq_depth_256;
@@ -546,8 +550,11 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
546 msleep(1); 550 msleep(1);
547 } 551 }
548 if (int_cnt > 1) { 552 if (int_cnt > 1) {
553 u32 sds;
549 spin_lock_irqsave(&nesadapter->phy_lock, flags); 554 spin_lock_irqsave(&nesadapter->phy_lock, flags);
550 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, 0x0000F088); 555 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
556 sds |= 0x00000040;
557 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
551 mh_detected++; 558 mh_detected++;
552 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET); 559 reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
553 reset_value |= 0x0000003d; 560 reset_value |= 0x0000003d;
@@ -736,39 +743,49 @@ static int nes_init_serdes(struct nes_device *nesdev, u8 hw_rev, u8 port_count,
736{ 743{
737 int i; 744 int i;
738 u32 u32temp; 745 u32 u32temp;
739 u32 serdes_common_control; 746 u32 sds;
740 747
741 if (hw_rev != NE020_REV) { 748 if (hw_rev != NE020_REV) {
742 /* init serdes 0 */ 749 /* init serdes 0 */
750 if (wide_ppm_offset && (nesadapter->phy_type[0] == NES_PHY_TYPE_CX4))
751 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000FFFAA);
752 else
753 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
743 754
744 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000FF);
745 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { 755 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
746 serdes_common_control = nes_read_indexed(nesdev, 756 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0);
747 NES_IDX_ETH_SERDES_COMMON_CONTROL0); 757 sds |= 0x00000100;
748 serdes_common_control |= 0x000000100; 758 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds);
749 nes_write_indexed(nesdev,
750 NES_IDX_ETH_SERDES_COMMON_CONTROL0,
751 serdes_common_control);
752 } else if (!OneG_Mode) {
753 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
754 } 759 }
755 if (((port_count > 1) && 760 if (!OneG_Mode)
756 (nesadapter->phy_type[0] != NES_PHY_TYPE_PUMA_1G)) || 761 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0, 0x11110000);
757 ((port_count > 2) && 762
758 (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G))) { 763 if (port_count < 2)
759 /* init serdes 1 */ 764 return 0;
760 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF); 765
761 if (nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) { 766 /* init serdes 1 */
762 serdes_common_control = nes_read_indexed(nesdev, 767 switch (nesadapter->phy_type[1]) {
763 NES_IDX_ETH_SERDES_COMMON_CONTROL1); 768 case NES_PHY_TYPE_ARGUS:
764 serdes_common_control |= 0x000000100; 769 case NES_PHY_TYPE_SFP_D:
765 nes_write_indexed(nesdev, 770 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x00000000);
766 NES_IDX_ETH_SERDES_COMMON_CONTROL1, 771 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP1, 0x00000000);
767 serdes_common_control); 772 break;
768 } else if (!OneG_Mode) { 773 case NES_PHY_TYPE_CX4:
769 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000); 774 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
770 } 775 sds &= 0xFFFFFFBF;
776 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
777 if (wide_ppm_offset)
778 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000FFFAA);
779 else
780 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL1, 0x000000FF);
781 break;
782 case NES_PHY_TYPE_PUMA_1G:
783 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1);
784 sds |= 0x000000100;
785 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL1, sds);
771 } 786 }
787 if (!OneG_Mode)
788 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1, 0x11110000);
772 } else { 789 } else {
773 /* init serdes 0 */ 790 /* init serdes 0 */
774 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008); 791 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
@@ -1259,203 +1276,162 @@ int nes_init_phy(struct nes_device *nesdev)
1259{ 1276{
1260 struct nes_adapter *nesadapter = nesdev->nesadapter; 1277 struct nes_adapter *nesadapter = nesdev->nesadapter;
1261 u32 counter = 0; 1278 u32 counter = 0;
1262 u32 sds_common_control0; 1279 u32 sds;
1263 u32 mac_index = nesdev->mac_index; 1280 u32 mac_index = nesdev->mac_index;
1264 u32 tx_config = 0; 1281 u32 tx_config = 0;
1265 u16 phy_data; 1282 u16 phy_data;
1266 u32 temp_phy_data = 0; 1283 u32 temp_phy_data = 0;
1267 u32 temp_phy_data2 = 0; 1284 u32 temp_phy_data2 = 0;
1268 u32 i = 0; 1285 u8 phy_type = nesadapter->phy_type[mac_index];
1286 u8 phy_index = nesadapter->phy_index[mac_index];
1269 1287
1270 if ((nesadapter->OneG_Mode) && 1288 if ((nesadapter->OneG_Mode) &&
1271 (nesadapter->phy_type[mac_index] != NES_PHY_TYPE_PUMA_1G)) { 1289 (phy_type != NES_PHY_TYPE_PUMA_1G)) {
1272 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index); 1290 nes_debug(NES_DBG_PHY, "1G PHY, mac_index = %d.\n", mac_index);
1273 if (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_1G) { 1291 if (phy_type == NES_PHY_TYPE_1G) {
1274 printk(PFX "%s: Programming mdc config for 1G\n", __func__);
1275 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG); 1292 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1276 tx_config &= 0xFFFFFFE3; 1293 tx_config &= 0xFFFFFFE3;
1277 tx_config |= 0x04; 1294 tx_config |= 0x04;
1278 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config); 1295 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1279 } 1296 }
1280 1297
1281 nes_read_1G_phy_reg(nesdev, 1, nesadapter->phy_index[mac_index], &phy_data); 1298 nes_read_1G_phy_reg(nesdev, 1, phy_index, &phy_data);
1282 nes_debug(NES_DBG_PHY, "Phy data from register 1 phy address %u = 0x%X.\n", 1299 nes_write_1G_phy_reg(nesdev, 23, phy_index, 0xb000);
1283 nesadapter->phy_index[mac_index], phy_data);
1284 nes_write_1G_phy_reg(nesdev, 23, nesadapter->phy_index[mac_index], 0xb000);
1285 1300
1286 /* Reset the PHY */ 1301 /* Reset the PHY */
1287 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], 0x8000); 1302 nes_write_1G_phy_reg(nesdev, 0, phy_index, 0x8000);
1288 udelay(100); 1303 udelay(100);
1289 counter = 0; 1304 counter = 0;
1290 do { 1305 do {
1291 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1306 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1292 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data); 1307 if (counter++ > 100)
1293 if (counter++ > 100) break; 1308 break;
1294 } while (phy_data & 0x8000); 1309 } while (phy_data & 0x8000);
1295 1310
1296 /* Setting no phy loopback */ 1311 /* Setting no phy loopback */
1297 phy_data &= 0xbfff; 1312 phy_data &= 0xbfff;
1298 phy_data |= 0x1140; 1313 phy_data |= 0x1140;
1299 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data); 1314 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
1300 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data); 1315 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1301 nes_debug(NES_DBG_PHY, "Phy data from register 0 = 0x%X.\n", phy_data); 1316 nes_read_1G_phy_reg(nesdev, 0x17, phy_index, &phy_data);
1302 1317 nes_read_1G_phy_reg(nesdev, 0x1e, phy_index, &phy_data);
1303 nes_read_1G_phy_reg(nesdev, 0x17, nesadapter->phy_index[mac_index], &phy_data);
1304 nes_debug(NES_DBG_PHY, "Phy data from register 0x17 = 0x%X.\n", phy_data);
1305
1306 nes_read_1G_phy_reg(nesdev, 0x1e, nesadapter->phy_index[mac_index], &phy_data);
1307 nes_debug(NES_DBG_PHY, "Phy data from register 0x1e = 0x%X.\n", phy_data);
1308 1318
1309 /* Setting the interrupt mask */ 1319 /* Setting the interrupt mask */
1310 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data); 1320 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1311 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data); 1321 nes_write_1G_phy_reg(nesdev, 0x19, phy_index, 0xffee);
1312 nes_write_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], 0xffee); 1322 nes_read_1G_phy_reg(nesdev, 0x19, phy_index, &phy_data);
1313
1314 nes_read_1G_phy_reg(nesdev, 0x19, nesadapter->phy_index[mac_index], &phy_data);
1315 nes_debug(NES_DBG_PHY, "Phy data from register 0x19 = 0x%X.\n", phy_data);
1316 1323
1317 /* turning on flow control */ 1324 /* turning on flow control */
1318 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data); 1325 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1319 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data); 1326 nes_write_1G_phy_reg(nesdev, 4, phy_index, (phy_data & ~(0x03E0)) | 0xc00);
1320 nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], 1327 nes_read_1G_phy_reg(nesdev, 4, phy_index, &phy_data);
1321 (phy_data & ~(0x03E0)) | 0xc00);
1322 /* nes_write_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index],
1323 phy_data | 0xc00); */
1324 nes_read_1G_phy_reg(nesdev, 4, nesadapter->phy_index[mac_index], &phy_data);
1325 nes_debug(NES_DBG_PHY, "Phy data from register 0x4 = 0x%X.\n", phy_data);
1326
1327 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1328 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1329 /* Clear Half duplex */
1330 nes_write_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index],
1331 phy_data & ~(0x0100));
1332 nes_read_1G_phy_reg(nesdev, 9, nesadapter->phy_index[mac_index], &phy_data);
1333 nes_debug(NES_DBG_PHY, "Phy data from register 0x9 = 0x%X.\n", phy_data);
1334
1335 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], &phy_data);
1336 nes_write_1G_phy_reg(nesdev, 0, nesadapter->phy_index[mac_index], phy_data | 0x0300);
1337 } else {
1338 if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_IRIS) ||
1339 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
1340 /* setup 10G MDIO operation */
1341 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1342 tx_config &= 0xFFFFFFE3;
1343 tx_config |= 0x15;
1344 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1345 }
1346 if ((nesadapter->phy_type[mac_index] == NES_PHY_TYPE_ARGUS)) {
1347 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee);
1348 1328
1349 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1329 /* Clear Half duplex */
1350 mdelay(10); 1330 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1351 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee); 1331 nes_write_1G_phy_reg(nesdev, 9, phy_index, phy_data & ~(0x0100));
1352 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1332 nes_read_1G_phy_reg(nesdev, 9, phy_index, &phy_data);
1353 1333
1354 /* 1334 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1355 * if firmware is already running (like from a 1335 nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data | 0x0300);
1356 * driver un-load/load, don't do anything.
1357 */
1358 if (temp_phy_data == temp_phy_data2) {
1359 /* configure QT2505 AMCC PHY */
1360 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0x0000, 0x8000);
1361 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0000);
1362 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc302, 0x0044);
1363 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc318, 0x0052);
1364 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc319, 0x0008);
1365 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc31a, 0x0098);
1366 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0026, 0x0E00);
1367 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0027, 0x0001);
1368 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0x0028, 0xA528);
1369 1336
1370 /* 1337 return 0;
1371 * remove micro from reset; chip boots from ROM, 1338 }
1372 * uploads EEPROM f/w image, uC executes f/w
1373 */
1374 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc300, 0x0002);
1375 1339
1376 /* 1340 if ((phy_type == NES_PHY_TYPE_IRIS) ||
1377 * wait for heart beat to start to 1341 (phy_type == NES_PHY_TYPE_ARGUS) ||
1378 * know loading is done 1342 (phy_type == NES_PHY_TYPE_SFP_D)) {
1379 */ 1343 /* setup 10G MDIO operation */
1380 counter = 0; 1344 tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
1381 do { 1345 tx_config &= 0xFFFFFFE3;
1382 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee); 1346 tx_config |= 0x15;
1383 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1347 nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
1384 if (counter++ > 1000) { 1348 }
1385 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from heartbeat check <this is bad!!!> \n"); 1349 if ((phy_type == NES_PHY_TYPE_ARGUS) ||
1386 break; 1350 (phy_type == NES_PHY_TYPE_SFP_D)) {
1387 } 1351 /* Check firmware heartbeat */
1388 mdelay(100); 1352 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1389 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7ee); 1353 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1390 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1354 udelay(1500);
1391 } while ((temp_phy_data2 == temp_phy_data)); 1355 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1356 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1357
1358 if (temp_phy_data != temp_phy_data2)
1359 return 0;
1392 1360
1393 /* 1361 /* no heartbeat, configure the PHY */
1394 * wait for tracking to start to know 1362 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0x0000, 0x8000);
1395 * f/w is good to go 1363 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0000);
1396 */ 1364 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc316, 0x000A);
1397 counter = 0; 1365 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc318, 0x0052);
1398 do { 1366 if (phy_type == NES_PHY_TYPE_ARGUS) {
1399 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x3, 0xd7fd); 1367 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x000C);
1400 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 1368 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0008);
1401 if (counter++ > 1000) { 1369 } else {
1402 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from status check <this is bad!!!> \n"); 1370 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc302, 0x0004);
1403 break; 1371 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc319, 0x0038);
1404 } 1372 }
1405 mdelay(1000); 1373 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc31a, 0x0098);
1406 /* 1374 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0026, 0x0E00);
1407 * nes_debug(NES_DBG_PHY, "AMCC PHY- phy_status not ready yet = 0x%02X\n", 1375 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0027, 0x0001);
1408 * temp_phy_data);
1409 */
1410 } while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
1411
1412 /* set LOS Control invert RXLOSB_I_PADINV */
1413 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd003, 0x0000);
1414 /* set LOS Control to mask of RXLOSB_I */
1415 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xc314, 0x0042);
1416 /* set LED1 to input mode (LED1 and LED2 share same LED) */
1417 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd006, 0x0007);
1418 /* set LED2 to RX link_status and activity */
1419 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd007, 0x000A);
1420 /* set LED3 to RX link_status */
1421 nes_write_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 0x1, 0xd008, 0x0009);
1422 1376
1423 /* 1377 /* setup LEDs */
1424 * reset the res-calibration on t2 1378 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd006, 0x0007);
1425 * serdes; ensures it is stable after 1379 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd007, 0x000A);
1426 * the amcc phy is stable 1380 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd008, 0x0009);
1427 */
1428 1381
1429 sds_common_control0 = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0); 1382 nes_write_10G_phy_reg(nesdev, phy_index, 0x3, 0x0028, 0xA528);
1430 sds_common_control0 |= 0x1;
1431 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
1432 1383
1433 /* release the res-calibration reset */ 1384 /* Bring PHY out of reset */
1434 sds_common_control0 &= 0xfffffffe; 1385 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc300, 0x0002);
1435 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, sds_common_control0);
1436 1386
1437 i = 0; 1387 /* Check for heartbeat */
1438 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040) 1388 counter = 0;
1439 && (i++ < 5000)) { 1389 mdelay(690);
1440 /* mdelay(1); */ 1390 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1441 } 1391 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1392 do {
1393 if (counter++ > 150) {
1394 nes_debug(NES_DBG_PHY, "No PHY heartbeat\n");
1395 break;
1396 }
1397 mdelay(1);
1398 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7ee);
1399 temp_phy_data2 = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1400 } while ((temp_phy_data2 == temp_phy_data));
1442 1401
1443 /* 1402 /* wait for tracking */
1444 * wait for link train done before moving on, 1403 counter = 0;
1445 * or will get an interupt storm 1404 do {
1446 */ 1405 nes_read_10G_phy_reg(nesdev, phy_index, 0x3, 0xd7fd);
1447 counter = 0; 1406 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
1448 do { 1407 if (counter++ > 300) {
1449 temp_phy_data = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 + 1408 nes_debug(NES_DBG_PHY, "PHY did not track\n");
1450 (0x200 * (nesdev->mac_index & 1))); 1409 break;
1451 if (counter++ > 1000) {
1452 nes_debug(NES_DBG_PHY, "AMCC PHY- breaking from link train wait <this is bad, link didnt train!!!>\n");
1453 break;
1454 }
1455 mdelay(1);
1456 } while (((temp_phy_data & 0x0f1f0000) != 0x0f0f0000));
1457 } 1410 }
1458 } 1411 mdelay(10);
1412 } while (((temp_phy_data & 0xff) != 0x50) && ((temp_phy_data & 0xff) != 0x70));
1413
1414 /* setup signal integrity */
1415 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xd003, 0x0000);
1416 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00D, 0x00FE);
1417 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00E, 0x0032);
1418 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xF00F, 0x0002);
1419 nes_write_10G_phy_reg(nesdev, phy_index, 0x1, 0xc314, 0x0063);
1420
1421 /* reset serdes */
1422 sds = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1423 mac_index * 0x200);
1424 sds |= 0x1;
1425 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1426 mac_index * 0x200, sds);
1427 sds &= 0xfffffffe;
1428 nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0 +
1429 mac_index * 0x200, sds);
1430
1431 counter = 0;
1432 while (((nes_read32(nesdev->regs + NES_SOFTWARE_RESET) & 0x00000040) != 0x00000040)
1433 && (counter++ < 5000))
1434 ;
1459 } 1435 }
1460 return 0; 1436 return 0;
1461} 1437}
@@ -2359,6 +2335,7 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2359 u16 temp_phy_data; 2335 u16 temp_phy_data;
2360 u32 pcs_val = 0x0f0f0000; 2336 u32 pcs_val = 0x0f0f0000;
2361 u32 pcs_mask = 0x0f1f0000; 2337 u32 pcs_mask = 0x0f1f0000;
2338 u32 cdr_ctrl;
2362 2339
2363 spin_lock_irqsave(&nesadapter->phy_lock, flags); 2340 spin_lock_irqsave(&nesadapter->phy_lock, flags);
2364 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) { 2341 if (nesadapter->mac_sw_state[mac_number] != NES_MAC_SW_IDLE) {
@@ -2473,6 +2450,7 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2473 break; 2450 break;
2474 2451
2475 case NES_PHY_TYPE_ARGUS: 2452 case NES_PHY_TYPE_ARGUS:
2453 case NES_PHY_TYPE_SFP_D:
2476 /* clear the alarms */ 2454 /* clear the alarms */
2477 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008); 2455 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0x0008);
2478 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001); 2456 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 4, 0xc001);
@@ -2483,19 +2461,18 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2483 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004); 2461 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9004);
2484 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005); 2462 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9005);
2485 /* check link status */ 2463 /* check link status */
2486 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1); 2464 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 0x9003);
2487 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 2465 temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2488 u32temp = 100;
2489 do {
2490 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 1, 1);
2491 2466
2492 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL); 2467 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2493 if ((phy_data == temp_phy_data) || (!(--u32temp))) 2468 nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2494 break; 2469 nes_read_10G_phy_reg(nesdev, nesadapter->phy_index[mac_index], 3, 0x0021);
2495 temp_phy_data = phy_data; 2470 phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
2496 } while (1); 2471
2472 phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
2473
2497 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n", 2474 nes_debug(NES_DBG_PHY, "%s: Phy data = 0x%04X, link was %s.\n",
2498 __func__, phy_data, nesadapter->mac_link_down ? "DOWN" : "UP"); 2475 __func__, phy_data, nesadapter->mac_link_down[mac_index] ? "DOWN" : "UP");
2499 break; 2476 break;
2500 2477
2501 case NES_PHY_TYPE_PUMA_1G: 2478 case NES_PHY_TYPE_PUMA_1G:
@@ -2511,6 +2488,17 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2511 } 2488 }
2512 2489
2513 if (phy_data & 0x0004) { 2490 if (phy_data & 0x0004) {
2491 if (wide_ppm_offset &&
2492 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2493 (nesadapter->hw_rev != NE020_REV)) {
2494 cdr_ctrl = nes_read_indexed(nesdev,
2495 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2496 mac_index * 0x200);
2497 nes_write_indexed(nesdev,
2498 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2499 mac_index * 0x200,
2500 cdr_ctrl | 0x000F0000);
2501 }
2514 nesadapter->mac_link_down[mac_index] = 0; 2502 nesadapter->mac_link_down[mac_index] = 0;
2515 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) { 2503 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2516 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n", 2504 nes_debug(NES_DBG_PHY, "The Link is UP!!. linkup was %d\n",
@@ -2525,6 +2513,17 @@ static void nes_process_mac_intr(struct nes_device *nesdev, u32 mac_number)
2525 } 2513 }
2526 } 2514 }
2527 } else { 2515 } else {
2516 if (wide_ppm_offset &&
2517 (nesadapter->phy_type[mac_index] == NES_PHY_TYPE_CX4) &&
2518 (nesadapter->hw_rev != NE020_REV)) {
2519 cdr_ctrl = nes_read_indexed(nesdev,
2520 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2521 mac_index * 0x200);
2522 nes_write_indexed(nesdev,
2523 NES_IDX_ETH_SERDES_CDR_CONTROL0 +
2524 mac_index * 0x200,
2525 cdr_ctrl & 0xFFF0FFFF);
2526 }
2528 nesadapter->mac_link_down[mac_index] = 1; 2527 nesadapter->mac_link_down[mac_index] = 1;
2529 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) { 2528 list_for_each_entry(nesvnic, &nesadapter->nesvnic_list[mac_index], list) {
2530 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n", 2529 nes_debug(NES_DBG_PHY, "The Link is Down!!. linkup was %d\n",
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h
index f41a8710d2a8..c3654c6383fe 100644
--- a/drivers/infiniband/hw/nes/nes_hw.h
+++ b/drivers/infiniband/hw/nes/nes_hw.h
@@ -35,12 +35,14 @@
35 35
36#include <linux/inet_lro.h> 36#include <linux/inet_lro.h>
37 37
38#define NES_PHY_TYPE_CX4 1
38#define NES_PHY_TYPE_1G 2 39#define NES_PHY_TYPE_1G 2
39#define NES_PHY_TYPE_IRIS 3 40#define NES_PHY_TYPE_IRIS 3
40#define NES_PHY_TYPE_ARGUS 4 41#define NES_PHY_TYPE_ARGUS 4
41#define NES_PHY_TYPE_PUMA_1G 5 42#define NES_PHY_TYPE_PUMA_1G 5
42#define NES_PHY_TYPE_PUMA_10G 6 43#define NES_PHY_TYPE_PUMA_10G 6
43#define NES_PHY_TYPE_GLADIUS 7 44#define NES_PHY_TYPE_GLADIUS 7
45#define NES_PHY_TYPE_SFP_D 8
44 46
45#define NES_MULTICAST_PF_MAX 8 47#define NES_MULTICAST_PF_MAX 8
46 48
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c
index ecb1f6fd6276..c6e6611d3016 100644
--- a/drivers/infiniband/hw/nes/nes_nic.c
+++ b/drivers/infiniband/hw/nes/nes_nic.c
@@ -1426,49 +1426,55 @@ static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd
1426 struct nes_vnic *nesvnic = netdev_priv(netdev); 1426 struct nes_vnic *nesvnic = netdev_priv(netdev);
1427 struct nes_device *nesdev = nesvnic->nesdev; 1427 struct nes_device *nesdev = nesvnic->nesdev;
1428 struct nes_adapter *nesadapter = nesdev->nesadapter; 1428 struct nes_adapter *nesadapter = nesdev->nesadapter;
1429 u32 mac_index = nesdev->mac_index;
1430 u8 phy_type = nesadapter->phy_type[mac_index];
1431 u8 phy_index = nesadapter->phy_index[mac_index];
1429 u16 phy_data; 1432 u16 phy_data;
1430 1433
1431 et_cmd->duplex = DUPLEX_FULL; 1434 et_cmd->duplex = DUPLEX_FULL;
1432 et_cmd->port = PORT_MII; 1435 et_cmd->port = PORT_MII;
1436 et_cmd->maxtxpkt = 511;
1437 et_cmd->maxrxpkt = 511;
1433 1438
1434 if (nesadapter->OneG_Mode) { 1439 if (nesadapter->OneG_Mode) {
1435 et_cmd->speed = SPEED_1000; 1440 et_cmd->speed = SPEED_1000;
1436 if (nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_PUMA_1G) { 1441 if (phy_type == NES_PHY_TYPE_PUMA_1G) {
1437 et_cmd->supported = SUPPORTED_1000baseT_Full; 1442 et_cmd->supported = SUPPORTED_1000baseT_Full;
1438 et_cmd->advertising = ADVERTISED_1000baseT_Full; 1443 et_cmd->advertising = ADVERTISED_1000baseT_Full;
1439 et_cmd->autoneg = AUTONEG_DISABLE; 1444 et_cmd->autoneg = AUTONEG_DISABLE;
1440 et_cmd->transceiver = XCVR_INTERNAL; 1445 et_cmd->transceiver = XCVR_INTERNAL;
1441 et_cmd->phy_address = nesdev->mac_index; 1446 et_cmd->phy_address = mac_index;
1442 } else { 1447 } else {
1443 et_cmd->supported = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg; 1448 et_cmd->supported = SUPPORTED_1000baseT_Full
1444 et_cmd->advertising = ADVERTISED_1000baseT_Full | ADVERTISED_Autoneg; 1449 | SUPPORTED_Autoneg;
1445 nes_read_1G_phy_reg(nesdev, 0, nesadapter->phy_index[nesdev->mac_index], &phy_data); 1450 et_cmd->advertising = ADVERTISED_1000baseT_Full
1451 | ADVERTISED_Autoneg;
1452 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1446 if (phy_data & 0x1000) 1453 if (phy_data & 0x1000)
1447 et_cmd->autoneg = AUTONEG_ENABLE; 1454 et_cmd->autoneg = AUTONEG_ENABLE;
1448 else 1455 else
1449 et_cmd->autoneg = AUTONEG_DISABLE; 1456 et_cmd->autoneg = AUTONEG_DISABLE;
1450 et_cmd->transceiver = XCVR_EXTERNAL; 1457 et_cmd->transceiver = XCVR_EXTERNAL;
1451 et_cmd->phy_address = nesadapter->phy_index[nesdev->mac_index]; 1458 et_cmd->phy_address = phy_index;
1452 } 1459 }
1460 return 0;
1461 }
1462 if ((phy_type == NES_PHY_TYPE_IRIS) ||
1463 (phy_type == NES_PHY_TYPE_ARGUS) ||
1464 (phy_type == NES_PHY_TYPE_SFP_D)) {
1465 et_cmd->transceiver = XCVR_EXTERNAL;
1466 et_cmd->port = PORT_FIBRE;
1467 et_cmd->supported = SUPPORTED_FIBRE;
1468 et_cmd->advertising = ADVERTISED_FIBRE;
1469 et_cmd->phy_address = phy_index;
1453 } else { 1470 } else {
1454 if ((nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_IRIS) || 1471 et_cmd->transceiver = XCVR_INTERNAL;
1455 (nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_ARGUS)) { 1472 et_cmd->supported = SUPPORTED_10000baseT_Full;
1456 et_cmd->transceiver = XCVR_EXTERNAL; 1473 et_cmd->advertising = ADVERTISED_10000baseT_Full;
1457 et_cmd->port = PORT_FIBRE; 1474 et_cmd->phy_address = mac_index;
1458 et_cmd->supported = SUPPORTED_FIBRE;
1459 et_cmd->advertising = ADVERTISED_FIBRE;
1460 et_cmd->phy_address = nesadapter->phy_index[nesdev->mac_index];
1461 } else {
1462 et_cmd->transceiver = XCVR_INTERNAL;
1463 et_cmd->supported = SUPPORTED_10000baseT_Full;
1464 et_cmd->advertising = ADVERTISED_10000baseT_Full;
1465 et_cmd->phy_address = nesdev->mac_index;
1466 }
1467 et_cmd->speed = SPEED_10000;
1468 et_cmd->autoneg = AUTONEG_DISABLE;
1469 } 1475 }
1470 et_cmd->maxtxpkt = 511; 1476 et_cmd->speed = SPEED_10000;
1471 et_cmd->maxrxpkt = 511; 1477 et_cmd->autoneg = AUTONEG_DISABLE;
1472 return 0; 1478 return 0;
1473} 1479}
1474 1480
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_vlan.c b/drivers/infiniband/ulp/ipoib/ipoib_vlan.c
index 5a76a5510350..4c57f329dd50 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_vlan.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_vlan.c
@@ -70,12 +70,14 @@ int ipoib_vlan_add(struct net_device *pdev, unsigned short pkey)
70 */ 70 */
71 if (ppriv->pkey == pkey) { 71 if (ppriv->pkey == pkey) {
72 result = -ENOTUNIQ; 72 result = -ENOTUNIQ;
73 priv = NULL;
73 goto err; 74 goto err;
74 } 75 }
75 76
76 list_for_each_entry(priv, &ppriv->child_intfs, list) { 77 list_for_each_entry(priv, &ppriv->child_intfs, list) {
77 if (priv->pkey == pkey) { 78 if (priv->pkey == pkey) {
78 result = -ENOTUNIQ; 79 result = -ENOTUNIQ;
80 priv = NULL;
79 goto err; 81 goto err;
80 } 82 }
81 } 83 }
@@ -96,7 +98,7 @@ int ipoib_vlan_add(struct net_device *pdev, unsigned short pkey)
96 98
97 result = ipoib_set_dev_features(priv, ppriv->ca); 99 result = ipoib_set_dev_features(priv, ppriv->ca);
98 if (result) 100 if (result)
99 goto device_init_failed; 101 goto err;
100 102
101 priv->pkey = pkey; 103 priv->pkey = pkey;
102 104
@@ -109,7 +111,7 @@ int ipoib_vlan_add(struct net_device *pdev, unsigned short pkey)
109 ipoib_warn(ppriv, "failed to initialize subinterface: " 111 ipoib_warn(ppriv, "failed to initialize subinterface: "
110 "device %s, port %d", 112 "device %s, port %d",
111 ppriv->ca->name, ppriv->port); 113 ppriv->ca->name, ppriv->port);
112 goto device_init_failed; 114 goto err;
113 } 115 }
114 116
115 result = register_netdevice(priv->dev); 117 result = register_netdevice(priv->dev);
@@ -146,19 +148,19 @@ sysfs_failed:
146register_failed: 148register_failed:
147 ipoib_dev_cleanup(priv->dev); 149 ipoib_dev_cleanup(priv->dev);
148 150
149device_init_failed:
150 free_netdev(priv->dev);
151
152err: 151err:
153 mutex_unlock(&ppriv->vlan_mutex); 152 mutex_unlock(&ppriv->vlan_mutex);
154 rtnl_unlock(); 153 rtnl_unlock();
154 if (priv)
155 free_netdev(priv->dev);
156
155 return result; 157 return result;
156} 158}
157 159
158int ipoib_vlan_delete(struct net_device *pdev, unsigned short pkey) 160int ipoib_vlan_delete(struct net_device *pdev, unsigned short pkey)
159{ 161{
160 struct ipoib_dev_priv *ppriv, *priv, *tpriv; 162 struct ipoib_dev_priv *ppriv, *priv, *tpriv;
161 int ret = -ENOENT; 163 struct net_device *dev = NULL;
162 164
163 if (!capable(CAP_NET_ADMIN)) 165 if (!capable(CAP_NET_ADMIN))
164 return -EPERM; 166 return -EPERM;
@@ -172,14 +174,17 @@ int ipoib_vlan_delete(struct net_device *pdev, unsigned short pkey)
172 unregister_netdevice(priv->dev); 174 unregister_netdevice(priv->dev);
173 ipoib_dev_cleanup(priv->dev); 175 ipoib_dev_cleanup(priv->dev);
174 list_del(&priv->list); 176 list_del(&priv->list);
175 free_netdev(priv->dev); 177 dev = priv->dev;
176
177 ret = 0;
178 break; 178 break;
179 } 179 }
180 } 180 }
181 mutex_unlock(&ppriv->vlan_mutex); 181 mutex_unlock(&ppriv->vlan_mutex);
182 rtnl_unlock(); 182 rtnl_unlock();
183 183
184 return ret; 184 if (dev) {
185 free_netdev(dev);
186 return 0;
187 }
188
189 return -ENODEV;
185} 190}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 21:24:24 -0500