aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/infiniband
diff options
context:
space:
mode:
authorDon Wood <donald.e.wood@intel.com>2009-09-05 23:36:38 -0400
committerRoland Dreier <rolandd@cisco.com>2009-09-05 23:36:38 -0400
commit4b281faec3ad00f7fb00080078321e4d819795eb (patch)
tree0d85e499fa7767847770c4da256467f1b5f3cfdc /drivers/infiniband
parent8b1c9dc4ba713985d33aba87c761bf71d5a96491 (diff)
RDMA/nes: Use flush mechanism to set status for wqe in error
When an asynchronous event occurs that requires a terminate, it is sometimes possible to identify the wqe in error. This change uses flush to get this information to the poll routine. The flush operation puts the status into the cqe. If this information is not available, it continues to use the more generic flush code as before. Signed-off-by: Don Wood <donald.e.wood@intel.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c54
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.h12
-rw-r--r--drivers/infiniband/hw/nes/nes_verbs.h2
3 files changed, 68 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index 297026f0c138..63a1a8e1e8a3 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -2944,6 +2944,7 @@ static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 a
2944 u16 ddp_seg_len; 2944 u16 ddp_seg_len;
2945 int copy_len = 0; 2945 int copy_len = 0;
2946 u8 is_tagged = 0; 2946 u8 is_tagged = 0;
2947 u8 flush_code = 0;
2947 struct nes_terminate_hdr *termhdr; 2948 struct nes_terminate_hdr *termhdr;
2948 2949
2949 termhdr = (struct nes_terminate_hdr *)nesqp->hwqp.q2_vbase; 2950 termhdr = (struct nes_terminate_hdr *)nesqp->hwqp.q2_vbase;
@@ -2983,19 +2984,23 @@ static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 a
2983 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG: 2984 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG:
2984 switch (iwarp_opcode(nesqp, aeq_info)) { 2985 switch (iwarp_opcode(nesqp, aeq_info)) {
2985 case IWARP_OPCODE_WRITE: 2986 case IWARP_OPCODE_WRITE:
2987 flush_code = IB_WC_LOC_PROT_ERR;
2986 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER; 2988 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
2987 termhdr->error_code = DDP_TAGGED_INV_STAG; 2989 termhdr->error_code = DDP_TAGGED_INV_STAG;
2988 break; 2990 break;
2989 default: 2991 default:
2992 flush_code = IB_WC_REM_ACCESS_ERR;
2990 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 2993 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
2991 termhdr->error_code = RDMAP_INV_STAG; 2994 termhdr->error_code = RDMAP_INV_STAG;
2992 } 2995 }
2993 break; 2996 break;
2994 case NES_AEQE_AEID_AMP_INVALID_STAG: 2997 case NES_AEQE_AEID_AMP_INVALID_STAG:
2998 flush_code = IB_WC_REM_ACCESS_ERR;
2995 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 2999 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
2996 termhdr->error_code = RDMAP_INV_STAG; 3000 termhdr->error_code = RDMAP_INV_STAG;
2997 break; 3001 break;
2998 case NES_AEQE_AEID_AMP_BAD_QP: 3002 case NES_AEQE_AEID_AMP_BAD_QP:
3003 flush_code = IB_WC_LOC_QP_OP_ERR;
2999 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER; 3004 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3000 termhdr->error_code = DDP_UNTAGGED_INV_QN; 3005 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3001 break; 3006 break;
@@ -3004,19 +3009,23 @@ static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 a
3004 switch (iwarp_opcode(nesqp, aeq_info)) { 3009 switch (iwarp_opcode(nesqp, aeq_info)) {
3005 case IWARP_OPCODE_SEND_INV: 3010 case IWARP_OPCODE_SEND_INV:
3006 case IWARP_OPCODE_SEND_SE_INV: 3011 case IWARP_OPCODE_SEND_SE_INV:
3012 flush_code = IB_WC_REM_OP_ERR;
3007 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP; 3013 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3008 termhdr->error_code = RDMAP_CANT_INV_STAG; 3014 termhdr->error_code = RDMAP_CANT_INV_STAG;
3009 break; 3015 break;
3010 default: 3016 default:
3017 flush_code = IB_WC_REM_ACCESS_ERR;
3011 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 3018 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3012 termhdr->error_code = RDMAP_INV_STAG; 3019 termhdr->error_code = RDMAP_INV_STAG;
3013 } 3020 }
3014 break; 3021 break;
3015 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION: 3022 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION:
3016 if (aeq_info & (NES_AEQE_Q2_DATA_ETHERNET | NES_AEQE_Q2_DATA_MPA)) { 3023 if (aeq_info & (NES_AEQE_Q2_DATA_ETHERNET | NES_AEQE_Q2_DATA_MPA)) {
3024 flush_code = IB_WC_LOC_PROT_ERR;
3017 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER; 3025 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3018 termhdr->error_code = DDP_TAGGED_BOUNDS; 3026 termhdr->error_code = DDP_TAGGED_BOUNDS;
3019 } else { 3027 } else {
3028 flush_code = IB_WC_REM_ACCESS_ERR;
3020 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 3029 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3021 termhdr->error_code = RDMAP_INV_BOUNDS; 3030 termhdr->error_code = RDMAP_INV_BOUNDS;
3022 } 3031 }
@@ -3024,57 +3033,69 @@ static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 a
3024 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION: 3033 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION:
3025 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 3034 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
3026 case NES_AEQE_AEID_PRIV_OPERATION_DENIED: 3035 case NES_AEQE_AEID_PRIV_OPERATION_DENIED:
3036 flush_code = IB_WC_REM_ACCESS_ERR;
3027 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 3037 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3028 termhdr->error_code = RDMAP_ACCESS; 3038 termhdr->error_code = RDMAP_ACCESS;
3029 break; 3039 break;
3030 case NES_AEQE_AEID_AMP_TO_WRAP: 3040 case NES_AEQE_AEID_AMP_TO_WRAP:
3041 flush_code = IB_WC_REM_ACCESS_ERR;
3031 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 3042 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3032 termhdr->error_code = RDMAP_TO_WRAP; 3043 termhdr->error_code = RDMAP_TO_WRAP;
3033 break; 3044 break;
3034 case NES_AEQE_AEID_AMP_BAD_PD: 3045 case NES_AEQE_AEID_AMP_BAD_PD:
3035 switch (iwarp_opcode(nesqp, aeq_info)) { 3046 switch (iwarp_opcode(nesqp, aeq_info)) {
3036 case IWARP_OPCODE_WRITE: 3047 case IWARP_OPCODE_WRITE:
3048 flush_code = IB_WC_LOC_PROT_ERR;
3037 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER; 3049 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3038 termhdr->error_code = DDP_TAGGED_UNASSOC_STAG; 3050 termhdr->error_code = DDP_TAGGED_UNASSOC_STAG;
3039 break; 3051 break;
3040 case IWARP_OPCODE_SEND_INV: 3052 case IWARP_OPCODE_SEND_INV:
3041 case IWARP_OPCODE_SEND_SE_INV: 3053 case IWARP_OPCODE_SEND_SE_INV:
3054 flush_code = IB_WC_REM_ACCESS_ERR;
3042 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 3055 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3043 termhdr->error_code = RDMAP_CANT_INV_STAG; 3056 termhdr->error_code = RDMAP_CANT_INV_STAG;
3044 break; 3057 break;
3045 default: 3058 default:
3059 flush_code = IB_WC_REM_ACCESS_ERR;
3046 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT; 3060 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT;
3047 termhdr->error_code = RDMAP_UNASSOC_STAG; 3061 termhdr->error_code = RDMAP_UNASSOC_STAG;
3048 } 3062 }
3049 break; 3063 break;
3050 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH: 3064 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH:
3065 flush_code = IB_WC_LOC_LEN_ERR;
3051 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP; 3066 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3052 termhdr->error_code = MPA_MARKER; 3067 termhdr->error_code = MPA_MARKER;
3053 break; 3068 break;
3054 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR: 3069 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR:
3070 flush_code = IB_WC_GENERAL_ERR;
3055 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP; 3071 termhdr->layer_etype = (LAYER_MPA << 4) | DDP_LLP;
3056 termhdr->error_code = MPA_CRC; 3072 termhdr->error_code = MPA_CRC;
3057 break; 3073 break;
3058 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE: 3074 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE:
3059 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL: 3075 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL:
3076 flush_code = IB_WC_LOC_LEN_ERR;
3060 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC; 3077 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3061 termhdr->error_code = DDP_CATASTROPHIC_LOCAL; 3078 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3062 break; 3079 break;
3063 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC: 3080 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC:
3064 case NES_AEQE_AEID_DDP_NO_L_BIT: 3081 case NES_AEQE_AEID_DDP_NO_L_BIT:
3082 flush_code = IB_WC_FATAL_ERR;
3065 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC; 3083 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_CATASTROPHIC;
3066 termhdr->error_code = DDP_CATASTROPHIC_LOCAL; 3084 termhdr->error_code = DDP_CATASTROPHIC_LOCAL;
3067 break; 3085 break;
3068 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN: 3086 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN:
3069 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID: 3087 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID:
3088 flush_code = IB_WC_GENERAL_ERR;
3070 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER; 3089 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3071 termhdr->error_code = DDP_UNTAGGED_INV_MSN_RANGE; 3090 termhdr->error_code = DDP_UNTAGGED_INV_MSN_RANGE;
3072 break; 3091 break;
3073 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 3092 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
3093 flush_code = IB_WC_LOC_LEN_ERR;
3074 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER; 3094 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3075 termhdr->error_code = DDP_UNTAGGED_INV_TOO_LONG; 3095 termhdr->error_code = DDP_UNTAGGED_INV_TOO_LONG;
3076 break; 3096 break;
3077 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION: 3097 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION:
3098 flush_code = IB_WC_GENERAL_ERR;
3078 if (is_tagged) { 3099 if (is_tagged) {
3079 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER; 3100 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_TAGGED_BUFFER;
3080 termhdr->error_code = DDP_TAGGED_INV_DDP_VER; 3101 termhdr->error_code = DDP_TAGGED_INV_DDP_VER;
@@ -3084,26 +3105,32 @@ static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 a
3084 } 3105 }
3085 break; 3106 break;
3086 case NES_AEQE_AEID_DDP_UBE_INVALID_MO: 3107 case NES_AEQE_AEID_DDP_UBE_INVALID_MO:
3108 flush_code = IB_WC_GENERAL_ERR;
3087 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER; 3109 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3088 termhdr->error_code = DDP_UNTAGGED_INV_MO; 3110 termhdr->error_code = DDP_UNTAGGED_INV_MO;
3089 break; 3111 break;
3090 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: 3112 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
3113 flush_code = IB_WC_REM_OP_ERR;
3091 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER; 3114 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3092 termhdr->error_code = DDP_UNTAGGED_INV_MSN_NO_BUF; 3115 termhdr->error_code = DDP_UNTAGGED_INV_MSN_NO_BUF;
3093 break; 3116 break;
3094 case NES_AEQE_AEID_DDP_UBE_INVALID_QN: 3117 case NES_AEQE_AEID_DDP_UBE_INVALID_QN:
3118 flush_code = IB_WC_GENERAL_ERR;
3095 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER; 3119 termhdr->layer_etype = (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER;
3096 termhdr->error_code = DDP_UNTAGGED_INV_QN; 3120 termhdr->error_code = DDP_UNTAGGED_INV_QN;
3097 break; 3121 break;
3098 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION: 3122 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION:
3123 flush_code = IB_WC_GENERAL_ERR;
3099 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP; 3124 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3100 termhdr->error_code = RDMAP_INV_RDMAP_VER; 3125 termhdr->error_code = RDMAP_INV_RDMAP_VER;
3101 break; 3126 break;
3102 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE: 3127 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE:
3128 flush_code = IB_WC_LOC_QP_OP_ERR;
3103 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP; 3129 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3104 termhdr->error_code = RDMAP_UNEXPECTED_OP; 3130 termhdr->error_code = RDMAP_UNEXPECTED_OP;
3105 break; 3131 break;
3106 default: 3132 default:
3133 flush_code = IB_WC_FATAL_ERR;
3107 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP; 3134 termhdr->layer_etype = (LAYER_RDMA << 4) | RDMAP_REMOTE_OP;
3108 termhdr->error_code = RDMAP_UNSPECIFIED; 3135 termhdr->error_code = RDMAP_UNSPECIFIED;
3109 break; 3136 break;
@@ -3112,6 +3139,13 @@ static int nes_bld_terminate_hdr(struct nes_qp *nesqp, u16 async_event_id, u32 a
3112 if (copy_len) 3139 if (copy_len)
3113 memcpy(termhdr + 1, pkt, copy_len); 3140 memcpy(termhdr + 1, pkt, copy_len);
3114 3141
3142 if ((flush_code) && ((NES_AEQE_INBOUND_RDMA & aeq_info) == 0)) {
3143 if (aeq_info & NES_AEQE_SQ)
3144 nesqp->term_sq_flush_code = flush_code;
3145 else
3146 nesqp->term_rq_flush_code = flush_code;
3147 }
3148
3115 return sizeof(struct nes_terminate_hdr) + copy_len; 3149 return sizeof(struct nes_terminate_hdr) + copy_len;
3116} 3150}
3117 3151
@@ -3646,6 +3680,8 @@ void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
3646{ 3680{
3647 struct nes_cqp_request *cqp_request; 3681 struct nes_cqp_request *cqp_request;
3648 struct nes_hw_cqp_wqe *cqp_wqe; 3682 struct nes_hw_cqp_wqe *cqp_wqe;
3683 u32 sq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3684 u32 rq_code = (NES_IWARP_CQE_MAJOR_FLUSH << 16) | NES_IWARP_CQE_MINOR_FLUSH;
3649 int ret; 3685 int ret;
3650 3686
3651 cqp_request = nes_get_cqp_request(nesdev); 3687 cqp_request = nes_get_cqp_request(nesdev);
@@ -3662,6 +3698,24 @@ void flush_wqes(struct nes_device *nesdev, struct nes_qp *nesqp,
3662 cqp_wqe = &cqp_request->cqp_wqe; 3698 cqp_wqe = &cqp_request->cqp_wqe;
3663 nes_fill_init_cqp_wqe(cqp_wqe, nesdev); 3699 nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
3664 3700
3701 /* If wqe in error was identified, set code to be put into cqe */
3702 if ((nesqp->term_sq_flush_code) && (which_wq & NES_CQP_FLUSH_SQ)) {
3703 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3704 sq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_sq_flush_code;
3705 nesqp->term_sq_flush_code = 0;
3706 }
3707
3708 if ((nesqp->term_rq_flush_code) && (which_wq & NES_CQP_FLUSH_RQ)) {
3709 which_wq |= NES_CQP_FLUSH_MAJ_MIN;
3710 rq_code = (CQE_MAJOR_DRV << 16) | nesqp->term_rq_flush_code;
3711 nesqp->term_rq_flush_code = 0;
3712 }
3713
3714 if (which_wq & NES_CQP_FLUSH_MAJ_MIN) {
3715 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_SQ_CODE] = cpu_to_le32(sq_code);
3716 cqp_wqe->wqe_words[NES_CQP_QP_WQE_FLUSH_RQ_CODE] = cpu_to_le32(rq_code);
3717 }
3718
3665 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = 3719 cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] =
3666 cpu_to_le32(NES_CQP_FLUSH_WQES | which_wq); 3720 cpu_to_le32(NES_CQP_FLUSH_WQES | which_wq);
3667 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesqp->hwqp.qp_id); 3721 cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(nesqp->hwqp.qp_id);
diff --git a/drivers/infiniband/hw/nes/nes_hw.h b/drivers/infiniband/hw/nes/nes_hw.h
index 4a0bfcd5a628..f28a41ba9fa1 100644
--- a/drivers/infiniband/hw/nes/nes_hw.h
+++ b/drivers/infiniband/hw/nes/nes_hw.h
@@ -274,6 +274,8 @@ enum nes_cqp_qp_bits {
274enum nes_cqp_qp_wqe_word_idx { 274enum nes_cqp_qp_wqe_word_idx {
275 NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6, 275 NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
276 NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7, 276 NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
277 NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
278 NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
277 NES_CQP_QP_WQE_NEW_MSS_IDX = 15, 279 NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
278}; 280};
279 281
@@ -364,6 +366,7 @@ enum nes_cqp_arp_bits {
364enum nes_cqp_flush_bits { 366enum nes_cqp_flush_bits {
365 NES_CQP_FLUSH_SQ = (1<<30), 367 NES_CQP_FLUSH_SQ = (1<<30),
366 NES_CQP_FLUSH_RQ = (1<<31), 368 NES_CQP_FLUSH_RQ = (1<<31),
369 NES_CQP_FLUSH_MAJ_MIN = (1<<28),
367}; 370};
368 371
369enum nes_cqe_opcode_bits { 372enum nes_cqe_opcode_bits {
@@ -757,6 +760,15 @@ enum nes_iwarp_sq_wqe_bits {
757 NES_IWARP_SQ_OP_NOP = 12, 760 NES_IWARP_SQ_OP_NOP = 12,
758}; 761};
759 762
763enum nes_iwarp_cqe_major_code {
764 NES_IWARP_CQE_MAJOR_FLUSH = 1,
765 NES_IWARP_CQE_MAJOR_DRV = 0x8000
766};
767
768enum nes_iwarp_cqe_minor_code {
769 NES_IWARP_CQE_MINOR_FLUSH = 1
770};
771
760#define NES_EEPROM_READ_REQUEST (1<<16) 772#define NES_EEPROM_READ_REQUEST (1<<16)
761#define NES_MAC_ADDR_VALID (1<<20) 773#define NES_MAC_ADDR_VALID (1<<20)
762 774
diff --git a/drivers/infiniband/hw/nes/nes_verbs.h b/drivers/infiniband/hw/nes/nes_verbs.h
index d92b1ef4653b..89822d75f82e 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.h
+++ b/drivers/infiniband/hw/nes/nes_verbs.h
@@ -168,6 +168,8 @@ struct nes_qp {
168 wait_queue_head_t kick_waitq; 168 wait_queue_head_t kick_waitq;
169 u16 in_disconnect; 169 u16 in_disconnect;
170 u16 private_data_len; 170 u16 private_data_len;
171 u16 term_sq_flush_code;
172 u16 term_rq_flush_code;
171 u8 active_conn; 173 u8 active_conn;
172 u8 skip_lsmm; 174 u8 skip_lsmm;
173 u8 user_mode; 175 u8 user_mode;