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authorJes Sorensen <Jes.Sorensen@redhat.com>2014-10-05 10:33:24 -0400
committerRoland Dreier <roland@purestorage.com>2014-10-10 12:43:01 -0400
commitde12348535a93535c408de396d3505541ca5e0d6 (patch)
tree86454b77d19a9bbaef9ce83294bad035972697db /drivers/infiniband
parentbeb9b703811736adfc608034d1f0d5cf0c8a7073 (diff)
RDMA/ocrdma: The kernel has a perfectly good BIT() macro - use it
No need to re-invent the wheel here Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_hw.c4
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_sli.h200
2 files changed, 101 insertions, 103 deletions
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
index 0ac34cb0fcae..638bff1ffc6c 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
@@ -561,8 +561,8 @@ static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
561 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT); 561 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
562 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID; 562 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
563 563
564 cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE); 564 cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
565 cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE); 565 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
566 566
567 cmd->async_cqid_ringsize = cq->id; 567 cmd->async_cqid_ringsize = cq->id;
568 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) << 568 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_sli.h b/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
index 904989ec5eaa..c5212612f37f 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_sli.h
@@ -28,8 +28,6 @@
28#ifndef __OCRDMA_SLI_H__ 28#ifndef __OCRDMA_SLI_H__
29#define __OCRDMA_SLI_H__ 29#define __OCRDMA_SLI_H__
30 30
31#define Bit(_b) (1 << (_b))
32
33enum { 31enum {
34 OCRDMA_ASIC_GEN_SKH_R = 0x04, 32 OCRDMA_ASIC_GEN_SKH_R = 0x04,
35 OCRDMA_ASIC_GEN_LANCER = 0x0B 33 OCRDMA_ASIC_GEN_LANCER = 0x0B
@@ -238,7 +236,7 @@ struct ocrdma_mqe_sge {
238 236
239enum { 237enum {
240 OCRDMA_MQE_HDR_EMB_SHIFT = 0, 238 OCRDMA_MQE_HDR_EMB_SHIFT = 0,
241 OCRDMA_MQE_HDR_EMB_MASK = Bit(0), 239 OCRDMA_MQE_HDR_EMB_MASK = BIT(0),
242 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3, 240 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,
243 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT, 241 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
244 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24, 242 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,
@@ -304,7 +302,7 @@ struct ocrdma_create_eq_req {
304}; 302};
305 303
306enum { 304enum {
307 OCRDMA_CREATE_EQ_VALID = Bit(29), 305 OCRDMA_CREATE_EQ_VALID = BIT(29),
308 OCRDMA_CREATE_EQ_CNT_SHIFT = 26, 306 OCRDMA_CREATE_EQ_CNT_SHIFT = 26,
309 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13, 307 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13,
310}; 308};
@@ -322,13 +320,13 @@ enum {
322 OCRDMA_MCQE_ESTATUS_SHIFT = 16, 320 OCRDMA_MCQE_ESTATUS_SHIFT = 16,
323 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT, 321 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
324 OCRDMA_MCQE_CONS_SHIFT = 27, 322 OCRDMA_MCQE_CONS_SHIFT = 27,
325 OCRDMA_MCQE_CONS_MASK = Bit(27), 323 OCRDMA_MCQE_CONS_MASK = BIT(27),
326 OCRDMA_MCQE_CMPL_SHIFT = 28, 324 OCRDMA_MCQE_CMPL_SHIFT = 28,
327 OCRDMA_MCQE_CMPL_MASK = Bit(28), 325 OCRDMA_MCQE_CMPL_MASK = BIT(28),
328 OCRDMA_MCQE_AE_SHIFT = 30, 326 OCRDMA_MCQE_AE_SHIFT = 30,
329 OCRDMA_MCQE_AE_MASK = Bit(30), 327 OCRDMA_MCQE_AE_MASK = BIT(30),
330 OCRDMA_MCQE_VALID_SHIFT = 31, 328 OCRDMA_MCQE_VALID_SHIFT = 31,
331 OCRDMA_MCQE_VALID_MASK = Bit(31) 329 OCRDMA_MCQE_VALID_MASK = BIT(31)
332}; 330};
333 331
334struct ocrdma_mcqe { 332struct ocrdma_mcqe {
@@ -339,13 +337,13 @@ struct ocrdma_mcqe {
339}; 337};
340 338
341enum { 339enum {
342 OCRDMA_AE_MCQE_QPVALID = Bit(31), 340 OCRDMA_AE_MCQE_QPVALID = BIT(31),
343 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF, 341 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,
344 342
345 OCRDMA_AE_MCQE_CQVALID = Bit(31), 343 OCRDMA_AE_MCQE_CQVALID = BIT(31),
346 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF, 344 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,
347 OCRDMA_AE_MCQE_VALID = Bit(31), 345 OCRDMA_AE_MCQE_VALID = BIT(31),
348 OCRDMA_AE_MCQE_AE = Bit(30), 346 OCRDMA_AE_MCQE_AE = BIT(30),
349 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16, 347 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
350 OCRDMA_AE_MCQE_EVENT_TYPE_MASK = 348 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
351 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT, 349 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
@@ -386,9 +384,9 @@ enum {
386 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF << 384 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF <<
387 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT, 385 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
388 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30, 386 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,
389 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30), 387 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30),
390 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31, 388 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,
391 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31) 389 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31)
392}; 390};
393 391
394struct ocrdma_ae_mpa_mcqe { 392struct ocrdma_ae_mpa_mcqe {
@@ -412,9 +410,9 @@ enum {
412 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF << 410 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF <<
413 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT, 411 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
414 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30, 412 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,
415 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30), 413 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30),
416 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31, 414 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,
417 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31) 415 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31)
418}; 416};
419 417
420struct ocrdma_ae_qp_mcqe { 418struct ocrdma_ae_qp_mcqe {
@@ -449,9 +447,9 @@ enum OCRDMA_ASYNC_EVENT_TYPE {
449/* mailbox command request and responses */ 447/* mailbox command request and responses */
450enum { 448enum {
451 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2, 449 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,
452 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2), 450 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2),
453 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3, 451 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,
454 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3), 452 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3),
455 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8, 453 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,
456 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF << 454 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF <<
457 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT, 455 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
@@ -672,9 +670,9 @@ enum {
672 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF, 670 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,
673 671
674 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12, 672 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,
675 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12), 673 OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12),
676 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14), 674 OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14),
677 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15), 675 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15),
678 676
679 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF, 677 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,
680 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF 678 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF
@@ -687,8 +685,8 @@ enum {
687 OCRDMA_CREATE_CQ_EQID_SHIFT = 22, 685 OCRDMA_CREATE_CQ_EQID_SHIFT = 22,
688 686
689 OCRDMA_CREATE_CQ_CNT_SHIFT = 27, 687 OCRDMA_CREATE_CQ_CNT_SHIFT = 27,
690 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29), 688 OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29),
691 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31), 689 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31),
692 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID | 690 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID |
693 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE | 691 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
694 OCRDMA_CREATE_CQ_FLAGS_NODELAY 692 OCRDMA_CREATE_CQ_FLAGS_NODELAY
@@ -731,8 +729,8 @@ enum {
731 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22, 729 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,
732 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16, 730 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
733 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16, 731 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
734 OCRDMA_CREATE_MQ_VALID = Bit(31), 732 OCRDMA_CREATE_MQ_VALID = BIT(31),
735 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0) 733 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0)
736}; 734};
737 735
738struct ocrdma_create_mq_req { 736struct ocrdma_create_mq_req {
@@ -783,7 +781,7 @@ enum {
783 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16, 781 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
784 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19, 782 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
785 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29, 783 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,
786 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29), 784 OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29),
787 785
788 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0, 786 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,
789 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF, 787 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,
@@ -798,23 +796,23 @@ enum {
798 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT, 796 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
799 797
800 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0, 798 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,
801 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0), 799 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0),
802 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1, 800 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,
803 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1), 801 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1),
804 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2, 802 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,
805 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2), 803 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2),
806 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3, 804 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,
807 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3), 805 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3),
808 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4, 806 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,
809 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4), 807 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4),
810 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5, 808 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,
811 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5), 809 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5),
812 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6, 810 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,
813 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6), 811 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6),
814 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7, 812 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,
815 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7), 813 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7),
816 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8, 814 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,
817 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8), 815 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8),
818 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16, 816 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
819 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF << 817 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF <<
820 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT, 818 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
@@ -927,7 +925,7 @@ enum {
927 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF << 925 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF <<
928 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT, 926 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
929 927
930 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0), 928 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0),
931 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1, 929 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,
932 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF << 930 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF <<
933 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT, 931 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
@@ -964,38 +962,38 @@ enum {
964 OCRDMA_MODIFY_QP_ID_SHIFT = 0, 962 OCRDMA_MODIFY_QP_ID_SHIFT = 0,
965 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF, 963 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,
966 964
967 OCRDMA_QP_PARA_QPS_VALID = Bit(0), 965 OCRDMA_QP_PARA_QPS_VALID = BIT(0),
968 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1), 966 OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1),
969 OCRDMA_QP_PARA_PKEY_VALID = Bit(2), 967 OCRDMA_QP_PARA_PKEY_VALID = BIT(2),
970 OCRDMA_QP_PARA_QKEY_VALID = Bit(3), 968 OCRDMA_QP_PARA_QKEY_VALID = BIT(3),
971 OCRDMA_QP_PARA_PMTU_VALID = Bit(4), 969 OCRDMA_QP_PARA_PMTU_VALID = BIT(4),
972 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5), 970 OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5),
973 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6), 971 OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6),
974 OCRDMA_QP_PARA_RRC_VALID = Bit(7), 972 OCRDMA_QP_PARA_RRC_VALID = BIT(7),
975 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8), 973 OCRDMA_QP_PARA_RQPSN_VALID = BIT(8),
976 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9), 974 OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9),
977 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10), 975 OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10),
978 OCRDMA_QP_PARA_RNT_VALID = Bit(11), 976 OCRDMA_QP_PARA_RNT_VALID = BIT(11),
979 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12), 977 OCRDMA_QP_PARA_SQPSN_VALID = BIT(12),
980 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13), 978 OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13),
981 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14), 979 OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14),
982 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15), 980 OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15),
983 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16), 981 OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16),
984 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17), 982 OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17),
985 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18), 983 OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18),
986 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19), 984 OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19),
987 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20), 985 OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20),
988 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21), 986 OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21),
989 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22), 987 OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22),
990 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23), 988 OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23),
991 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24), 989 OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24),
992 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25), 990 OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25),
993 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26), 991 OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26),
994 992
995 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0), 993 OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0),
996 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1), 994 OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1),
997 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2), 995 OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2),
998 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3) 996 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3)
999}; 997};
1000 998
1001enum { 999enum {
@@ -1014,15 +1012,15 @@ enum {
1014 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF << 1012 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF <<
1015 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT, 1013 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1016 1014
1017 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0), 1015 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0),
1018 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1), 1016 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1),
1019 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2), 1017 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2),
1020 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3), 1018 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3),
1021 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4), 1019 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4),
1022 OCRDMA_QP_PARAMS_STATE_SHIFT = 5, 1020 OCRDMA_QP_PARAMS_STATE_SHIFT = 5,
1023 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7), 1021 OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7),
1024 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8), 1022 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8),
1025 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9), 1023 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9),
1026 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16, 1024 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
1027 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF << 1025 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF <<
1028 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT, 1026 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
@@ -1277,7 +1275,7 @@ struct ocrdma_alloc_pd {
1277}; 1275};
1278 1276
1279enum { 1277enum {
1280 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16), 1278 OCRDMA_ALLOC_PD_RSP_DPP = BIT(16),
1281 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20, 1279 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,
1282 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF, 1280 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF,
1283}; 1281};
@@ -1309,18 +1307,18 @@ enum {
1309 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF, 1307 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,
1310 1308
1311 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0, 1309 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,
1312 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0), 1310 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0),
1313 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1, 1311 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,
1314 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1), 1312 OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1),
1315 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2, 1313 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,
1316 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2), 1314 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2),
1317 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3, 1315 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,
1318 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3), 1316 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3),
1319 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4, 1317 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,
1320 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4), 1318 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4),
1321 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5, 1319 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,
1322 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5), 1320 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5),
1323 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6), 1321 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6),
1324 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6, 1322 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,
1325 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16, 1323 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
1326 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF << 1324 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF <<
@@ -1379,21 +1377,21 @@ enum {
1379 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF << 1377 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF <<
1380 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT, 1378 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1381 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24, 1379 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,
1382 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24), 1380 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24),
1383 OCRDMA_REG_NSMR_ZB_SHIFT = 25, 1381 OCRDMA_REG_NSMR_ZB_SHIFT = 25,
1384 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25), 1382 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25),
1385 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26, 1383 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,
1386 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26), 1384 OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26),
1387 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27, 1385 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,
1388 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27), 1386 OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27),
1389 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28, 1387 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,
1390 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28), 1388 OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28),
1391 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29, 1389 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,
1392 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29), 1390 OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29),
1393 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30, 1391 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,
1394 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30), 1392 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30),
1395 OCRDMA_REG_NSMR_LAST_SHIFT = 31, 1393 OCRDMA_REG_NSMR_LAST_SHIFT = 31,
1396 OCRDMA_REG_NSMR_LAST_MASK = Bit(31) 1394 OCRDMA_REG_NSMR_LAST_MASK = BIT(31)
1397}; 1395};
1398 1396
1399struct ocrdma_reg_nsmr { 1397struct ocrdma_reg_nsmr {
@@ -1420,7 +1418,7 @@ enum {
1420 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT, 1418 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1421 1419
1422 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31, 1420 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,
1423 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31) 1421 OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31)
1424}; 1422};
1425 1423
1426struct ocrdma_reg_nsmr_cont { 1424struct ocrdma_reg_nsmr_cont {
@@ -1566,7 +1564,7 @@ struct ocrdma_delete_ah_tbl_rsp {
1566 1564
1567enum { 1565enum {
1568 OCRDMA_EQE_VALID_SHIFT = 0, 1566 OCRDMA_EQE_VALID_SHIFT = 0,
1569 OCRDMA_EQE_VALID_MASK = Bit(0), 1567 OCRDMA_EQE_VALID_MASK = BIT(0),
1570 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE, 1568 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,
1571 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16, 1569 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
1572 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF << 1570 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF <<
@@ -1624,11 +1622,11 @@ enum {
1624 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT, 1622 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1625 OCRDMA_CQE_STATUS_SHIFT = 16, 1623 OCRDMA_CQE_STATUS_SHIFT = 16,
1626 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT, 1624 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1627 OCRDMA_CQE_VALID = Bit(31), 1625 OCRDMA_CQE_VALID = BIT(31),
1628 OCRDMA_CQE_INVALIDATE = Bit(30), 1626 OCRDMA_CQE_INVALIDATE = BIT(30),
1629 OCRDMA_CQE_QTYPE = Bit(29), 1627 OCRDMA_CQE_QTYPE = BIT(29),
1630 OCRDMA_CQE_IMM = Bit(28), 1628 OCRDMA_CQE_IMM = BIT(28),
1631 OCRDMA_CQE_WRITE_IMM = Bit(27), 1629 OCRDMA_CQE_WRITE_IMM = BIT(27),
1632 OCRDMA_CQE_QTYPE_SQ = 0, 1630 OCRDMA_CQE_QTYPE_SQ = 0,
1633 OCRDMA_CQE_QTYPE_RQ = 1, 1631 OCRDMA_CQE_QTYPE_RQ = 1,
1634 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF 1632 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF
@@ -1772,8 +1770,8 @@ struct ocrdma_grh {
1772 u16 rsvd; 1770 u16 rsvd;
1773} __packed; 1771} __packed;
1774 1772
1775#define OCRDMA_AV_VALID Bit(7) 1773#define OCRDMA_AV_VALID BIT(7)
1776#define OCRDMA_AV_VLAN_VALID Bit(1) 1774#define OCRDMA_AV_VLAN_VALID BIT(1)
1777 1775
1778struct ocrdma_av { 1776struct ocrdma_av {
1779 struct ocrdma_eth_vlan eth_hdr; 1777 struct ocrdma_eth_vlan eth_hdr;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 13:53:52 -0500