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authorMichael S. Tsirkin <mst@mellanox.co.il>2005-04-16 18:26:25 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:26:25 -0400
commit2a4443a699347cb5ac442491421ce7cd7a12e3e2 (patch)
treeef082564fb6a3f9969278f611da96d4713d425bc /drivers/infiniband
parent44ea66879d5638cfed5b5ecf628badfd8ec26f36 (diff)
[PATCH] IB/mthca: fill in opcode field for send completions
Fill in missing fields in send completions. Signed-off-by: Itamar Rabenstein <itamar@mellanox.co.il> Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Signed-off-by: Roland Dreier <roland@topspin.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_cq.c36
-rw-r--r--drivers/infiniband/hw/mthca/mthca_dev.h13
-rw-r--r--drivers/infiniband/hw/mthca/mthca_qp.c13
3 files changed, 48 insertions, 14 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_cq.c b/drivers/infiniband/hw/mthca/mthca_cq.c
index 8b3ffd23e505..0ad954e18bd7 100644
--- a/drivers/infiniband/hw/mthca/mthca_cq.c
+++ b/drivers/infiniband/hw/mthca/mthca_cq.c
@@ -473,7 +473,41 @@ static inline int mthca_poll_one(struct mthca_dev *dev,
473 } 473 }
474 474
475 if (is_send) { 475 if (is_send) {
476 entry->opcode = IB_WC_SEND; /* XXX */ 476 entry->wc_flags = 0;
477 switch (cqe->opcode) {
478 case MTHCA_OPCODE_RDMA_WRITE:
479 entry->opcode = IB_WC_RDMA_WRITE;
480 break;
481 case MTHCA_OPCODE_RDMA_WRITE_IMM:
482 entry->opcode = IB_WC_RDMA_WRITE;
483 entry->wc_flags |= IB_WC_WITH_IMM;
484 break;
485 case MTHCA_OPCODE_SEND:
486 entry->opcode = IB_WC_SEND;
487 break;
488 case MTHCA_OPCODE_SEND_IMM:
489 entry->opcode = IB_WC_SEND;
490 entry->wc_flags |= IB_WC_WITH_IMM;
491 break;
492 case MTHCA_OPCODE_RDMA_READ:
493 entry->opcode = IB_WC_RDMA_READ;
494 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
495 break;
496 case MTHCA_OPCODE_ATOMIC_CS:
497 entry->opcode = IB_WC_COMP_SWAP;
498 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
499 break;
500 case MTHCA_OPCODE_ATOMIC_FA:
501 entry->opcode = IB_WC_FETCH_ADD;
502 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
503 break;
504 case MTHCA_OPCODE_BIND_MW:
505 entry->opcode = IB_WC_BIND_MW;
506 break;
507 default:
508 entry->opcode = MTHCA_OPCODE_INVALID;
509 break;
510 }
477 } else { 511 } else {
478 entry->byte_len = be32_to_cpu(cqe->byte_cnt); 512 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
479 switch (cqe->opcode & 0x1f) { 513 switch (cqe->opcode & 0x1f) {
diff --git a/drivers/infiniband/hw/mthca/mthca_dev.h b/drivers/infiniband/hw/mthca/mthca_dev.h
index f437979e8967..d4bd9aa232b1 100644
--- a/drivers/infiniband/hw/mthca/mthca_dev.h
+++ b/drivers/infiniband/hw/mthca/mthca_dev.h
@@ -88,6 +88,19 @@ enum {
88 MTHCA_NUM_EQ 88 MTHCA_NUM_EQ
89}; 89};
90 90
91enum {
92 MTHCA_OPCODE_NOP = 0x00,
93 MTHCA_OPCODE_RDMA_WRITE = 0x08,
94 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
95 MTHCA_OPCODE_SEND = 0x0a,
96 MTHCA_OPCODE_SEND_IMM = 0x0b,
97 MTHCA_OPCODE_RDMA_READ = 0x10,
98 MTHCA_OPCODE_ATOMIC_CS = 0x11,
99 MTHCA_OPCODE_ATOMIC_FA = 0x12,
100 MTHCA_OPCODE_BIND_MW = 0x18,
101 MTHCA_OPCODE_INVALID = 0xff
102};
103
91struct mthca_cmd { 104struct mthca_cmd {
92 int use_events; 105 int use_events;
93 struct semaphore hcr_sem; 106 struct semaphore hcr_sem;
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c
index 2d3b1815c04e..997a34a2b2be 100644
--- a/drivers/infiniband/hw/mthca/mthca_qp.c
+++ b/drivers/infiniband/hw/mthca/mthca_qp.c
@@ -171,19 +171,6 @@ enum {
171}; 171};
172 172
173enum { 173enum {
174 MTHCA_OPCODE_NOP = 0x00,
175 MTHCA_OPCODE_RDMA_WRITE = 0x08,
176 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
177 MTHCA_OPCODE_SEND = 0x0a,
178 MTHCA_OPCODE_SEND_IMM = 0x0b,
179 MTHCA_OPCODE_RDMA_READ = 0x10,
180 MTHCA_OPCODE_ATOMIC_CS = 0x11,
181 MTHCA_OPCODE_ATOMIC_FA = 0x12,
182 MTHCA_OPCODE_BIND_MW = 0x18,
183 MTHCA_OPCODE_INVALID = 0xff
184};
185
186enum {
187 MTHCA_NEXT_DBD = 1 << 7, 174 MTHCA_NEXT_DBD = 1 << 7,
188 MTHCA_NEXT_FENCE = 1 << 6, 175 MTHCA_NEXT_FENCE = 1 << 6,
189 MTHCA_NEXT_CQ_UPDATE = 1 << 3, 176 MTHCA_NEXT_CQ_UPDATE = 1 << 3,