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authorRalph Campbell <ralph.campbell@qlogic.com>2008-04-17 00:09:30 -0400
committerRoland Dreier <rolandd@cisco.com>2008-04-17 00:09:30 -0400
commit843e6ab489cb5a2fd5df45bed1254812bc8ed8fa (patch)
treec7d1ab98ee0039ae2aa097874958a806c1352b25 /drivers/infiniband/hw
parentdd042d59c18b2f26375494af7f5b6d1499acd2bb (diff)
IB/ipath: HCA-specific code to support IBA7220
This patch adds the HCA-specific code for the IBA7220 HCA. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw')
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba7220.c2571
1 files changed, 2571 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_iba7220.c b/drivers/infiniband/hw/ipath/ipath_iba7220.c
new file mode 100644
index 000000000000..1b2de2cfb69b
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ipath_iba7220.c
@@ -0,0 +1,2571 @@
1/*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7220 chip (except that specific to the SerDes)
36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/io.h>
42#include <rdma/ib_verbs.h>
43
44#include "ipath_kernel.h"
45#include "ipath_registers.h"
46#include "ipath_7220.h"
47
48static void ipath_setup_7220_setextled(struct ipath_devdata *, u64, u64);
49
50static unsigned ipath_compat_ddr_negotiate = 1;
51
52module_param_named(compat_ddr_negotiate, ipath_compat_ddr_negotiate, uint,
53 S_IWUSR | S_IRUGO);
54MODULE_PARM_DESC(compat_ddr_negotiate,
55 "Attempt pre-IBTA 1.2 DDR speed negotiation");
56
57static unsigned ipath_sdma_fetch_arb = 1;
58module_param_named(fetch_arb, ipath_sdma_fetch_arb, uint, S_IRUGO);
59MODULE_PARM_DESC(fetch_arb, "IBA7220: change SDMA descriptor arbitration");
60
61/*
62 * This file contains almost all the chip-specific register information and
63 * access functions for the QLogic InfiniPath 7220 PCI-Express chip, with the
64 * exception of SerDes support, which in in ipath_sd7220.c.
65 *
66 * This lists the InfiniPath registers, in the actual chip layout.
67 * This structure should never be directly accessed.
68 */
69struct _infinipath_do_not_use_kernel_regs {
70 unsigned long long Revision;
71 unsigned long long Control;
72 unsigned long long PageAlign;
73 unsigned long long PortCnt;
74 unsigned long long DebugPortSelect;
75 unsigned long long DebugSigsIntSel; /* was Reserved0;*/
76 unsigned long long SendRegBase;
77 unsigned long long UserRegBase;
78 unsigned long long CounterRegBase;
79 unsigned long long Scratch;
80 unsigned long long EEPROMAddrCmd; /* was Reserved1; */
81 unsigned long long EEPROMData; /* was Reserved2; */
82 unsigned long long IntBlocked;
83 unsigned long long IntMask;
84 unsigned long long IntStatus;
85 unsigned long long IntClear;
86 unsigned long long ErrorMask;
87 unsigned long long ErrorStatus;
88 unsigned long long ErrorClear;
89 unsigned long long HwErrMask;
90 unsigned long long HwErrStatus;
91 unsigned long long HwErrClear;
92 unsigned long long HwDiagCtrl;
93 unsigned long long MDIO;
94 unsigned long long IBCStatus;
95 unsigned long long IBCCtrl;
96 unsigned long long ExtStatus;
97 unsigned long long ExtCtrl;
98 unsigned long long GPIOOut;
99 unsigned long long GPIOMask;
100 unsigned long long GPIOStatus;
101 unsigned long long GPIOClear;
102 unsigned long long RcvCtrl;
103 unsigned long long RcvBTHQP;
104 unsigned long long RcvHdrSize;
105 unsigned long long RcvHdrCnt;
106 unsigned long long RcvHdrEntSize;
107 unsigned long long RcvTIDBase;
108 unsigned long long RcvTIDCnt;
109 unsigned long long RcvEgrBase;
110 unsigned long long RcvEgrCnt;
111 unsigned long long RcvBufBase;
112 unsigned long long RcvBufSize;
113 unsigned long long RxIntMemBase;
114 unsigned long long RxIntMemSize;
115 unsigned long long RcvPartitionKey;
116 unsigned long long RcvQPMulticastPort;
117 unsigned long long RcvPktLEDCnt;
118 unsigned long long IBCDDRCtrl;
119 unsigned long long HRTBT_GUID;
120 unsigned long long IB_SDTEST_IF_TX;
121 unsigned long long IB_SDTEST_IF_RX;
122 unsigned long long IBCDDRCtrl2;
123 unsigned long long IBCDDRStatus;
124 unsigned long long JIntReload;
125 unsigned long long IBNCModeCtrl;
126 unsigned long long SendCtrl;
127 unsigned long long SendBufBase;
128 unsigned long long SendBufSize;
129 unsigned long long SendBufCnt;
130 unsigned long long SendAvailAddr;
131 unsigned long long TxIntMemBase;
132 unsigned long long TxIntMemSize;
133 unsigned long long SendDmaBase;
134 unsigned long long SendDmaLenGen;
135 unsigned long long SendDmaTail;
136 unsigned long long SendDmaHead;
137 unsigned long long SendDmaHeadAddr;
138 unsigned long long SendDmaBufMask0;
139 unsigned long long SendDmaBufMask1;
140 unsigned long long SendDmaBufMask2;
141 unsigned long long SendDmaStatus;
142 unsigned long long SendBufferError;
143 unsigned long long SendBufferErrorCONT1;
144 unsigned long long SendBufErr2; /* was Reserved6SBE[0/6] */
145 unsigned long long Reserved6L[2];
146 unsigned long long AvailUpdCount;
147 unsigned long long RcvHdrAddr0;
148 unsigned long long RcvHdrAddrs[16]; /* Why enumerate? */
149 unsigned long long Reserved7hdtl; /* Align next to 300 */
150 unsigned long long RcvHdrTailAddr0; /* 300, like others */
151 unsigned long long RcvHdrTailAddrs[16];
152 unsigned long long Reserved9SW[7]; /* was [8]; we have 17 ports */
153 unsigned long long IbsdEpbAccCtl; /* IB Serdes EPB access control */
154 unsigned long long IbsdEpbTransReg; /* IB Serdes EPB Transaction */
155 unsigned long long Reserved10sds; /* was SerdesStatus on */
156 unsigned long long XGXSConfig;
157 unsigned long long IBSerDesCtrl; /* Was IBPLLCfg on Monty */
158 unsigned long long EEPCtlStat; /* for "boot" EEPROM/FLASH */
159 unsigned long long EEPAddrCmd;
160 unsigned long long EEPData;
161 unsigned long long PcieEpbAccCtl;
162 unsigned long long PcieEpbTransCtl;
163 unsigned long long EfuseCtl; /* E-Fuse control */
164 unsigned long long EfuseData[4];
165 unsigned long long ProcMon;
166 /* this chip moves following two from previous 200, 208 */
167 unsigned long long PCIeRBufTestReg0;
168 unsigned long long PCIeRBufTestReg1;
169 /* added for this chip */
170 unsigned long long PCIeRBufTestReg2;
171 unsigned long long PCIeRBufTestReg3;
172 /* added for this chip, debug only */
173 unsigned long long SPC_JTAG_ACCESS_REG;
174 unsigned long long LAControlReg;
175 unsigned long long GPIODebugSelReg;
176 unsigned long long DebugPortValueReg;
177 /* added for this chip, DMA */
178 unsigned long long SendDmaBufUsed[3];
179 unsigned long long SendDmaReqTagUsed;
180 /*
181 * added for this chip, EFUSE: note that these program 64-bit
182 * words 2 and 3 */
183 unsigned long long efuse_pgm_data[2];
184 unsigned long long Reserved11LAalign[10]; /* Skip 4B0..4F8 */
185 /* we have 30 regs for DDS and RXEQ in IB SERDES */
186 unsigned long long SerDesDDSRXEQ[30];
187 unsigned long long Reserved12LAalign[2]; /* Skip 5F0, 5F8 */
188 /* added for LA debug support */
189 unsigned long long LAMemory[32];
190};
191
192struct _infinipath_do_not_use_counters {
193 __u64 LBIntCnt;
194 __u64 LBFlowStallCnt;
195 __u64 TxSDmaDescCnt; /* was Reserved1 */
196 __u64 TxUnsupVLErrCnt;
197 __u64 TxDataPktCnt;
198 __u64 TxFlowPktCnt;
199 __u64 TxDwordCnt;
200 __u64 TxLenErrCnt;
201 __u64 TxMaxMinLenErrCnt;
202 __u64 TxUnderrunCnt;
203 __u64 TxFlowStallCnt;
204 __u64 TxDroppedPktCnt;
205 __u64 RxDroppedPktCnt;
206 __u64 RxDataPktCnt;
207 __u64 RxFlowPktCnt;
208 __u64 RxDwordCnt;
209 __u64 RxLenErrCnt;
210 __u64 RxMaxMinLenErrCnt;
211 __u64 RxICRCErrCnt;
212 __u64 RxVCRCErrCnt;
213 __u64 RxFlowCtrlErrCnt;
214 __u64 RxBadFormatCnt;
215 __u64 RxLinkProblemCnt;
216 __u64 RxEBPCnt;
217 __u64 RxLPCRCErrCnt;
218 __u64 RxBufOvflCnt;
219 __u64 RxTIDFullErrCnt;
220 __u64 RxTIDValidErrCnt;
221 __u64 RxPKeyMismatchCnt;
222 __u64 RxP0HdrEgrOvflCnt;
223 __u64 RxP1HdrEgrOvflCnt;
224 __u64 RxP2HdrEgrOvflCnt;
225 __u64 RxP3HdrEgrOvflCnt;
226 __u64 RxP4HdrEgrOvflCnt;
227 __u64 RxP5HdrEgrOvflCnt;
228 __u64 RxP6HdrEgrOvflCnt;
229 __u64 RxP7HdrEgrOvflCnt;
230 __u64 RxP8HdrEgrOvflCnt;
231 __u64 RxP9HdrEgrOvflCnt; /* was Reserved6 */
232 __u64 RxP10HdrEgrOvflCnt; /* was Reserved7 */
233 __u64 RxP11HdrEgrOvflCnt; /* new for IBA7220 */
234 __u64 RxP12HdrEgrOvflCnt; /* new for IBA7220 */
235 __u64 RxP13HdrEgrOvflCnt; /* new for IBA7220 */
236 __u64 RxP14HdrEgrOvflCnt; /* new for IBA7220 */
237 __u64 RxP15HdrEgrOvflCnt; /* new for IBA7220 */
238 __u64 RxP16HdrEgrOvflCnt; /* new for IBA7220 */
239 __u64 IBStatusChangeCnt;
240 __u64 IBLinkErrRecoveryCnt;
241 __u64 IBLinkDownedCnt;
242 __u64 IBSymbolErrCnt;
243 /* The following are new for IBA7220 */
244 __u64 RxVL15DroppedPktCnt;
245 __u64 RxOtherLocalPhyErrCnt;
246 __u64 PcieRetryBufDiagQwordCnt;
247 __u64 ExcessBufferOvflCnt;
248 __u64 LocalLinkIntegrityErrCnt;
249 __u64 RxVlErrCnt;
250 __u64 RxDlidFltrCnt;
251 __u64 Reserved8[7];
252 __u64 PSStat;
253 __u64 PSStart;
254 __u64 PSInterval;
255 __u64 PSRcvDataCount;
256 __u64 PSRcvPktsCount;
257 __u64 PSXmitDataCount;
258 __u64 PSXmitPktsCount;
259 __u64 PSXmitWaitCount;
260};
261
262#define IPATH_KREG_OFFSET(field) (offsetof( \
263 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
264#define IPATH_CREG_OFFSET(field) (offsetof( \
265 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
266
267static const struct ipath_kregs ipath_7220_kregs = {
268 .kr_control = IPATH_KREG_OFFSET(Control),
269 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
270 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
271 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
272 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
273 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
274 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
275 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
276 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
277 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
278 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
279 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
280 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
281 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
282 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
283 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
284 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
285 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
286 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
287 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
288 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
289 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
290 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
291 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
292 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
293 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
294 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
295 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
296 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
297 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
298 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
299 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
300 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
301 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
302 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
303 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
304 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
305 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
306 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
307 .kr_revision = IPATH_KREG_OFFSET(Revision),
308 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
309 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
310 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
311 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendAvailAddr),
312 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendBufBase),
313 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendBufCnt),
314 .kr_sendpiosize = IPATH_KREG_OFFSET(SendBufSize),
315 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
316 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
317 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
318 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
319
320 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
321
322 /* send dma related regs */
323 .kr_senddmabase = IPATH_KREG_OFFSET(SendDmaBase),
324 .kr_senddmalengen = IPATH_KREG_OFFSET(SendDmaLenGen),
325 .kr_senddmatail = IPATH_KREG_OFFSET(SendDmaTail),
326 .kr_senddmahead = IPATH_KREG_OFFSET(SendDmaHead),
327 .kr_senddmaheadaddr = IPATH_KREG_OFFSET(SendDmaHeadAddr),
328 .kr_senddmabufmask0 = IPATH_KREG_OFFSET(SendDmaBufMask0),
329 .kr_senddmabufmask1 = IPATH_KREG_OFFSET(SendDmaBufMask1),
330 .kr_senddmabufmask2 = IPATH_KREG_OFFSET(SendDmaBufMask2),
331 .kr_senddmastatus = IPATH_KREG_OFFSET(SendDmaStatus),
332
333 /* SerDes related regs */
334 .kr_ibserdesctrl = IPATH_KREG_OFFSET(IBSerDesCtrl),
335 .kr_ib_epbacc = IPATH_KREG_OFFSET(IbsdEpbAccCtl),
336 .kr_ib_epbtrans = IPATH_KREG_OFFSET(IbsdEpbTransReg),
337 .kr_pcie_epbacc = IPATH_KREG_OFFSET(PcieEpbAccCtl),
338 .kr_pcie_epbtrans = IPATH_KREG_OFFSET(PcieEpbTransCtl),
339 .kr_ib_ddsrxeq = IPATH_KREG_OFFSET(SerDesDDSRXEQ),
340
341 /*
342 * These should not be used directly via ipath_read_kreg64(),
343 * use them with ipath_read_kreg64_port()
344 */
345 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
346 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
347
348 /*
349 * The rcvpktled register controls one of the debug port signals, so
350 * a packet activity LED can be connected to it.
351 */
352 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
353 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
354 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
355
356 .kr_hrtbt_guid = IPATH_KREG_OFFSET(HRTBT_GUID),
357 .kr_ibcddrctrl = IPATH_KREG_OFFSET(IBCDDRCtrl),
358 .kr_ibcddrstatus = IPATH_KREG_OFFSET(IBCDDRStatus),
359 .kr_jintreload = IPATH_KREG_OFFSET(JIntReload)
360};
361
362static const struct ipath_cregs ipath_7220_cregs = {
363 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
364 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
365 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
366 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
367 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
368 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
369 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
370 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
371 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
372 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
373 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
374 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
375 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
376 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
377 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
378 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
379 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
380 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
381 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
382 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
383 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
384 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
385 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
386 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
387 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
388 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
389 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
390 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
391 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
392 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
393 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
394 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
395 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt),
396 .cr_vl15droppedpktcnt = IPATH_CREG_OFFSET(RxVL15DroppedPktCnt),
397 .cr_rxotherlocalphyerrcnt =
398 IPATH_CREG_OFFSET(RxOtherLocalPhyErrCnt),
399 .cr_excessbufferovflcnt = IPATH_CREG_OFFSET(ExcessBufferOvflCnt),
400 .cr_locallinkintegrityerrcnt =
401 IPATH_CREG_OFFSET(LocalLinkIntegrityErrCnt),
402 .cr_rxvlerrcnt = IPATH_CREG_OFFSET(RxVlErrCnt),
403 .cr_rxdlidfltrcnt = IPATH_CREG_OFFSET(RxDlidFltrCnt),
404 .cr_psstat = IPATH_CREG_OFFSET(PSStat),
405 .cr_psstart = IPATH_CREG_OFFSET(PSStart),
406 .cr_psinterval = IPATH_CREG_OFFSET(PSInterval),
407 .cr_psrcvdatacount = IPATH_CREG_OFFSET(PSRcvDataCount),
408 .cr_psrcvpktscount = IPATH_CREG_OFFSET(PSRcvPktsCount),
409 .cr_psxmitdatacount = IPATH_CREG_OFFSET(PSXmitDataCount),
410 .cr_psxmitpktscount = IPATH_CREG_OFFSET(PSXmitPktsCount),
411 .cr_psxmitwaitcount = IPATH_CREG_OFFSET(PSXmitWaitCount),
412};
413
414/* kr_control bits */
415#define INFINIPATH_C_RESET (1U<<7)
416
417/* kr_intstatus, kr_intclear, kr_intmask bits */
418#define INFINIPATH_I_RCVURG_MASK ((1ULL<<17)-1)
419#define INFINIPATH_I_RCVURG_SHIFT 32
420#define INFINIPATH_I_RCVAVAIL_MASK ((1ULL<<17)-1)
421#define INFINIPATH_I_RCVAVAIL_SHIFT 0
422#define INFINIPATH_I_SERDESTRIMDONE (1ULL<<27)
423
424/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
425#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x00000000000000ffULL
426#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
427#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
428#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
429#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
430#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
431#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
432#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
433#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
434#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
435#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
436#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
437/* specific to this chip */
438#define INFINIPATH_HWE_PCIECPLDATAQUEUEERR 0x0000000000000040ULL
439#define INFINIPATH_HWE_PCIECPLHDRQUEUEERR 0x0000000000000080ULL
440#define INFINIPATH_HWE_SDMAMEMREADERR 0x0000000010000000ULL
441#define INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED 0x2000000000000000ULL
442#define INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT 0x0100000000000000ULL
443#define INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT 0x0200000000000000ULL
444#define INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT 0x0400000000000000ULL
445#define INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT 0x0800000000000000ULL
446#define INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR 0x0000008000000000ULL
447#define INFINIPATH_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
448#define INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
449#define INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
450
451#define IBA7220_IBCS_LINKTRAININGSTATE_MASK 0x1F
452#define IBA7220_IBCS_LINKSTATE_SHIFT 5
453#define IBA7220_IBCS_LINKSPEED_SHIFT 8
454#define IBA7220_IBCS_LINKWIDTH_SHIFT 9
455
456#define IBA7220_IBCC_LINKINITCMD_MASK 0x7ULL
457#define IBA7220_IBCC_LINKCMD_SHIFT 19
458#define IBA7220_IBCC_MAXPKTLEN_SHIFT 21
459
460/* kr_ibcddrctrl bits */
461#define IBA7220_IBC_DLIDLMC_MASK 0xFFFFFFFFUL
462#define IBA7220_IBC_DLIDLMC_SHIFT 32
463#define IBA7220_IBC_HRTBT_MASK 3
464#define IBA7220_IBC_HRTBT_SHIFT 16
465#define IBA7220_IBC_HRTBT_ENB 0x10000UL
466#define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
467#define IBA7220_IBC_LREV_MASK 1
468#define IBA7220_IBC_LREV_SHIFT 8
469#define IBA7220_IBC_RXPOL_MASK 1
470#define IBA7220_IBC_RXPOL_SHIFT 7
471#define IBA7220_IBC_WIDTH_SHIFT 5
472#define IBA7220_IBC_WIDTH_MASK 0x3
473#define IBA7220_IBC_WIDTH_1X_ONLY (0<<IBA7220_IBC_WIDTH_SHIFT)
474#define IBA7220_IBC_WIDTH_4X_ONLY (1<<IBA7220_IBC_WIDTH_SHIFT)
475#define IBA7220_IBC_WIDTH_AUTONEG (2<<IBA7220_IBC_WIDTH_SHIFT)
476#define IBA7220_IBC_SPEED_AUTONEG (1<<1)
477#define IBA7220_IBC_SPEED_SDR (1<<2)
478#define IBA7220_IBC_SPEED_DDR (1<<3)
479#define IBA7220_IBC_SPEED_AUTONEG_MASK (0x7<<1)
480#define IBA7220_IBC_IBTA_1_2_MASK (1)
481
482/* kr_ibcddrstatus */
483/* link latency shift is 0, don't bother defining */
484#define IBA7220_DDRSTAT_LINKLAT_MASK 0x3ffffff
485
486/* kr_extstatus bits */
487#define INFINIPATH_EXTS_FREQSEL 0x2
488#define INFINIPATH_EXTS_SERDESSEL 0x4
489#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
490#define INFINIPATH_EXTS_MEMBIST_DISABLED 0x0000000000008000
491
492/* kr_xgxsconfig bits */
493#define INFINIPATH_XGXS_RESET 0x5ULL
494#define INFINIPATH_XGXS_FC_SAFE (1ULL<<63)
495
496/* kr_rcvpktledcnt */
497#define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
498#define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
499
500#define _IPATH_GPIO_SDA_NUM 1
501#define _IPATH_GPIO_SCL_NUM 0
502
503#define IPATH_GPIO_SDA (1ULL << \
504 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
505#define IPATH_GPIO_SCL (1ULL << \
506 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
507
508#define IBA7220_R_INTRAVAIL_SHIFT 17
509#define IBA7220_R_TAILUPD_SHIFT 35
510#define IBA7220_R_PORTCFG_SHIFT 36
511
512#define INFINIPATH_JINT_PACKETSHIFT 16
513#define INFINIPATH_JINT_DEFAULT_IDLE_TICKS 0
514#define INFINIPATH_JINT_DEFAULT_MAX_PACKETS 0
515
516#define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
517
518/*
519 * the size bits give us 2^N, in KB units. 0 marks as invalid,
520 * and 7 is reserved. We currently use only 2KB and 4KB
521 */
522#define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
523#define IBA7220_TID_SZ_2K (1UL<<IBA7220_TID_SZ_SHIFT) /* 2KB */
524#define IBA7220_TID_SZ_4K (2UL<<IBA7220_TID_SZ_SHIFT) /* 4KB */
525#define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
526
527#define IPATH_AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
528
529static char int_type[16] = "auto";
530module_param_string(interrupt_type, int_type, sizeof(int_type), 0444);
531MODULE_PARM_DESC(int_type, " interrupt_type=auto|force_msi|force_intx\n");
532
533/* packet rate matching delay; chip has support */
534static u8 rate_to_delay[2][2] = {
535 /* 1x, 4x */
536 { 8, 2 }, /* SDR */
537 { 4, 1 } /* DDR */
538};
539
540/* 7220 specific hardware errors... */
541static const struct ipath_hwerror_msgs ipath_7220_hwerror_msgs[] = {
542 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
543 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
544 /*
545 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
546 * parity or memory parity error failures, because most likely we
547 * won't be able to talk to the core of the chip. Nonetheless, we
548 * might see them, if they are in parts of the PCIe core that aren't
549 * essential.
550 */
551 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
552 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
553 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
554 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
555 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
556 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
557 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
558 INFINIPATH_HWE_MSG(PCIECPLDATAQUEUEERR, "PCIe cpl header queue"),
559 INFINIPATH_HWE_MSG(PCIECPLHDRQUEUEERR, "PCIe cpl data queue"),
560 INFINIPATH_HWE_MSG(SDMAMEMREADERR, "Send DMA memory read"),
561 INFINIPATH_HWE_MSG(CLK_UC_PLLNOTLOCKED, "uC PLL clock not locked"),
562 INFINIPATH_HWE_MSG(PCIESERDESQ0PCLKNOTDETECT,
563 "PCIe serdes Q0 no clock"),
564 INFINIPATH_HWE_MSG(PCIESERDESQ1PCLKNOTDETECT,
565 "PCIe serdes Q1 no clock"),
566 INFINIPATH_HWE_MSG(PCIESERDESQ2PCLKNOTDETECT,
567 "PCIe serdes Q2 no clock"),
568 INFINIPATH_HWE_MSG(PCIESERDESQ3PCLKNOTDETECT,
569 "PCIe serdes Q3 no clock"),
570 INFINIPATH_HWE_MSG(DDSRXEQMEMORYPARITYERR,
571 "DDS RXEQ memory parity"),
572 INFINIPATH_HWE_MSG(IB_UC_MEMORYPARITYERR, "IB uC memory parity"),
573 INFINIPATH_HWE_MSG(PCIE_UC_OCT0MEMORYPARITYERR,
574 "PCIe uC oct0 memory parity"),
575 INFINIPATH_HWE_MSG(PCIE_UC_OCT1MEMORYPARITYERR,
576 "PCIe uC oct1 memory parity"),
577};
578
579static void autoneg_work(struct work_struct *);
580
581/*
582 * the offset is different for different configured port numbers, since
583 * port0 is fixed in size, but others can vary. Make it a function to
584 * make the issue more obvious.
585*/
586static inline u32 port_egrtid_idx(struct ipath_devdata *dd, unsigned port)
587{
588 return port ? dd->ipath_p0_rcvegrcnt +
589 (port-1) * dd->ipath_rcvegrcnt : 0;
590}
591
592static void ipath_7220_txe_recover(struct ipath_devdata *dd)
593{
594 ++ipath_stats.sps_txeparity;
595
596 dev_info(&dd->pcidev->dev,
597 "Recovering from TXE PIO parity error\n");
598 ipath_disarm_senderrbufs(dd, 1);
599}
600
601
602/**
603 * ipath_7220_handle_hwerrors - display hardware errors.
604 * @dd: the infinipath device
605 * @msg: the output buffer
606 * @msgl: the size of the output buffer
607 *
608 * Use same msg buffer as regular errors to avoid excessive stack
609 * use. Most hardware errors are catastrophic, but for right now,
610 * we'll print them and continue. We reuse the same message buffer as
611 * ipath_handle_errors() to avoid excessive stack usage.
612 */
613static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
614 size_t msgl)
615{
616 ipath_err_t hwerrs;
617 u32 bits, ctrl;
618 int isfatal = 0;
619 char bitsmsg[64];
620 int log_idx;
621
622 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
623 if (!hwerrs) {
624 /*
625 * better than printing cofusing messages
626 * This seems to be related to clearing the crc error, or
627 * the pll error during init.
628 */
629 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
630 goto bail;
631 } else if (hwerrs == ~0ULL) {
632 ipath_dev_err(dd, "Read of hardware error status failed "
633 "(all bits set); ignoring\n");
634 goto bail;
635 }
636 ipath_stats.sps_hwerrs++;
637
638 /*
639 * Always clear the error status register, except MEMBISTFAIL,
640 * regardless of whether we continue or stop using the chip.
641 * We want that set so we know it failed, even across driver reload.
642 * We'll still ignore it in the hwerrmask. We do this partly for
643 * diagnostics, but also for support.
644 */
645 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
646 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
647
648 hwerrs &= dd->ipath_hwerrmask;
649
650 /* We log some errors to EEPROM, check if we have any of those. */
651 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
652 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
653 ipath_inc_eeprom_err(dd, log_idx, 1);
654 /*
655 * Make sure we get this much out, unless told to be quiet,
656 * or it's occurred within the last 5 seconds.
657 */
658 if ((hwerrs & ~(dd->ipath_lasthwerror |
659 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
660 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
661 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
662 (ipath_debug & __IPATH_VERBDBG))
663 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
664 "(cleared)\n", (unsigned long long) hwerrs);
665 dd->ipath_lasthwerror |= hwerrs;
666
667 if (hwerrs & ~dd->ipath_hwe_bitsextant)
668 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
669 "%llx set\n", (unsigned long long)
670 (hwerrs & ~dd->ipath_hwe_bitsextant));
671
672 if (hwerrs & INFINIPATH_HWE_IB_UC_MEMORYPARITYERR)
673 ipath_sd7220_clr_ibpar(dd);
674
675 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
676 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
677 /*
678 * Parity errors in send memory are recoverable,
679 * just cancel the send (if indicated in * sendbuffererror),
680 * count the occurrence, unfreeze (if no other handled
681 * hardware error bits are set), and continue.
682 */
683 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
684 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
685 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
686 ipath_7220_txe_recover(dd);
687 hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
688 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
689 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
690 if (!hwerrs) {
691 /* else leave in freeze mode */
692 ipath_write_kreg(dd,
693 dd->ipath_kregs->kr_control,
694 dd->ipath_control);
695 goto bail;
696 }
697 }
698 if (hwerrs) {
699 /*
700 * If any set that we aren't ignoring only make the
701 * complaint once, in case it's stuck or recurring,
702 * and we get here multiple times
703 * Force link down, so switch knows, and
704 * LEDs are turned off.
705 */
706 if (dd->ipath_flags & IPATH_INITTED) {
707 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
708 ipath_setup_7220_setextled(dd,
709 INFINIPATH_IBCS_L_STATE_DOWN,
710 INFINIPATH_IBCS_LT_STATE_DISABLED);
711 ipath_dev_err(dd, "Fatal Hardware Error "
712 "(freeze mode), no longer"
713 " usable, SN %.16s\n",
714 dd->ipath_serial);
715 isfatal = 1;
716 }
717 /*
718 * Mark as having had an error for driver, and also
719 * for /sys and status word mapped to user programs.
720 * This marks unit as not usable, until reset.
721 */
722 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
723 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
724 dd->ipath_flags &= ~IPATH_INITTED;
725 } else {
726 ipath_dbg("Clearing freezemode on ignored hardware "
727 "error\n");
728 ipath_clear_freeze(dd);
729 }
730 }
731
732 *msg = '\0';
733
734 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
735 strlcat(msg, "[Memory BIST test failed, "
736 "InfiniPath hardware unusable]", msgl);
737 /* ignore from now on, so disable until driver reloaded */
738 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
739 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
740 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
741 dd->ipath_hwerrmask);
742 }
743
744 ipath_format_hwerrors(hwerrs,
745 ipath_7220_hwerror_msgs,
746 ARRAY_SIZE(ipath_7220_hwerror_msgs),
747 msg, msgl);
748
749 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
750 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
751 bits = (u32) ((hwerrs >>
752 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
753 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
754 snprintf(bitsmsg, sizeof bitsmsg,
755 "[PCIe Mem Parity Errs %x] ", bits);
756 strlcat(msg, bitsmsg, msgl);
757 }
758
759#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
760 INFINIPATH_HWE_COREPLL_RFSLIP)
761
762 if (hwerrs & _IPATH_PLL_FAIL) {
763 snprintf(bitsmsg, sizeof bitsmsg,
764 "[PLL failed (%llx), InfiniPath hardware unusable]",
765 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
766 strlcat(msg, bitsmsg, msgl);
767 /* ignore from now on, so disable until driver reloaded */
768 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
769 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
770 dd->ipath_hwerrmask);
771 }
772
773 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
774 /*
775 * If it occurs, it is left masked since the eternal
776 * interface is unused.
777 */
778 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
779 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
780 dd->ipath_hwerrmask);
781 }
782
783 ipath_dev_err(dd, "%s hardware error\n", msg);
784 /*
785 * For /sys status file. if no trailing } is copied, we'll
786 * know it was truncated.
787 */
788 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
789 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
790 "{%s}", msg);
791bail:;
792}
793
794/**
795 * ipath_7220_boardname - fill in the board name
796 * @dd: the infinipath device
797 * @name: the output buffer
798 * @namelen: the size of the output buffer
799 *
800 * info is based on the board revision register
801 */
802static int ipath_7220_boardname(struct ipath_devdata *dd, char *name,
803 size_t namelen)
804{
805 char *n = NULL;
806 u8 boardrev = dd->ipath_boardrev;
807 int ret;
808
809 if (boardrev == 15) {
810 /*
811 * Emulator sometimes comes up all-ones, rather than zero.
812 */
813 boardrev = 0;
814 dd->ipath_boardrev = boardrev;
815 }
816 switch (boardrev) {
817 case 0:
818 n = "InfiniPath_7220_Emulation";
819 break;
820 case 1:
821 n = "InfiniPath_QLE7240";
822 break;
823 case 2:
824 n = "InfiniPath_QLE7280";
825 break;
826 case 3:
827 n = "InfiniPath_QLE7242";
828 break;
829 case 4:
830 n = "InfiniPath_QEM7240";
831 break;
832 case 5:
833 n = "InfiniPath_QMI7240";
834 break;
835 case 6:
836 n = "InfiniPath_QMI7264";
837 break;
838 case 7:
839 n = "InfiniPath_QMH7240";
840 break;
841 case 8:
842 n = "InfiniPath_QME7240";
843 break;
844 case 9:
845 n = "InfiniPath_QLE7250";
846 break;
847 case 10:
848 n = "InfiniPath_QLE7290";
849 break;
850 case 11:
851 n = "InfiniPath_QEM7250";
852 break;
853 case 12:
854 n = "InfiniPath_QLE-Bringup";
855 break;
856 default:
857 ipath_dev_err(dd,
858 "Don't yet know about board with ID %u\n",
859 boardrev);
860 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
861 boardrev);
862 break;
863 }
864 if (n)
865 snprintf(name, namelen, "%s", n);
866
867 if (dd->ipath_majrev != 5 || !dd->ipath_minrev ||
868 dd->ipath_minrev > 2) {
869 ipath_dev_err(dd, "Unsupported InfiniPath hardware "
870 "revision %u.%u!\n",
871 dd->ipath_majrev, dd->ipath_minrev);
872 ret = 1;
873 } else if (dd->ipath_minrev == 1) {
874 /* Rev1 chips are prototype. Complain, but allow use */
875 ipath_dev_err(dd, "Unsupported hardware "
876 "revision %u.%u, Contact support@qlogic.com\n",
877 dd->ipath_majrev, dd->ipath_minrev);
878 ret = 0;
879 } else
880 ret = 0;
881
882 /*
883 * Set here not in ipath_init_*_funcs because we have to do
884 * it after we can read chip registers.
885 */
886 dd->ipath_ureg_align = 0x10000; /* 64KB alignment */
887
888 return ret;
889}
890
891/**
892 * ipath_7220_init_hwerrors - enable hardware errors
893 * @dd: the infinipath device
894 *
895 * now that we have finished initializing everything that might reasonably
896 * cause a hardware error, and cleared those errors bits as they occur,
897 * we can enable hardware errors in the mask (potentially enabling
898 * freeze mode), and enable hardware errors as errors (along with
899 * everything else) in errormask
900 */
901static void ipath_7220_init_hwerrors(struct ipath_devdata *dd)
902{
903 ipath_err_t val;
904 u64 extsval;
905
906 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
907
908 if (!(extsval & (INFINIPATH_EXTS_MEMBIST_ENDTEST |
909 INFINIPATH_EXTS_MEMBIST_DISABLED)))
910 ipath_dev_err(dd, "MemBIST did not complete!\n");
911 if (extsval & INFINIPATH_EXTS_MEMBIST_DISABLED)
912 dev_info(&dd->pcidev->dev, "MemBIST is disabled.\n");
913
914 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
915
916 if (!dd->ipath_boardrev) /* no PLL for Emulator */
917 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
918
919 if (dd->ipath_minrev == 1)
920 val &= ~(1ULL << 42); /* TXE LaunchFIFO Parity rev1 issue */
921
922 val &= ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR;
923 dd->ipath_hwerrmask = val;
924
925 /*
926 * special trigger "error" is for debugging purposes. It
927 * works around a processor/chipset problem. The error
928 * interrupt allows us to count occurrences, but we don't
929 * want to pay the overhead for normal use. Emulation only
930 */
931 if (!dd->ipath_boardrev)
932 dd->ipath_maskederrs = INFINIPATH_E_SENDSPECIALTRIGGER;
933}
934
935/*
936 * All detailed interaction with the SerDes has been moved to ipath_sd7220.c
937 *
938 * The portion of IBA7220-specific bringup_serdes() that actually deals with
939 * registers and memory within the SerDes itself is ipath_sd7220_init().
940 */
941
942/**
943 * ipath_7220_bringup_serdes - bring up the serdes
944 * @dd: the infinipath device
945 */
946static int ipath_7220_bringup_serdes(struct ipath_devdata *dd)
947{
948 int ret = 0;
949 u64 val, prev_val, guid;
950 int was_reset; /* Note whether uC was reset */
951
952 ipath_dbg("Trying to bringup serdes\n");
953
954 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
955 INFINIPATH_HWE_SERDESPLLFAILED) {
956 ipath_dbg("At start, serdes PLL failed bit set "
957 "in hwerrstatus, clearing and continuing\n");
958 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
959 INFINIPATH_HWE_SERDESPLLFAILED);
960 }
961
962 if (!dd->ipath_ibcddrctrl) {
963 /* not on re-init after reset */
964 dd->ipath_ibcddrctrl =
965 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrctrl);
966
967 if (dd->ipath_link_speed_enabled ==
968 (IPATH_IB_SDR | IPATH_IB_DDR))
969 dd->ipath_ibcddrctrl |=
970 IBA7220_IBC_SPEED_AUTONEG_MASK |
971 IBA7220_IBC_IBTA_1_2_MASK;
972 else
973 dd->ipath_ibcddrctrl |=
974 dd->ipath_link_speed_enabled == IPATH_IB_DDR
975 ? IBA7220_IBC_SPEED_DDR :
976 IBA7220_IBC_SPEED_SDR;
977 if ((dd->ipath_link_width_enabled & (IB_WIDTH_1X |
978 IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X))
979 dd->ipath_ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
980 else
981 dd->ipath_ibcddrctrl |=
982 dd->ipath_link_width_enabled == IB_WIDTH_4X
983 ? IBA7220_IBC_WIDTH_4X_ONLY :
984 IBA7220_IBC_WIDTH_1X_ONLY;
985
986 /* always enable these on driver reload, not sticky */
987 dd->ipath_ibcddrctrl |=
988 IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
989 dd->ipath_ibcddrctrl |=
990 IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
991 /*
992 * automatic lane reversal detection for receive
993 * doesn't work correctly in rev 1, so disable it
994 * on that rev, otherwise enable (disabling not
995 * sticky across reload for >rev1)
996 */
997 if (dd->ipath_minrev == 1)
998 dd->ipath_ibcddrctrl &=
999 ~IBA7220_IBC_LANE_REV_SUPPORTED;
1000 else
1001 dd->ipath_ibcddrctrl |=
1002 IBA7220_IBC_LANE_REV_SUPPORTED;
1003 }
1004
1005 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
1006 dd->ipath_ibcddrctrl);
1007
1008 ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl), 0Ull);
1009
1010 /* IBA7220 has SERDES MPU reset in D0 of what _was_ IBPLLCfg */
1011 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
1012 /* remember if uC was in Reset or not, for dactrim */
1013 was_reset = (val & 1);
1014 ipath_cdbg(VERBOSE, "IBReset %s xgxsconfig %llx\n",
1015 was_reset ? "Asserted" : "Negated", (unsigned long long)
1016 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1017
1018 if (dd->ipath_boardrev) {
1019 /*
1020 * Hardware is not emulator, and may have been reset. Init it.
1021 * Below will release reset, but needs to know if chip was
1022 * originally in reset, to only trim DACs on first time
1023 * after chip reset or powercycle (not driver reload)
1024 */
1025 ret = ipath_sd7220_init(dd, was_reset);
1026 }
1027
1028 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1029 prev_val = val;
1030 val |= INFINIPATH_XGXS_FC_SAFE;
1031 if (val != prev_val) {
1032 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1033 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1034 }
1035 if (val & INFINIPATH_XGXS_RESET)
1036 val &= ~INFINIPATH_XGXS_RESET;
1037 if (val != prev_val)
1038 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1039
1040 ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n",
1041 (unsigned long long)
1042 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig),
1043 prev_val);
1044
1045 guid = be64_to_cpu(dd->ipath_guid);
1046
1047 if (!guid) {
1048 /* have to have something, so use likely unique tsc */
1049 guid = get_cycles();
1050 ipath_dbg("No GUID for heartbeat, faking %llx\n",
1051 (unsigned long long)guid);
1052 } else
1053 ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n", guid);
1054 ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid);
1055 return ret;
1056}
1057
1058static void ipath_7220_config_jint(struct ipath_devdata *dd,
1059 u16 idle_ticks, u16 max_packets)
1060{
1061
1062 /*
1063 * We can request a receive interrupt for 1 or more packets
1064 * from current offset.
1065 */
1066 if (idle_ticks == 0 || max_packets == 0)
1067 /* interrupt after one packet if no mitigation */
1068 dd->ipath_rhdrhead_intr_off =
1069 1ULL << IBA7220_HDRHEAD_PKTINT_SHIFT;
1070 else
1071 /* Turn off RcvHdrHead interrupts if using mitigation */
1072 dd->ipath_rhdrhead_intr_off = 0ULL;
1073
1074 /* refresh kernel RcvHdrHead registers... */
1075 ipath_write_ureg(dd, ur_rcvhdrhead,
1076 dd->ipath_rhdrhead_intr_off |
1077 dd->ipath_pd[0]->port_head, 0);
1078
1079 dd->ipath_jint_max_packets = max_packets;
1080 dd->ipath_jint_idle_ticks = idle_ticks;
1081 ipath_write_kreg(dd, dd->ipath_kregs->kr_jintreload,
1082 ((u64) max_packets << INFINIPATH_JINT_PACKETSHIFT) |
1083 idle_ticks);
1084}
1085
1086/**
1087 * ipath_7220_quiet_serdes - set serdes to txidle
1088 * @dd: the infinipath device
1089 * Called when driver is being unloaded
1090 */
1091static void ipath_7220_quiet_serdes(struct ipath_devdata *dd)
1092{
1093 u64 val;
1094 dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
1095 wake_up(&dd->ipath_autoneg_wait);
1096 cancel_delayed_work(&dd->ipath_autoneg_work);
1097 flush_scheduled_work();
1098 ipath_shutdown_relock_poll(dd);
1099 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1100 val |= INFINIPATH_XGXS_RESET;
1101 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1102}
1103
1104static int ipath_7220_intconfig(struct ipath_devdata *dd)
1105{
1106 ipath_7220_config_jint(dd, dd->ipath_jint_idle_ticks,
1107 dd->ipath_jint_max_packets);
1108 return 0;
1109}
1110
1111/**
1112 * ipath_setup_7220_setextled - set the state of the two external LEDs
1113 * @dd: the infinipath device
1114 * @lst: the L state
1115 * @ltst: the LT state
1116 *
1117 * These LEDs indicate the physical and logical state of IB link.
1118 * For this chip (at least with recommended board pinouts), LED1
1119 * is Yellow (logical state) and LED2 is Green (physical state),
1120 *
1121 * Note: We try to match the Mellanox HCA LED behavior as best
1122 * we can. Green indicates physical link state is OK (something is
1123 * plugged in, and we can train).
1124 * Amber indicates the link is logically up (ACTIVE).
1125 * Mellanox further blinks the amber LED to indicate data packet
1126 * activity, but we have no hardware support for that, so it would
1127 * require waking up every 10-20 msecs and checking the counters
1128 * on the chip, and then turning the LED off if appropriate. That's
1129 * visible overhead, so not something we will do.
1130 *
1131 */
1132static void ipath_setup_7220_setextled(struct ipath_devdata *dd, u64 lst,
1133 u64 ltst)
1134{
1135 u64 extctl, ledblink = 0;
1136 unsigned long flags = 0;
1137
1138 /* the diags use the LED to indicate diag info, so we leave
1139 * the external LED alone when the diags are running */
1140 if (ipath_diag_inuse)
1141 return;
1142
1143 /* Allow override of LED display for, e.g. Locating system in rack */
1144 if (dd->ipath_led_override) {
1145 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1146 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1147 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1148 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1149 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1150 : INFINIPATH_IBCS_L_STATE_DOWN;
1151 }
1152
1153 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1154 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1155 INFINIPATH_EXTC_LED2PRIPORT_ON);
1156 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) {
1157 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1158 /*
1159 * counts are in chip clock (4ns) periods.
1160 * This is 1/16 sec (66.6ms) on,
1161 * 3/16 sec (187.5 ms) off, with packets rcvd
1162 */
1163 ledblink = ((66600*1000UL/4) << IBA7220_LEDBLINK_ON_SHIFT)
1164 | ((187500*1000UL/4) << IBA7220_LEDBLINK_OFF_SHIFT);
1165 }
1166 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1167 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1168 dd->ipath_extctrl = extctl;
1169 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1170 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1171
1172 if (ledblink) /* blink the LED on packet receive */
1173 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvpktledcnt,
1174 ledblink);
1175}
1176
1177/*
1178 * Similar to pci_intx(pdev, 1), except that we make sure
1179 * msi is off...
1180 */
1181static void ipath_enable_intx(struct pci_dev *pdev)
1182{
1183 u16 cw, new;
1184 int pos;
1185
1186 /* first, turn on INTx */
1187 pci_read_config_word(pdev, PCI_COMMAND, &cw);
1188 new = cw & ~PCI_COMMAND_INTX_DISABLE;
1189 if (new != cw)
1190 pci_write_config_word(pdev, PCI_COMMAND, new);
1191
1192 /* then turn off MSI */
1193 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1194 if (pos) {
1195 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1196 new = cw & ~PCI_MSI_FLAGS_ENABLE;
1197 if (new != cw)
1198 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
1199 }
1200}
1201
1202static int ipath_msi_enabled(struct pci_dev *pdev)
1203{
1204 int pos, ret = 0;
1205
1206 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1207 if (pos) {
1208 u16 cw;
1209
1210 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1211 ret = !!(cw & PCI_MSI_FLAGS_ENABLE);
1212 }
1213 return ret;
1214}
1215
1216/*
1217 * disable msi interrupt if enabled, and clear the flag.
1218 * flag is used primarily for the fallback to IntX, but
1219 * is also used in reinit after reset as a flag.
1220 */
1221static void ipath_7220_nomsi(struct ipath_devdata *dd)
1222{
1223 dd->ipath_msi_lo = 0;
1224#ifdef CONFIG_PCI_MSI
1225 if (ipath_msi_enabled(dd->pcidev)) {
1226 /*
1227 * free, but don't zero; later kernels require
1228 * it be freed before disable_msi, so the intx
1229 * setup has to request it again.
1230 */
1231 if (dd->ipath_irq)
1232 free_irq(dd->ipath_irq, dd);
1233 pci_disable_msi(dd->pcidev);
1234 }
1235#endif
1236}
1237
1238/*
1239 * ipath_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1240 * @dd: the infinipath device
1241 *
1242 * Nothing but msi interrupt cleanup for now.
1243 *
1244 * This is called during driver unload.
1245 */
1246static void ipath_setup_7220_cleanup(struct ipath_devdata *dd)
1247{
1248 ipath_7220_nomsi(dd);
1249}
1250
1251
1252static void ipath_7220_pcie_params(struct ipath_devdata *dd, u32 boardrev)
1253{
1254 u16 linkstat, minwidth, speed;
1255 int pos;
1256
1257 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
1258 if (!pos) {
1259 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
1260 goto bail;
1261 }
1262
1263 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
1264 &linkstat);
1265 /*
1266 * speed is bits 0-4, linkwidth is bits 4-8
1267 * no defines for them in headers
1268 */
1269 speed = linkstat & 0xf;
1270 linkstat >>= 4;
1271 linkstat &= 0x1f;
1272 dd->ipath_lbus_width = linkstat;
1273 switch (boardrev) {
1274 case 0:
1275 case 2:
1276 case 10:
1277 case 12:
1278 minwidth = 16; /* x16 capable boards */
1279 break;
1280 default:
1281 minwidth = 8; /* x8 capable boards */
1282 break;
1283 }
1284
1285 switch (speed) {
1286 case 1:
1287 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
1288 break;
1289 case 2:
1290 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
1291 break;
1292 default: /* not defined, assume gen1 */
1293 dd->ipath_lbus_speed = 2500;
1294 break;
1295 }
1296
1297 if (linkstat < minwidth)
1298 ipath_dev_err(dd,
1299 "PCIe width %u (x%u HCA), performance "
1300 "reduced\n", linkstat, minwidth);
1301 else
1302 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x%u HCA)\n",
1303 dd->ipath_lbus_speed, linkstat, minwidth);
1304
1305 if (speed != 1)
1306 ipath_dev_err(dd,
1307 "PCIe linkspeed %u is incorrect; "
1308 "should be 1 (2500)!\n", speed);
1309
1310bail:
1311 /* fill in string, even on errors */
1312 snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
1313 "PCIe,%uMHz,x%u\n",
1314 dd->ipath_lbus_speed,
1315 dd->ipath_lbus_width);
1316 return;
1317}
1318
1319
1320/**
1321 * ipath_setup_7220_config - setup PCIe config related stuff
1322 * @dd: the infinipath device
1323 * @pdev: the PCI device
1324 *
1325 * The pci_enable_msi() call will fail on systems with MSI quirks
1326 * such as those with AMD8131, even if the device of interest is not
1327 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
1328 * late in 2.6.16).
1329 * All that can be done is to edit the kernel source to remove the quirk
1330 * check until that is fixed.
1331 * We do not need to call enable_msi() for our HyperTransport chip,
1332 * even though it uses MSI, and we want to avoid the quirk warning, so
1333 * So we call enable_msi only for PCIe. If we do end up needing
1334 * pci_enable_msi at some point in the future for HT, we'll move the
1335 * call back into the main init_one code.
1336 * We save the msi lo and hi values, so we can restore them after
1337 * chip reset (the kernel PCI infrastructure doesn't yet handle that
1338 * correctly).
1339 */
1340static int ipath_setup_7220_config(struct ipath_devdata *dd,
1341 struct pci_dev *pdev)
1342{
1343 int pos, ret = -1;
1344 u32 boardrev;
1345
1346 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
1347#ifdef CONFIG_PCI_MSI
1348 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1349 if (!strcmp(int_type, "force_msi") || !strcmp(int_type, "auto"))
1350 ret = pci_enable_msi(pdev);
1351 if (ret) {
1352 if (!strcmp(int_type, "force_msi")) {
1353 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1354 "force_msi is on, so not continuing.\n",
1355 ret);
1356 return ret;
1357 }
1358
1359 ipath_enable_intx(pdev);
1360 if (!strcmp(int_type, "auto"))
1361 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1362 "falling back to INTx\n", ret);
1363 } else if (pos) {
1364 u16 control;
1365 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
1366 &dd->ipath_msi_lo);
1367 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
1368 &dd->ipath_msi_hi);
1369 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS,
1370 &control);
1371 /* now save the data (vector) info */
1372 pci_read_config_word(pdev,
1373 pos + ((control & PCI_MSI_FLAGS_64BIT)
1374 ? PCI_MSI_DATA_64 :
1375 PCI_MSI_DATA_32),
1376 &dd->ipath_msi_data);
1377 } else
1378 ipath_dev_err(dd, "Can't find MSI capability, "
1379 "can't save MSI settings for reset\n");
1380#else
1381 ipath_dbg("PCI_MSI not configured, using IntX interrupts\n");
1382 ipath_enable_intx(pdev);
1383#endif
1384
1385 dd->ipath_irq = pdev->irq;
1386
1387 /*
1388 * We save the cachelinesize also, although it doesn't
1389 * really matter.
1390 */
1391 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1392 &dd->ipath_pci_cacheline);
1393
1394 /*
1395 * this function called early, ipath_boardrev not set yet. Can't
1396 * use ipath_read_kreg64() yet, too early in init, so use readq()
1397 */
1398 boardrev = (readq(&dd->ipath_kregbase[dd->ipath_kregs->kr_revision])
1399 >> INFINIPATH_R_BOARDID_SHIFT) & INFINIPATH_R_BOARDID_MASK;
1400
1401 ipath_7220_pcie_params(dd, boardrev);
1402
1403 dd->ipath_flags |= IPATH_NODMA_RTAIL | IPATH_HAS_SEND_DMA |
1404 IPATH_HAS_PBC_CNT | IPATH_HAS_THRESH_UPDATE;
1405 dd->ipath_pioupd_thresh = 4U; /* set default update threshold */
1406 return 0;
1407}
1408
1409static void ipath_init_7220_variables(struct ipath_devdata *dd)
1410{
1411 /*
1412 * setup the register offsets, since they are different for each
1413 * chip
1414 */
1415 dd->ipath_kregs = &ipath_7220_kregs;
1416 dd->ipath_cregs = &ipath_7220_cregs;
1417
1418 /*
1419 * bits for selecting i2c direction and values,
1420 * used for I2C serial flash
1421 */
1422 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1423 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1424 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1425 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1426
1427 /*
1428 * Fill in data for field-values that change in IBA7220.
1429 * We dynamically specify only the mask for LINKTRAININGSTATE
1430 * and only the shift for LINKSTATE, as they are the only ones
1431 * that change. Also precalculate the 3 link states of interest
1432 * and the combined mask.
1433 */
1434 dd->ibcs_ls_shift = IBA7220_IBCS_LINKSTATE_SHIFT;
1435 dd->ibcs_lts_mask = IBA7220_IBCS_LINKTRAININGSTATE_MASK;
1436 dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1437 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1438 dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1439 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1440 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1441 dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1442 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1443 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1444 dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1445 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1446 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1447
1448 /*
1449 * Fill in data for ibcc field-values that change in IBA7220.
1450 * We dynamically specify only the mask for LINKINITCMD
1451 * and only the shift for LINKCMD and MAXPKTLEN, as they are
1452 * the only ones that change.
1453 */
1454 dd->ibcc_lic_mask = IBA7220_IBCC_LINKINITCMD_MASK;
1455 dd->ibcc_lc_shift = IBA7220_IBCC_LINKCMD_SHIFT;
1456 dd->ibcc_mpl_shift = IBA7220_IBCC_MAXPKTLEN_SHIFT;
1457
1458 /* Fill in shifts for RcvCtrl. */
1459 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1460 dd->ipath_r_intravail_shift = IBA7220_R_INTRAVAIL_SHIFT;
1461 dd->ipath_r_tailupd_shift = IBA7220_R_TAILUPD_SHIFT;
1462 dd->ipath_r_portcfg_shift = IBA7220_R_PORTCFG_SHIFT;
1463
1464 /* variables for sanity checking interrupt and errors */
1465 dd->ipath_hwe_bitsextant =
1466 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1467 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1468 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1469 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1470 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1471 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1472 INFINIPATH_HWE_PCIE1PLLFAILED |
1473 INFINIPATH_HWE_PCIE0PLLFAILED |
1474 INFINIPATH_HWE_PCIEPOISONEDTLP |
1475 INFINIPATH_HWE_PCIECPLTIMEOUT |
1476 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1477 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1478 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1479 INFINIPATH_HWE_MEMBISTFAILED |
1480 INFINIPATH_HWE_COREPLL_FBSLIP |
1481 INFINIPATH_HWE_COREPLL_RFSLIP |
1482 INFINIPATH_HWE_SERDESPLLFAILED |
1483 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1484 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR |
1485 INFINIPATH_HWE_PCIECPLDATAQUEUEERR |
1486 INFINIPATH_HWE_PCIECPLHDRQUEUEERR |
1487 INFINIPATH_HWE_SDMAMEMREADERR |
1488 INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED |
1489 INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT |
1490 INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT |
1491 INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT |
1492 INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT |
1493 INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR |
1494 INFINIPATH_HWE_IB_UC_MEMORYPARITYERR |
1495 INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR |
1496 INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR;
1497 dd->ipath_i_bitsextant =
1498 INFINIPATH_I_SDMAINT | INFINIPATH_I_SDMADISABLED |
1499 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1500 (INFINIPATH_I_RCVAVAIL_MASK <<
1501 INFINIPATH_I_RCVAVAIL_SHIFT) |
1502 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1503 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO |
1504 INFINIPATH_I_JINT | INFINIPATH_I_SERDESTRIMDONE;
1505 dd->ipath_e_bitsextant =
1506 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1507 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1508 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1509 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1510 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1511 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1512 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1513 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1514 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1515 INFINIPATH_E_SENDSPECIALTRIGGER |
1516 INFINIPATH_E_SDMADISABLED | INFINIPATH_E_SMINPKTLEN |
1517 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNDERRUN |
1518 INFINIPATH_E_SPKTLEN | INFINIPATH_E_SDROPPEDSMPPKT |
1519 INFINIPATH_E_SDROPPEDDATAPKT |
1520 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1521 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_SENDBUFMISUSE |
1522 INFINIPATH_E_SDMAGENMISMATCH | INFINIPATH_E_SDMAOUTOFBOUND |
1523 INFINIPATH_E_SDMATAILOUTOFBOUND | INFINIPATH_E_SDMABASE |
1524 INFINIPATH_E_SDMA1STDESC | INFINIPATH_E_SDMARPYTAG |
1525 INFINIPATH_E_SDMADWEN | INFINIPATH_E_SDMAMISSINGDW |
1526 INFINIPATH_E_SDMAUNEXPDATA |
1527 INFINIPATH_E_IBSTATUSCHANGED | INFINIPATH_E_INVALIDADDR |
1528 INFINIPATH_E_RESET | INFINIPATH_E_HARDWARE |
1529 INFINIPATH_E_SDMADESCADDRMISALIGN |
1530 INFINIPATH_E_INVALIDEEPCMD;
1531
1532 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1533 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1534 dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1535 dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1536 dd->ipath_flags |= IPATH_INTREG_64 | IPATH_HAS_MULT_IB_SPEED
1537 | IPATH_HAS_LINK_LATENCY;
1538
1539 /*
1540 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1541 * 2 is Some Misc, 3 is reserved for future.
1542 */
1543 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1544 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1545 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1546
1547 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1548 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1549 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1550
1551 dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1552
1553 ipath_linkrecovery = 0;
1554
1555 init_waitqueue_head(&dd->ipath_autoneg_wait);
1556 INIT_DELAYED_WORK(&dd->ipath_autoneg_work, autoneg_work);
1557
1558 dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1559 dd->ipath_link_speed_supported = IPATH_IB_SDR | IPATH_IB_DDR;
1560
1561 dd->ipath_link_width_enabled = dd->ipath_link_width_supported;
1562 dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1563 /*
1564 * set the initial values to reasonable default, will be set
1565 * for real when link is up.
1566 */
1567 dd->ipath_link_width_active = IB_WIDTH_4X;
1568 dd->ipath_link_speed_active = IPATH_IB_SDR;
1569 dd->delay_mult = rate_to_delay[0][1];
1570}
1571
1572
1573/*
1574 * Setup the MSI stuff again after a reset. I'd like to just call
1575 * pci_enable_msi() and request_irq() again, but when I do that,
1576 * the MSI enable bit doesn't get set in the command word, and
1577 * we switch to to a different interrupt vector, which is confusing,
1578 * so I instead just do it all inline. Perhaps somehow can tie this
1579 * into the PCIe hotplug support at some point
1580 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1581 * or free_irq() at the start of ipath_setup_7220_reset().
1582 */
1583static int ipath_reinit_msi(struct ipath_devdata *dd)
1584{
1585 int ret = 0;
1586#ifdef CONFIG_PCI_MSI
1587 int pos;
1588 u16 control;
1589 if (!dd->ipath_msi_lo) /* Using intX, or init problem */
1590 goto bail;
1591
1592 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
1593 if (!pos) {
1594 ipath_dev_err(dd, "Can't find MSI capability, "
1595 "can't restore MSI settings\n");
1596 goto bail;
1597 }
1598 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1599 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1600 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1601 dd->ipath_msi_lo);
1602 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1603 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1604 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1605 dd->ipath_msi_hi);
1606 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1607 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1608 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1609 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1610 control, control | PCI_MSI_FLAGS_ENABLE);
1611 control |= PCI_MSI_FLAGS_ENABLE;
1612 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1613 control);
1614 }
1615 /* now rewrite the data (vector) info */
1616 pci_write_config_word(dd->pcidev, pos +
1617 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1618 dd->ipath_msi_data);
1619 ret = 1;
1620bail:
1621#endif
1622 if (!ret) {
1623 ipath_dbg("Using IntX, MSI disabled or not configured\n");
1624 ipath_enable_intx(dd->pcidev);
1625 ret = 1;
1626 }
1627 /*
1628 * We restore the cachelinesize also, although it doesn't really
1629 * matter.
1630 */
1631 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1632 dd->ipath_pci_cacheline);
1633 /* and now set the pci master bit again */
1634 pci_set_master(dd->pcidev);
1635
1636 return ret;
1637}
1638
1639/*
1640 * This routine sleeps, so it can only be called from user context, not
1641 * from interrupt context. If we need interrupt context, we can split
1642 * it into two routines.
1643 */
1644static int ipath_setup_7220_reset(struct ipath_devdata *dd)
1645{
1646 u64 val;
1647 int i;
1648 int ret;
1649 u16 cmdval;
1650
1651 pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1652
1653 /* Use dev_err so it shows up in logs, etc. */
1654 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1655
1656 /* keep chip from being accessed in a few places */
1657 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_PRESENT);
1658 val = dd->ipath_control | INFINIPATH_C_RESET;
1659 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1660 mb();
1661
1662 for (i = 1; i <= 5; i++) {
1663 int r;
1664
1665 /*
1666 * Allow MBIST, etc. to complete; longer on each retry.
1667 * We sometimes get machine checks from bus timeout if no
1668 * response, so for now, make it *really* long.
1669 */
1670 msleep(1000 + (1 + i) * 2000);
1671 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1672 dd->ipath_pcibar0);
1673 if (r)
1674 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
1675 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1676 dd->ipath_pcibar1);
1677 if (r)
1678 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
1679 /* now re-enable memory access */
1680 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1681 r = pci_enable_device(dd->pcidev);
1682 if (r)
1683 ipath_dev_err(dd, "pci_enable_device failed after "
1684 "reset: %d\n", r);
1685 /*
1686 * whether it fully enabled or not, mark as present,
1687 * again (but not INITTED)
1688 */
1689 dd->ipath_flags |= IPATH_PRESENT;
1690 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1691 if (val == dd->ipath_revision) {
1692 ipath_cdbg(VERBOSE, "Got matching revision "
1693 "register %llx on try %d\n",
1694 (unsigned long long) val, i);
1695 ret = ipath_reinit_msi(dd);
1696 goto bail;
1697 }
1698 /* Probably getting -1 back */
1699 ipath_dbg("Didn't get expected revision register, "
1700 "got %llx, try %d\n", (unsigned long long) val,
1701 i + 1);
1702 }
1703 ret = 0; /* failed */
1704
1705bail:
1706 if (ret)
1707 ipath_7220_pcie_params(dd, dd->ipath_boardrev);
1708
1709 return ret;
1710}
1711
1712/**
1713 * ipath_7220_put_tid - write a TID to the chip
1714 * @dd: the infinipath device
1715 * @tidptr: pointer to the expected TID (in chip) to udpate
1716 * @tidtype: 0 for eager, 1 for expected
1717 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1718 *
1719 * This exists as a separate routine to allow for selection of the
1720 * appropriate "flavor". The static calls in cleanup just use the
1721 * revision-agnostic form, as they are not performance critical.
1722 */
1723static void ipath_7220_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1724 u32 type, unsigned long pa)
1725{
1726 if (pa != dd->ipath_tidinvalid) {
1727 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
1728
1729 /* paranoia checks */
1730 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
1731 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1732 "not 2KB aligned!\n", pa);
1733 return;
1734 }
1735 if (pa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
1736 ipath_dev_err(dd,
1737 "BUG: Physical page address 0x%lx "
1738 "larger than supported\n", pa);
1739 return;
1740 }
1741
1742 if (type == RCVHQ_RCV_TYPE_EAGER)
1743 chippa |= dd->ipath_tidtemplate;
1744 else /* for now, always full 4KB page */
1745 chippa |= IBA7220_TID_SZ_4K;
1746 writeq(chippa, tidptr);
1747 } else
1748 writeq(pa, tidptr);
1749 mmiowb();
1750}
1751
1752/**
1753 * ipath_7220_clear_tid - clear all TID entries for a port, expected and eager
1754 * @dd: the infinipath device
1755 * @port: the port
1756 *
1757 * clear all TID entries for a port, expected and eager.
1758 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1759 * not 64, but they are still on 64 bit boundaries, so tidbase
1760 * is declared as u64 * for the pointer math, even though we write 32 bits
1761 */
1762static void ipath_7220_clear_tids(struct ipath_devdata *dd, unsigned port)
1763{
1764 u64 __iomem *tidbase;
1765 unsigned long tidinv;
1766 int i;
1767
1768 if (!dd->ipath_kregbase)
1769 return;
1770
1771 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1772
1773 tidinv = dd->ipath_tidinvalid;
1774 tidbase = (u64 __iomem *)
1775 ((char __iomem *)(dd->ipath_kregbase) +
1776 dd->ipath_rcvtidbase +
1777 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1778
1779 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1780 ipath_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1781 tidinv);
1782
1783 tidbase = (u64 __iomem *)
1784 ((char __iomem *)(dd->ipath_kregbase) +
1785 dd->ipath_rcvegrbase + port_egrtid_idx(dd, port)
1786 * sizeof(*tidbase));
1787
1788 for (i = port ? dd->ipath_rcvegrcnt : dd->ipath_p0_rcvegrcnt; i; i--)
1789 ipath_7220_put_tid(dd, &tidbase[i-1], RCVHQ_RCV_TYPE_EAGER,
1790 tidinv);
1791}
1792
1793/**
1794 * ipath_7220_tidtemplate - setup constants for TID updates
1795 * @dd: the infinipath device
1796 *
1797 * We setup stuff that we use a lot, to avoid calculating each time
1798 */
1799static void ipath_7220_tidtemplate(struct ipath_devdata *dd)
1800{
1801 /* For now, we always allocate 4KB buffers (at init) so we can
1802 * receive max size packets. We may want a module parameter to
1803 * specify 2KB or 4KB and/or make be per port instead of per device
1804 * for those who want to reduce memory footprint. Note that the
1805 * ipath_rcvhdrentsize size must be large enough to hold the largest
1806 * IB header (currently 96 bytes) that we expect to handle (plus of
1807 * course the 2 dwords of RHF).
1808 */
1809 if (dd->ipath_rcvegrbufsize == 2048)
1810 dd->ipath_tidtemplate = IBA7220_TID_SZ_2K;
1811 else if (dd->ipath_rcvegrbufsize == 4096)
1812 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1813 else {
1814 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1815 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1816 4096);
1817 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1818 }
1819 dd->ipath_tidinvalid = 0;
1820}
1821
1822static int ipath_7220_early_init(struct ipath_devdata *dd)
1823{
1824 u32 i, s;
1825
1826 if (strcmp(int_type, "auto") &&
1827 strcmp(int_type, "force_msi") &&
1828 strcmp(int_type, "force_intx")) {
1829 ipath_dev_err(dd, "Invalid interrupt_type: '%s', expecting "
1830 "auto, force_msi or force_intx\n", int_type);
1831 return -EINVAL;
1832 }
1833
1834 /*
1835 * Control[4] has been added to change the arbitration within
1836 * the SDMA engine between favoring data fetches over descriptor
1837 * fetches. ipath_sdma_fetch_arb==0 gives data fetches priority.
1838 */
1839 if (ipath_sdma_fetch_arb && (dd->ipath_minrev > 1))
1840 dd->ipath_control |= 1<<4;
1841
1842 dd->ipath_flags |= IPATH_4BYTE_TID;
1843
1844 /*
1845 * For openfabrics, we need to be able to handle an IB header of
1846 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1847 * made them the same size as the PIO buffers. This chip does not
1848 * handle arbitrary size buffers, so we need the header large enough
1849 * to handle largest IB header, but still have room for a 2KB MTU
1850 * standard IB packet.
1851 */
1852 dd->ipath_rcvhdrentsize = 24;
1853 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1854 dd->ipath_rhf_offset =
1855 dd->ipath_rcvhdrentsize - sizeof(u64) / sizeof(u32);
1856
1857 dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1858 /*
1859 * the min() check here is currently a nop, but it may not always
1860 * be, depending on just how we do ipath_rcvegrbufsize
1861 */
1862 dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1863 dd->ipath_piosize2k,
1864 dd->ipath_rcvegrbufsize +
1865 (dd->ipath_rcvhdrentsize << 2));
1866 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1867
1868 ipath_7220_config_jint(dd, INFINIPATH_JINT_DEFAULT_IDLE_TICKS,
1869 INFINIPATH_JINT_DEFAULT_MAX_PACKETS);
1870
1871 if (dd->ipath_boardrev) /* no eeprom on emulator */
1872 ipath_get_eeprom_info(dd);
1873
1874 /* start of code to check and print procmon */
1875 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1876 s &= ~(1U<<31); /* clear done bit */
1877 s |= 1U<<14; /* clear counter (write 1 to clear) */
1878 ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1879 /* make sure clear_counter low long enough before start */
1880 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1881 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1882
1883 s &= ~(1U<<14); /* allow counter to count (before starting) */
1884 ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1885 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1886 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1887 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1888
1889 s |= 1U<<15; /* start the counter */
1890 s &= ~(1U<<31); /* clear done bit */
1891 s &= ~0x7ffU; /* clear frequency bits */
1892 s |= 0xe29; /* set frequency bits, in case cleared */
1893 ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1894
1895 s = 0;
1896 for (i = 500; i > 0 && !(s&(1ULL<<31)); i--) {
1897 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1898 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1899 }
1900 if (!(s&(1U<<31)))
1901 ipath_dev_err(dd, "ProcMon register not valid: 0x%x\n", s);
1902 else
1903 ipath_dbg("ProcMon=0x%x, count=0x%x\n", s, (s>>16)&0x1ff);
1904
1905 return 0;
1906}
1907
1908/**
1909 * ipath_init_7220_get_base_info - set chip-specific flags for user code
1910 * @pd: the infinipath port
1911 * @kbase: ipath_base_info pointer
1912 *
1913 * We set the PCIE flag because the lower bandwidth on PCIe vs
1914 * HyperTransport can affect some user packet algorithims.
1915 */
1916static int ipath_7220_get_base_info(struct ipath_portdata *pd, void *kbase)
1917{
1918 struct ipath_base_info *kinfo = kbase;
1919
1920 kinfo->spi_runtime_flags |=
1921 IPATH_RUNTIME_PCIE | IPATH_RUNTIME_NODMA_RTAIL |
1922 IPATH_RUNTIME_SDMA;
1923
1924 return 0;
1925}
1926
1927static void ipath_7220_free_irq(struct ipath_devdata *dd)
1928{
1929 free_irq(dd->ipath_irq, dd);
1930 dd->ipath_irq = 0;
1931}
1932
1933static struct ipath_message_header *
1934ipath_7220_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1935{
1936 u32 offset = ipath_hdrget_offset(rhf_addr);
1937
1938 return (struct ipath_message_header *)
1939 (rhf_addr - dd->ipath_rhf_offset + offset);
1940}
1941
1942static void ipath_7220_config_ports(struct ipath_devdata *dd, ushort cfgports)
1943{
1944 u32 nchipports;
1945
1946 nchipports = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1947 if (!cfgports) {
1948 int ncpus = num_online_cpus();
1949
1950 if (ncpus <= 4)
1951 dd->ipath_portcnt = 5;
1952 else if (ncpus <= 8)
1953 dd->ipath_portcnt = 9;
1954 if (dd->ipath_portcnt)
1955 ipath_dbg("Auto-configured for %u ports, %d cpus "
1956 "online\n", dd->ipath_portcnt, ncpus);
1957 } else if (cfgports <= nchipports)
1958 dd->ipath_portcnt = cfgports;
1959 if (!dd->ipath_portcnt) /* none of the above, set to max */
1960 dd->ipath_portcnt = nchipports;
1961 /*
1962 * chip can be configured for 5, 9, or 17 ports, and choice
1963 * affects number of eager TIDs per port (1K, 2K, 4K).
1964 */
1965 if (dd->ipath_portcnt > 9)
1966 dd->ipath_rcvctrl |= 2ULL << IBA7220_R_PORTCFG_SHIFT;
1967 else if (dd->ipath_portcnt > 5)
1968 dd->ipath_rcvctrl |= 1ULL << IBA7220_R_PORTCFG_SHIFT;
1969 /* else configure for default 5 receive ports */
1970 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1971 dd->ipath_rcvctrl);
1972 dd->ipath_p0_rcvegrcnt = 2048; /* always */
1973 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1974 dd->ipath_pioreserved = 1; /* reserve a buffer */
1975}
1976
1977
1978static int ipath_7220_get_ib_cfg(struct ipath_devdata *dd, int which)
1979{
1980 int lsb, ret = 0;
1981 u64 maskr; /* right-justified mask */
1982
1983 switch (which) {
1984 case IPATH_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
1985 lsb = IBA7220_IBC_HRTBT_SHIFT;
1986 maskr = IBA7220_IBC_HRTBT_MASK;
1987 break;
1988
1989 case IPATH_IB_CFG_LWID_ENB: /* Get allowed Link-width */
1990 ret = dd->ipath_link_width_enabled;
1991 goto done;
1992
1993 case IPATH_IB_CFG_LWID: /* Get currently active Link-width */
1994 ret = dd->ipath_link_width_active;
1995 goto done;
1996
1997 case IPATH_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
1998 ret = dd->ipath_link_speed_enabled;
1999 goto done;
2000
2001 case IPATH_IB_CFG_SPD: /* Get current Link spd */
2002 ret = dd->ipath_link_speed_active;
2003 goto done;
2004
2005 case IPATH_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
2006 lsb = IBA7220_IBC_RXPOL_SHIFT;
2007 maskr = IBA7220_IBC_RXPOL_MASK;
2008 break;
2009
2010 case IPATH_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
2011 lsb = IBA7220_IBC_LREV_SHIFT;
2012 maskr = IBA7220_IBC_LREV_MASK;
2013 break;
2014
2015 case IPATH_IB_CFG_LINKLATENCY:
2016 ret = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrstatus)
2017 & IBA7220_DDRSTAT_LINKLAT_MASK;
2018 goto done;
2019
2020 default:
2021 ret = -ENOTSUPP;
2022 goto done;
2023 }
2024 ret = (int)((dd->ipath_ibcddrctrl >> lsb) & maskr);
2025done:
2026 return ret;
2027}
2028
2029static int ipath_7220_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
2030{
2031 int lsb, ret = 0, setforce = 0;
2032 u64 maskr; /* right-justified mask */
2033
2034 switch (which) {
2035 case IPATH_IB_CFG_LIDLMC:
2036 /*
2037 * Set LID and LMC. Combined to avoid possible hazard
2038 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2039 */
2040 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2041 maskr = IBA7220_IBC_DLIDLMC_MASK;
2042 break;
2043
2044 case IPATH_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2045 if (val & IPATH_IB_HRTBT_ON &&
2046 (dd->ipath_flags & IPATH_NO_HRTBT))
2047 goto bail;
2048 lsb = IBA7220_IBC_HRTBT_SHIFT;
2049 maskr = IBA7220_IBC_HRTBT_MASK;
2050 break;
2051
2052 case IPATH_IB_CFG_LWID_ENB: /* set allowed Link-width */
2053 /*
2054 * As with speed, only write the actual register if
2055 * the link is currently down, otherwise takes effect
2056 * on next link change.
2057 */
2058 dd->ipath_link_width_enabled = val;
2059 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2060 IPATH_LINKDOWN)
2061 goto bail;
2062 /*
2063 * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2064 * will get called because we want update
2065 * link_width_active, and the change may not take
2066 * effect for some time (if we are in POLL), so this
2067 * flag will force the updown routine to be called
2068 * on the next ibstatuschange down interrupt, even
2069 * if it's not an down->up transition.
2070 */
2071 val--; /* convert from IB to chip */
2072 maskr = IBA7220_IBC_WIDTH_MASK;
2073 lsb = IBA7220_IBC_WIDTH_SHIFT;
2074 setforce = 1;
2075 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2076 break;
2077
2078 case IPATH_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2079 /*
2080 * If we turn off IB1.2, need to preset SerDes defaults,
2081 * but not right now. Set a flag for the next time
2082 * we command the link down. As with width, only write the
2083 * actual register if the link is currently down, otherwise
2084 * takes effect on next link change. Since setting is being
2085 * explictly requested (via MAD or sysfs), clear autoneg
2086 * failure status if speed autoneg is enabled.
2087 */
2088 dd->ipath_link_speed_enabled = val;
2089 if (dd->ipath_ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK &&
2090 !(val & (val - 1)))
2091 dd->ipath_presets_needed = 1;
2092 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2093 IPATH_LINKDOWN)
2094 goto bail;
2095 /*
2096 * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2097 * will get called because we want update
2098 * link_speed_active, and the change may not take
2099 * effect for some time (if we are in POLL), so this
2100 * flag will force the updown routine to be called
2101 * on the next ibstatuschange down interrupt, even
2102 * if it's not an down->up transition. When setting
2103 * speed autoneg, clear AUTONEG_FAILED.
2104 */
2105 if (val == (IPATH_IB_SDR | IPATH_IB_DDR)) {
2106 val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2107 IBA7220_IBC_IBTA_1_2_MASK;
2108 dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2109 } else
2110 val = val == IPATH_IB_DDR ? IBA7220_IBC_SPEED_DDR
2111 : IBA7220_IBC_SPEED_SDR;
2112 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2113 IBA7220_IBC_IBTA_1_2_MASK;
2114 lsb = 0; /* speed bits are low bits */
2115 setforce = 1;
2116 break;
2117
2118 case IPATH_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2119 lsb = IBA7220_IBC_RXPOL_SHIFT;
2120 maskr = IBA7220_IBC_RXPOL_MASK;
2121 break;
2122
2123 case IPATH_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2124 lsb = IBA7220_IBC_LREV_SHIFT;
2125 maskr = IBA7220_IBC_LREV_MASK;
2126 break;
2127
2128 default:
2129 ret = -ENOTSUPP;
2130 goto bail;
2131 }
2132 dd->ipath_ibcddrctrl &= ~(maskr << lsb);
2133 dd->ipath_ibcddrctrl |= (((u64) val & maskr) << lsb);
2134 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2135 dd->ipath_ibcddrctrl);
2136 if (setforce)
2137 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2138bail:
2139 return ret;
2140}
2141
2142static void ipath_7220_read_counters(struct ipath_devdata *dd,
2143 struct infinipath_counters *cntrs)
2144{
2145 u64 *counters = (u64 *) cntrs;
2146 int i;
2147
2148 for (i = 0; i < sizeof(*cntrs) / sizeof(u64); i++)
2149 counters[i] = ipath_snap_cntr(dd, i);
2150}
2151
2152/* if we are using MSI, try to fallback to IntX */
2153static int ipath_7220_intr_fallback(struct ipath_devdata *dd)
2154{
2155 if (dd->ipath_msi_lo) {
2156 dev_info(&dd->pcidev->dev, "MSI interrupt not detected,"
2157 " trying IntX interrupts\n");
2158 ipath_7220_nomsi(dd);
2159 ipath_enable_intx(dd->pcidev);
2160 /*
2161 * some newer kernels require free_irq before disable_msi,
2162 * and irq can be changed during disable and intx enable
2163 * and we need to therefore use the pcidev->irq value,
2164 * not our saved MSI value.
2165 */
2166 dd->ipath_irq = dd->pcidev->irq;
2167 if (request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
2168 IPATH_DRV_NAME, dd))
2169 ipath_dev_err(dd,
2170 "Could not re-request_irq for IntX\n");
2171 return 1;
2172 }
2173 return 0;
2174}
2175
2176/*
2177 * reset the XGXS (between serdes and IBC). Slightly less intrusive
2178 * than resetting the IBC or external link state, and useful in some
2179 * cases to cause some retraining. To do this right, we reset IBC
2180 * as well.
2181 */
2182static void ipath_7220_xgxs_reset(struct ipath_devdata *dd)
2183{
2184 u64 val, prev_val;
2185
2186 prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2187 val = prev_val | INFINIPATH_XGXS_RESET;
2188 prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
2189 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2190 dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
2191 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2192 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
2193 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
2194 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2195 dd->ipath_control);
2196}
2197
2198
2199/* Still needs cleanup, too much hardwired stuff */
2200static void autoneg_send(struct ipath_devdata *dd,
2201 u32 *hdr, u32 dcnt, u32 *data)
2202{
2203 int i;
2204 u64 cnt;
2205 u32 __iomem *piobuf;
2206 u32 pnum;
2207
2208 i = 0;
2209 cnt = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
2210 while (!(piobuf = ipath_getpiobuf(dd, cnt, &pnum))) {
2211 if (i++ > 15) {
2212 ipath_dbg("Couldn't get pio buffer for send\n");
2213 return;
2214 }
2215 udelay(2);
2216 }
2217 if (dd->ipath_flags&IPATH_HAS_PBC_CNT)
2218 cnt |= 0x80000000UL<<32; /* mark as VL15 */
2219 writeq(cnt, piobuf);
2220 ipath_flush_wc();
2221 __iowrite32_copy(piobuf + 2, hdr, 7);
2222 __iowrite32_copy(piobuf + 9, data, dcnt);
2223 ipath_flush_wc();
2224}
2225
2226/*
2227 * _start packet gets sent twice at start, _done gets sent twice at end
2228 */
2229static void ipath_autoneg_send(struct ipath_devdata *dd, int which)
2230{
2231 static u32 swapped;
2232 u32 dw, i, hcnt, dcnt, *data;
2233 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
2234 static u32 madpayload_start[0x40] = {
2235 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2236 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2237 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
2238 };
2239 static u32 madpayload_done[0x40] = {
2240 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2241 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2242 0x40000001, 0x1388, 0x15e, /* rest 0's */
2243 };
2244 dcnt = sizeof(madpayload_start)/sizeof(madpayload_start[0]);
2245 hcnt = sizeof(hdr)/sizeof(hdr[0]);
2246 if (!swapped) {
2247 /* for maintainability, do it at runtime */
2248 for (i = 0; i < hcnt; i++) {
2249 dw = (__force u32) cpu_to_be32(hdr[i]);
2250 hdr[i] = dw;
2251 }
2252 for (i = 0; i < dcnt; i++) {
2253 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
2254 madpayload_start[i] = dw;
2255 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
2256 madpayload_done[i] = dw;
2257 }
2258 swapped = 1;
2259 }
2260
2261 data = which ? madpayload_done : madpayload_start;
2262 ipath_cdbg(PKT, "Sending %s special MADs\n", which?"done":"start");
2263
2264 autoneg_send(dd, hdr, dcnt, data);
2265 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2266 udelay(2);
2267 autoneg_send(dd, hdr, dcnt, data);
2268 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2269 udelay(2);
2270}
2271
2272
2273
2274/*
2275 * Do the absolute minimum to cause an IB speed change, and make it
2276 * ready, but don't actually trigger the change. The caller will
2277 * do that when ready (if link is in Polling training state, it will
2278 * happen immediately, otherwise when link next goes down)
2279 *
2280 * This routine should only be used as part of the DDR autonegotation
2281 * code for devices that are not compliant with IB 1.2 (or code that
2282 * fixes things up for same).
2283 *
2284 * When link has gone down, and autoneg enabled, or autoneg has
2285 * failed and we give up until next time we set both speeds, and
2286 * then we want IBTA enabled as well as "use max enabled speed.
2287 */
2288static void set_speed_fast(struct ipath_devdata *dd, u32 speed)
2289{
2290 dd->ipath_ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
2291 IBA7220_IBC_IBTA_1_2_MASK |
2292 (IBA7220_IBC_WIDTH_MASK << IBA7220_IBC_WIDTH_SHIFT));
2293
2294 if (speed == (IPATH_IB_SDR | IPATH_IB_DDR))
2295 dd->ipath_ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
2296 IBA7220_IBC_IBTA_1_2_MASK;
2297 else
2298 dd->ipath_ibcddrctrl |= speed == IPATH_IB_DDR ?
2299 IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2300
2301 /*
2302 * Convert from IB-style 1 = 1x, 2 = 4x, 3 = auto
2303 * to chip-centric 0 = 1x, 1 = 4x, 2 = auto
2304 */
2305 dd->ipath_ibcddrctrl |= (u64)(dd->ipath_link_width_enabled - 1) <<
2306 IBA7220_IBC_WIDTH_SHIFT;
2307 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2308 dd->ipath_ibcddrctrl);
2309 ipath_cdbg(VERBOSE, "setup for IB speed (%x) done\n", speed);
2310}
2311
2312
2313/*
2314 * this routine is only used when we are not talking to another
2315 * IB 1.2-compliant device that we think can do DDR.
2316 * (This includes all existing switch chips as of Oct 2007.)
2317 * 1.2-compliant devices go directly to DDR prior to reaching INIT
2318 */
2319static void try_auto_neg(struct ipath_devdata *dd)
2320{
2321 /*
2322 * required for older non-IB1.2 DDR switches. Newer
2323 * non-IB-compliant switches don't need it, but so far,
2324 * aren't bothered by it either. "Magic constant"
2325 */
2326 ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl),
2327 0x3b9dc07);
2328 dd->ipath_flags |= IPATH_IB_AUTONEG_INPROG;
2329 ipath_autoneg_send(dd, 0);
2330 set_speed_fast(dd, IPATH_IB_DDR);
2331 ipath_toggle_rclkrls(dd);
2332 /* 2 msec is minimum length of a poll cycle */
2333 schedule_delayed_work(&dd->ipath_autoneg_work,
2334 msecs_to_jiffies(2));
2335}
2336
2337
2338static int ipath_7220_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
2339{
2340 int ret = 0;
2341 u32 ltstate = ipath_ib_linkstate(dd, ibcs);
2342
2343 dd->ipath_link_width_active =
2344 ((ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1) ?
2345 IB_WIDTH_4X : IB_WIDTH_1X;
2346 dd->ipath_link_speed_active =
2347 ((ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1) ?
2348 IPATH_IB_DDR : IPATH_IB_SDR;
2349
2350 if (!ibup) {
2351 /*
2352 * when link goes down we don't want aeq running, so it
2353 * won't't interfere with IBC training, etc., and we need
2354 * to go back to the static SerDes preset values
2355 */
2356 if (dd->ipath_x1_fix_tries &&
2357 ltstate <= INFINIPATH_IBCS_LT_STATE_SLEEPQUIET &&
2358 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP)
2359 dd->ipath_x1_fix_tries = 0;
2360 if (!(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2361 IPATH_IB_AUTONEG_INPROG)))
2362 set_speed_fast(dd, dd->ipath_link_speed_enabled);
2363 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)) {
2364 ipath_cdbg(VERBOSE, "Setting RXEQ defaults\n");
2365 ipath_sd7220_presets(dd);
2366 }
2367 /* this might better in ipath_sd7220_presets() */
2368 ipath_set_relock_poll(dd, ibup);
2369 } else {
2370 if (ipath_compat_ddr_negotiate &&
2371 !(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2372 IPATH_IB_AUTONEG_INPROG)) &&
2373 dd->ipath_link_speed_active == IPATH_IB_SDR &&
2374 (dd->ipath_link_speed_enabled &
2375 (IPATH_IB_DDR | IPATH_IB_SDR)) ==
2376 (IPATH_IB_DDR | IPATH_IB_SDR) &&
2377 dd->ipath_autoneg_tries < IPATH_AUTONEG_TRIES) {
2378 /* we are SDR, and DDR auto-negotiation enabled */
2379 ++dd->ipath_autoneg_tries;
2380 ipath_dbg("DDR negotiation try, %u/%u\n",
2381 dd->ipath_autoneg_tries,
2382 IPATH_AUTONEG_TRIES);
2383 try_auto_neg(dd);
2384 ret = 1; /* no other IB status change processing */
2385 } else if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)
2386 && dd->ipath_link_speed_active == IPATH_IB_SDR) {
2387 ipath_autoneg_send(dd, 1);
2388 set_speed_fast(dd, IPATH_IB_DDR);
2389 udelay(2);
2390 ipath_toggle_rclkrls(dd);
2391 ret = 1; /* no other IB status change processing */
2392 } else {
2393 if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) &&
2394 (dd->ipath_link_speed_active & IPATH_IB_DDR)) {
2395 ipath_dbg("Got to INIT with DDR autoneg\n");
2396 dd->ipath_flags &= ~(IPATH_IB_AUTONEG_INPROG
2397 | IPATH_IB_AUTONEG_FAILED);
2398 dd->ipath_autoneg_tries = 0;
2399 /* re-enable SDR, for next link down */
2400 set_speed_fast(dd,
2401 dd->ipath_link_speed_enabled);
2402 wake_up(&dd->ipath_autoneg_wait);
2403 } else if (dd->ipath_flags & IPATH_IB_AUTONEG_FAILED) {
2404 /*
2405 * clear autoneg failure flag, and do setup
2406 * so we'll try next time link goes down and
2407 * back to INIT (possibly connected to different
2408 * device).
2409 */
2410 ipath_dbg("INIT %sDR after autoneg failure\n",
2411 (dd->ipath_link_speed_active &
2412 IPATH_IB_DDR) ? "D" : "S");
2413 dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2414 dd->ipath_ibcddrctrl |=
2415 IBA7220_IBC_IBTA_1_2_MASK;
2416 ipath_write_kreg(dd,
2417 IPATH_KREG_OFFSET(IBNCModeCtrl), 0);
2418 }
2419 }
2420 /*
2421 * if we are in 1X, and are in autoneg width, it
2422 * could be due to an xgxs problem, so if we haven't
2423 * already tried, try twice to get to 4X; if we
2424 * tried, and couldn't, report it, since it will
2425 * probably not be what is desired.
2426 */
2427 if ((dd->ipath_link_width_enabled & (IB_WIDTH_1X |
2428 IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X)
2429 && dd->ipath_link_width_active == IB_WIDTH_1X
2430 && dd->ipath_x1_fix_tries < 3) {
2431 if (++dd->ipath_x1_fix_tries == 3)
2432 dev_info(&dd->pcidev->dev,
2433 "IB link is in 1X mode\n");
2434 else {
2435 ipath_cdbg(VERBOSE, "IB 1X in "
2436 "auto-width, try %u to be "
2437 "sure it's really 1X; "
2438 "ltstate %u\n",
2439 dd->ipath_x1_fix_tries,
2440 ltstate);
2441 dd->ipath_f_xgxs_reset(dd);
2442 ret = 1; /* skip other processing */
2443 }
2444 }
2445
2446 if (!ret) {
2447 dd->delay_mult = rate_to_delay
2448 [(ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1]
2449 [(ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1];
2450
2451 ipath_set_relock_poll(dd, ibup);
2452 }
2453 }
2454
2455 if (!ret)
2456 ipath_setup_7220_setextled(dd, ipath_ib_linkstate(dd, ibcs),
2457 ltstate);
2458 return ret;
2459}
2460
2461
2462/*
2463 * Handle the empirically determined mechanism for auto-negotiation
2464 * of DDR speed with switches.
2465 */
2466static void autoneg_work(struct work_struct *work)
2467{
2468 struct ipath_devdata *dd;
2469 u64 startms;
2470 u32 lastlts, i;
2471
2472 dd = container_of(work, struct ipath_devdata,
2473 ipath_autoneg_work.work);
2474
2475 startms = jiffies_to_msecs(jiffies);
2476
2477 /*
2478 * busy wait for this first part, it should be at most a
2479 * few hundred usec, since we scheduled ourselves for 2msec.
2480 */
2481 for (i = 0; i < 25; i++) {
2482 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
2483 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
2484 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN_DISABLE);
2485 break;
2486 }
2487 udelay(100);
2488 }
2489
2490 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG))
2491 goto done; /* we got there early or told to stop */
2492
2493 /* we expect this to timeout */
2494 if (wait_event_timeout(dd->ipath_autoneg_wait,
2495 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2496 msecs_to_jiffies(90)))
2497 goto done;
2498
2499 ipath_toggle_rclkrls(dd);
2500
2501 /* we expect this to timeout */
2502 if (wait_event_timeout(dd->ipath_autoneg_wait,
2503 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2504 msecs_to_jiffies(1700)))
2505 goto done;
2506
2507 set_speed_fast(dd, IPATH_IB_SDR);
2508 ipath_toggle_rclkrls(dd);
2509
2510 /*
2511 * wait up to 250 msec for link to train and get to INIT at DDR;
2512 * this should terminate early
2513 */
2514 wait_event_timeout(dd->ipath_autoneg_wait,
2515 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2516 msecs_to_jiffies(250));
2517done:
2518 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
2519 ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n",
2520 ipath_ib_state(dd, dd->ipath_lastibcstat),
2521 jiffies_to_msecs(jiffies)-startms);
2522 dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
2523 if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) {
2524 dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED;
2525 ipath_dbg("Giving up on DDR until next IB "
2526 "link Down\n");
2527 dd->ipath_autoneg_tries = 0;
2528 }
2529 set_speed_fast(dd, dd->ipath_link_speed_enabled);
2530 }
2531}
2532
2533
2534/**
2535 * ipath_init_iba7220_funcs - set up the chip-specific function pointers
2536 * @dd: the infinipath device
2537 *
2538 * This is global, and is called directly at init to set up the
2539 * chip-specific function pointers for later use.
2540 */
2541void ipath_init_iba7220_funcs(struct ipath_devdata *dd)
2542{
2543 dd->ipath_f_intrsetup = ipath_7220_intconfig;
2544 dd->ipath_f_bus = ipath_setup_7220_config;
2545 dd->ipath_f_reset = ipath_setup_7220_reset;
2546 dd->ipath_f_get_boardname = ipath_7220_boardname;
2547 dd->ipath_f_init_hwerrors = ipath_7220_init_hwerrors;
2548 dd->ipath_f_early_init = ipath_7220_early_init;
2549 dd->ipath_f_handle_hwerrors = ipath_7220_handle_hwerrors;
2550 dd->ipath_f_quiet_serdes = ipath_7220_quiet_serdes;
2551 dd->ipath_f_bringup_serdes = ipath_7220_bringup_serdes;
2552 dd->ipath_f_clear_tids = ipath_7220_clear_tids;
2553 dd->ipath_f_put_tid = ipath_7220_put_tid;
2554 dd->ipath_f_cleanup = ipath_setup_7220_cleanup;
2555 dd->ipath_f_setextled = ipath_setup_7220_setextled;
2556 dd->ipath_f_get_base_info = ipath_7220_get_base_info;
2557 dd->ipath_f_free_irq = ipath_7220_free_irq;
2558 dd->ipath_f_tidtemplate = ipath_7220_tidtemplate;
2559 dd->ipath_f_intr_fallback = ipath_7220_intr_fallback;
2560 dd->ipath_f_xgxs_reset = ipath_7220_xgxs_reset;
2561 dd->ipath_f_get_ib_cfg = ipath_7220_get_ib_cfg;
2562 dd->ipath_f_set_ib_cfg = ipath_7220_set_ib_cfg;
2563 dd->ipath_f_config_jint = ipath_7220_config_jint;
2564 dd->ipath_f_config_ports = ipath_7220_config_ports;
2565 dd->ipath_f_read_counters = ipath_7220_read_counters;
2566 dd->ipath_f_get_msgheader = ipath_7220_get_msgheader;
2567 dd->ipath_f_ib_updown = ipath_7220_ib_updown;
2568
2569 /* initialize chip-specific variables */
2570 ipath_init_7220_variables(dd);
2571}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 14:23:05 -0500