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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 12:12:14 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 12:12:14 -0400
commitfac56c2df51bc29b07b3c2dcfabf32a015a0522c (patch)
tree1ff5d84ecf4ea0bcbd42e2ef9624b5ade3810890 /drivers/infiniband/hw/qib/qib_iba6120.c
parent6caa15d0b84d2ea688fd31f4f172c8353463e109 (diff)
parenta6360dd37e1a144ed11e6548371bade559a1e4df (diff)
Merge commit 'v2.6.39-rc3' into for-2.6.39
Diffstat (limited to 'drivers/infiniband/hw/qib/qib_iba6120.c')
-rw-r--r--drivers/infiniband/hw/qib/qib_iba6120.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/infiniband/hw/qib/qib_iba6120.c b/drivers/infiniband/hw/qib/qib_iba6120.c
index 774dea897e9c..7de4b7ebffc5 100644
--- a/drivers/infiniband/hw/qib/qib_iba6120.c
+++ b/drivers/infiniband/hw/qib/qib_iba6120.c
@@ -1799,7 +1799,7 @@ static int qib_6120_setup_reset(struct qib_devdata *dd)
1799 /* 1799 /*
1800 * Keep chip from being accessed until we are ready. Use 1800 * Keep chip from being accessed until we are ready. Use
1801 * writeq() directly, to allow the write even though QIB_PRESENT 1801 * writeq() directly, to allow the write even though QIB_PRESENT
1802 * isnt' set. 1802 * isn't' set.
1803 */ 1803 */
1804 dd->flags &= ~(QIB_INITTED | QIB_PRESENT); 1804 dd->flags &= ~(QIB_INITTED | QIB_PRESENT);
1805 dd->int_counter = 0; /* so we check interrupts work again */ 1805 dd->int_counter = 0; /* so we check interrupts work again */
@@ -2171,7 +2171,7 @@ static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op,
2171 * Init the context registers also; if we were 2171 * Init the context registers also; if we were
2172 * disabled, tail and head should both be zero 2172 * disabled, tail and head should both be zero
2173 * already from the enable, but since we don't 2173 * already from the enable, but since we don't
2174 * know, we have to do it explictly. 2174 * know, we have to do it explicitly.
2175 */ 2175 */
2176 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); 2176 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
2177 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); 2177 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);