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authorRoland Dreier <roland@eddore.topspincom.com>2005-08-19 13:33:35 -0400
committerRoland Dreier <rolandd@cisco.com>2005-08-26 23:37:37 -0400
commitc04bc3d1f417a8a90eef9ab46523dfd44858b28d (patch)
tree5ac9dac7c37fc0b644814f8563fa3dad3c73e789 /drivers/infiniband/hw/mthca/mthca_qp.c
parent288bdeb4bc5b89befd7ee2f0f0183604034ff6c5 (diff)
[PATCH] IB/mthca: Move WQE structures into their own header
Move the definitions of the WQE structures from mthca_qp.c into mthca_wqe.h, so that we'll be able to share them when we add the SRQ code in mthca_srq.c. Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_qp.c')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_qp.c75
1 files changed, 1 insertions, 74 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c
index 43af076acd5f..ebb8f4a3dd80 100644
--- a/drivers/infiniband/hw/mthca/mthca_qp.c
+++ b/drivers/infiniband/hw/mthca/mthca_qp.c
@@ -44,6 +44,7 @@
44#include "mthca_dev.h" 44#include "mthca_dev.h"
45#include "mthca_cmd.h" 45#include "mthca_cmd.h"
46#include "mthca_memfree.h" 46#include "mthca_memfree.h"
47#include "mthca_wqe.h"
47 48
48enum { 49enum {
49 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE, 50 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
@@ -175,80 +176,6 @@ enum {
175 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16 176 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
176}; 177};
177 178
178enum {
179 MTHCA_NEXT_DBD = 1 << 7,
180 MTHCA_NEXT_FENCE = 1 << 6,
181 MTHCA_NEXT_CQ_UPDATE = 1 << 3,
182 MTHCA_NEXT_EVENT_GEN = 1 << 2,
183 MTHCA_NEXT_SOLICIT = 1 << 1,
184
185 MTHCA_MLX_VL15 = 1 << 17,
186 MTHCA_MLX_SLR = 1 << 16
187};
188
189enum {
190 MTHCA_INVAL_LKEY = 0x100
191};
192
193struct mthca_next_seg {
194 __be32 nda_op; /* [31:6] next WQE [4:0] next opcode */
195 __be32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */
196 __be32 flags; /* [3] CQ [2] Event [1] Solicit */
197 __be32 imm; /* immediate data */
198};
199
200struct mthca_tavor_ud_seg {
201 u32 reserved1;
202 __be32 lkey;
203 __be64 av_addr;
204 u32 reserved2[4];
205 __be32 dqpn;
206 __be32 qkey;
207 u32 reserved3[2];
208};
209
210struct mthca_arbel_ud_seg {
211 __be32 av[8];
212 __be32 dqpn;
213 __be32 qkey;
214 u32 reserved[2];
215};
216
217struct mthca_bind_seg {
218 __be32 flags; /* [31] Atomic [30] rem write [29] rem read */
219 u32 reserved;
220 __be32 new_rkey;
221 __be32 lkey;
222 __be64 addr;
223 __be64 length;
224};
225
226struct mthca_raddr_seg {
227 __be64 raddr;
228 __be32 rkey;
229 u32 reserved;
230};
231
232struct mthca_atomic_seg {
233 __be64 swap_add;
234 __be64 compare;
235};
236
237struct mthca_data_seg {
238 __be32 byte_count;
239 __be32 lkey;
240 __be64 addr;
241};
242
243struct mthca_mlx_seg {
244 __be32 nda_op;
245 __be32 nds;
246 __be32 flags; /* [17] VL15 [16] SLR [14:12] static rate
247 [11:8] SL [3] C [2] E */
248 __be16 rlid;
249 __be16 vcrc;
250};
251
252static const u8 mthca_opcode[] = { 179static const u8 mthca_opcode[] = {
253 [IB_WR_SEND] = MTHCA_OPCODE_SEND, 180 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
254 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM, 181 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,