diff options
author | Roland Dreier <rolandd@cisco.com> | 2005-10-06 16:15:56 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2005-10-17 18:20:28 -0400 |
commit | 90f104da22bbf2e2b8a2136c12fb4e013fccf504 (patch) | |
tree | d720f4b226cd72903ee878096707578ccc7abc0c /drivers/infiniband/hw/mthca/mthca_eq.c | |
parent | 116c0074ecfd6f061570856bec52b691d54dbd3c (diff) |
[IB] mthca: SRQ limit reached events
Our hardware supports generating an event when the number of receives
posted to a shared receive queue (SRQ) falls below a user-specified
limit. Implement mthca_modify_srq() to arm the limit, and add code to
handle dispatching SRQ events when they occur.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_eq.c')
-rw-r--r-- | drivers/infiniband/hw/mthca/mthca_eq.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_eq.c b/drivers/infiniband/hw/mthca/mthca_eq.c index c81fa8e975ef..f2afdc6c7e60 100644 --- a/drivers/infiniband/hw/mthca/mthca_eq.c +++ b/drivers/infiniband/hw/mthca/mthca_eq.c | |||
@@ -83,7 +83,8 @@ enum { | |||
83 | MTHCA_EVENT_TYPE_PATH_MIG = 0x01, | 83 | MTHCA_EVENT_TYPE_PATH_MIG = 0x01, |
84 | MTHCA_EVENT_TYPE_COMM_EST = 0x02, | 84 | MTHCA_EVENT_TYPE_COMM_EST = 0x02, |
85 | MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03, | 85 | MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03, |
86 | MTHCA_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | 86 | MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, |
87 | MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14, | ||
87 | MTHCA_EVENT_TYPE_CQ_ERROR = 0x04, | 88 | MTHCA_EVENT_TYPE_CQ_ERROR = 0x04, |
88 | MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | 89 | MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, |
89 | MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | 90 | MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, |
@@ -110,8 +111,9 @@ enum { | |||
110 | (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \ | 111 | (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \ |
111 | (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \ | 112 | (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \ |
112 | (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT)) | 113 | (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT)) |
113 | #define MTHCA_SRQ_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \ | 114 | #define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \ |
114 | (1ULL << MTHCA_EVENT_TYPE_SRQ_LAST_WQE) | 115 | (1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ |
116 | (1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT)) | ||
115 | #define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD) | 117 | #define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD) |
116 | 118 | ||
117 | #define MTHCA_EQ_DB_INC_CI (1 << 24) | 119 | #define MTHCA_EQ_DB_INC_CI (1 << 24) |
@@ -142,6 +144,9 @@ struct mthca_eqe { | |||
142 | __be32 qpn; | 144 | __be32 qpn; |
143 | } __attribute__((packed)) qp; | 145 | } __attribute__((packed)) qp; |
144 | struct { | 146 | struct { |
147 | __be32 srqn; | ||
148 | } __attribute__((packed)) srq; | ||
149 | struct { | ||
145 | __be32 cqn; | 150 | __be32 cqn; |
146 | u32 reserved1; | 151 | u32 reserved1; |
147 | u8 reserved2[3]; | 152 | u8 reserved2[3]; |
@@ -305,6 +310,16 @@ static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq) | |||
305 | IB_EVENT_SQ_DRAINED); | 310 | IB_EVENT_SQ_DRAINED); |
306 | break; | 311 | break; |
307 | 312 | ||
313 | case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE: | ||
314 | mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, | ||
315 | IB_EVENT_QP_LAST_WQE_REACHED); | ||
316 | break; | ||
317 | |||
318 | case MTHCA_EVENT_TYPE_SRQ_LIMIT: | ||
319 | mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff, | ||
320 | IB_EVENT_SRQ_LIMIT_REACHED); | ||
321 | break; | ||
322 | |||
308 | case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR: | 323 | case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR: |
309 | mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, | 324 | mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, |
310 | IB_EVENT_QP_FATAL); | 325 | IB_EVENT_QP_FATAL); |