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authorEli Cohen <eli@dev.mellanox.co.il>2008-04-17 00:01:11 -0400
committerRoland Dreier <rolandd@cisco.com>2008-04-17 00:01:11 -0400
commit680b575f6d1ae8aa39c4d7ee7e40b749d277fa9f (patch)
tree202da857b6205b699bd189b63e483387f1c58d94 /drivers/infiniband/hw/mthca/mthca_cq.c
parent8ff095ec4bce7be943beff3b330562e2f0e42167 (diff)
IB/mthca: Add IPoIB checksum offload support
Arbel and Sinai devices support checksum generation and verification of TCP and UDP packets for UD IPoIB messages. This patch checks if the HCA supports this and sets the IB_DEVICE_UD_IP_CSUM capability flag if it does. It implements support for handling the IB_SEND_IP_CSUM send flag and setting the csum_ok field in receive work completions. Signed-off-by: Eli Cohen <eli@mellnaox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_cq.c')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_cq.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_cq.c b/drivers/infiniband/hw/mthca/mthca_cq.c
index 1e1e336d3ef9..20401d2ba6b2 100644
--- a/drivers/infiniband/hw/mthca/mthca_cq.c
+++ b/drivers/infiniband/hw/mthca/mthca_cq.c
@@ -119,7 +119,8 @@ struct mthca_cqe {
119 __be32 my_qpn; 119 __be32 my_qpn;
120 __be32 my_ee; 120 __be32 my_ee;
121 __be32 rqpn; 121 __be32 rqpn;
122 __be16 sl_g_mlpath; 122 u8 sl_ipok;
123 u8 g_mlpath;
123 __be16 rlid; 124 __be16 rlid;
124 __be32 imm_etype_pkey_eec; 125 __be32 imm_etype_pkey_eec;
125 __be32 byte_cnt; 126 __be32 byte_cnt;
@@ -493,6 +494,7 @@ static inline int mthca_poll_one(struct mthca_dev *dev,
493 int is_send; 494 int is_send;
494 int free_cqe = 1; 495 int free_cqe = 1;
495 int err = 0; 496 int err = 0;
497 u16 checksum;
496 498
497 cqe = next_cqe_sw(cq); 499 cqe = next_cqe_sw(cq);
498 if (!cqe) 500 if (!cqe)
@@ -635,12 +637,14 @@ static inline int mthca_poll_one(struct mthca_dev *dev,
635 break; 637 break;
636 } 638 }
637 entry->slid = be16_to_cpu(cqe->rlid); 639 entry->slid = be16_to_cpu(cqe->rlid);
638 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12; 640 entry->sl = cqe->sl_ipok >> 4;
639 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff; 641 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
640 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f; 642 entry->dlid_path_bits = cqe->g_mlpath & 0x7f;
641 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16; 643 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
642 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ? 644 entry->wc_flags |= cqe->g_mlpath & 0x80 ? IB_WC_GRH : 0;
643 IB_WC_GRH : 0; 645 checksum = (be32_to_cpu(cqe->rqpn) >> 24) |
646 ((be32_to_cpu(cqe->my_ee) >> 16) & 0xff00);
647 entry->csum_ok = (cqe->sl_ipok & 1 && checksum == 0xffff);
644 } 648 }
645 649
646 entry->status = IB_WC_SUCCESS; 650 entry->status = IB_WC_SUCCESS;