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authorRoland Dreier <rolandd@cisco.com>2006-02-13 19:30:18 -0500
committerRoland Dreier <rolandd@cisco.com>2006-03-20 13:08:13 -0500
commitd844183d9c7b103da1d7a1c753a1c171e9ce26b3 (patch)
tree5bd7ca0feaae115b2f487e20fcd0fa75f76a16d9 /drivers/infiniband/hw/mthca/mthca_cmd.c
parent8a51866f08103ba04894ce0f65eef567ddc3ed40 (diff)
IB/mthca: Convert to use ib_modify_qp_is_ok()
Use ib_modify_qp_is_ok() in mthca, and delete the big table of attributes for queue pair state transitions. Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_cmd.c')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_cmd.c98
1 files changed, 60 insertions, 38 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_cmd.c b/drivers/infiniband/hw/mthca/mthca_cmd.c
index 9e7baa8b57a9..acd00831ef08 100644
--- a/drivers/infiniband/hw/mthca/mthca_cmd.c
+++ b/drivers/infiniband/hw/mthca/mthca_cmd.c
@@ -1566,31 +1566,56 @@ int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
1566 CMD_TIME_CLASS_B, status); 1566 CMD_TIME_CLASS_B, status);
1567} 1567}
1568 1568
1569int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num, 1569int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1570 int is_ee, struct mthca_mailbox *mailbox, u32 optmask, 1570 enum ib_qp_state next, u32 num, int is_ee,
1571 struct mthca_mailbox *mailbox, u32 optmask,
1571 u8 *status) 1572 u8 *status)
1572{ 1573{
1573 static const u16 op[] = { 1574 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1574 [MTHCA_TRANS_RST2INIT] = CMD_RST2INIT_QPEE, 1575 [IB_QPS_RESET] = {
1575 [MTHCA_TRANS_INIT2INIT] = CMD_INIT2INIT_QPEE, 1576 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1576 [MTHCA_TRANS_INIT2RTR] = CMD_INIT2RTR_QPEE, 1577 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1577 [MTHCA_TRANS_RTR2RTS] = CMD_RTR2RTS_QPEE, 1578 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1578 [MTHCA_TRANS_RTS2RTS] = CMD_RTS2RTS_QPEE, 1579 },
1579 [MTHCA_TRANS_SQERR2RTS] = CMD_SQERR2RTS_QPEE, 1580 [IB_QPS_INIT] = {
1580 [MTHCA_TRANS_ANY2ERR] = CMD_2ERR_QPEE, 1581 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1581 [MTHCA_TRANS_RTS2SQD] = CMD_RTS2SQD_QPEE, 1582 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1582 [MTHCA_TRANS_SQD2SQD] = CMD_SQD2SQD_QPEE, 1583 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1583 [MTHCA_TRANS_SQD2RTS] = CMD_SQD2RTS_QPEE, 1584 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1584 [MTHCA_TRANS_ANY2RST] = CMD_ERR2RST_QPEE 1585 },
1586 [IB_QPS_RTR] = {
1587 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1588 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1589 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1590 },
1591 [IB_QPS_RTS] = {
1592 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1593 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1594 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1595 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1596 },
1597 [IB_QPS_SQD] = {
1598 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1599 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1600 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1601 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1602 },
1603 [IB_QPS_SQE] = {
1604 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1605 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1606 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1607 },
1608 [IB_QPS_ERR] = {
1609 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1610 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1611 }
1585 }; 1612 };
1613
1586 u8 op_mod = 0; 1614 u8 op_mod = 0;
1587 int my_mailbox = 0; 1615 int my_mailbox = 0;
1588 int err; 1616 int err;
1589 1617
1590 if (trans < 0 || trans >= ARRAY_SIZE(op)) 1618 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1591 return -EINVAL;
1592
1593 if (trans == MTHCA_TRANS_ANY2RST) {
1594 op_mod = 3; /* don't write outbox, any->reset */ 1619 op_mod = 3; /* don't write outbox, any->reset */
1595 1620
1596 /* For debugging */ 1621 /* For debugging */
@@ -1602,34 +1627,35 @@ int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1602 } else 1627 } else
1603 mailbox = NULL; 1628 mailbox = NULL;
1604 } 1629 }
1605 } else { 1630
1606 if (0) { 1631 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1632 (!!is_ee << 24) | num, op_mod,
1633 op[cur][next], CMD_TIME_CLASS_C, status);
1634
1635 if (0 && mailbox) {
1607 int i; 1636 int i;
1608 mthca_dbg(dev, "Dumping QP context:\n"); 1637 mthca_dbg(dev, "Dumping QP context:\n");
1609 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); 1638 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1610 for (i = 0; i < 0x100 / 4; ++i) { 1639 for (i = 0; i < 0x100 / 4; ++i) {
1611 if (i % 8 == 0) 1640 if (i % 8 == 0)
1612 printk(" [%02x] ", i * 4); 1641 printk("[%02x] ", i * 4);
1613 printk(" %08x", 1642 printk(" %08x",
1614 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1643 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1615 if ((i + 1) % 8 == 0) 1644 if ((i + 1) % 8 == 0)
1616 printk("\n"); 1645 printk("\n");
1617 } 1646 }
1618 } 1647 }
1619 }
1620 1648
1621 if (trans == MTHCA_TRANS_ANY2RST) { 1649 if (my_mailbox)
1622 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, 1650 mthca_free_mailbox(dev, mailbox);
1623 (!!is_ee << 24) | num, op_mod, 1651 } else {
1624 op[trans], CMD_TIME_CLASS_C, status); 1652 if (0) {
1625
1626 if (0 && mailbox) {
1627 int i; 1653 int i;
1628 mthca_dbg(dev, "Dumping QP context:\n"); 1654 mthca_dbg(dev, "Dumping QP context:\n");
1629 printk(" %08x\n", be32_to_cpup(mailbox->buf)); 1655 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1630 for (i = 0; i < 0x100 / 4; ++i) { 1656 for (i = 0; i < 0x100 / 4; ++i) {
1631 if (i % 8 == 0) 1657 if (i % 8 == 0)
1632 printk("[%02x] ", i * 4); 1658 printk(" [%02x] ", i * 4);
1633 printk(" %08x", 1659 printk(" %08x",
1634 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1660 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1635 if ((i + 1) % 8 == 0) 1661 if ((i + 1) % 8 == 0)
@@ -1637,13 +1663,9 @@ int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
1637 } 1663 }
1638 } 1664 }
1639 1665
1640 } else 1666 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1641 err = mthca_cmd(dev, mailbox->dma, 1667 op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
1642 optmask | (!!is_ee << 24) | num, 1668 }
1643 op_mod, op[trans], CMD_TIME_CLASS_C, status);
1644
1645 if (my_mailbox)
1646 mthca_free_mailbox(dev, mailbox);
1647 1669
1648 return err; 1670 return err;
1649} 1671}