aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/infiniband/hw/mlx5/qp.c
diff options
context:
space:
mode:
authorSagi Grimberg <sagig@mellanox.com>2014-08-13 12:54:32 -0400
committerRoland Dreier <roland@purestorage.com>2014-10-09 03:10:53 -0400
commit142537f4e5f7ffd3e34b0c46646ac9cb5d986d06 (patch)
treec85c8cf791d85ef3bac4390106869619c9b51832 /drivers/infiniband/hw/mlx5/qp.c
parentf043032ef1acd294e0360bec96c91b90dec7cc17 (diff)
IB/mlx5: Use extended internal signature layout
Rather than using the basic BSF layout which utilizes a pre-configured signature settings (sufficient for current DIF implementation), we use the extended BSF layout to expose advanced signature settings. These settings will also be exposed to the user later. Signed-off-by: Sagi Grimberg <sagig@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'drivers/infiniband/hw/mlx5/qp.c')
-rw-r--r--drivers/infiniband/hw/mlx5/qp.c80
1 files changed, 37 insertions, 43 deletions
diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index 554410c2655d..13924a256290 100644
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -2020,53 +2020,47 @@ static u8 bs_selector(int block_size)
2020 } 2020 }
2021} 2021}
2022 2022
2023static int format_selector(struct ib_sig_attrs *attr, 2023static int mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2024 struct ib_sig_domain *domain, 2024 struct mlx5_bsf_inl *inl)
2025 int *selector)
2026{ 2025{
2027 2026 /* Valid inline section and allow BSF refresh */
2028#define FORMAT_DIF_NONE 0 2027 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2029#define FORMAT_DIF_CRC_INC 8 2028 MLX5_BSF_REFRESH_DIF);
2030#define FORMAT_DIF_CRC_NO_INC 12 2029 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2031#define FORMAT_DIF_CSUM_INC 13 2030 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
2032#define FORMAT_DIF_CSUM_NO_INC 14
2033 2031
2034 switch (domain->sig.dif.type) { 2032 switch (domain->sig.dif.type) {
2035 case IB_T10DIF_NONE: 2033 case IB_T10DIF_NONE:
2036 /* No DIF */ 2034 /* No DIF */
2037 *selector = FORMAT_DIF_NONE;
2038 break; 2035 break;
2039 case IB_T10DIF_TYPE1: /* Fall through */ 2036 case IB_T10DIF_TYPE1: /* Fall through */
2040 case IB_T10DIF_TYPE2: 2037 case IB_T10DIF_TYPE2:
2041 switch (domain->sig.dif.bg_type) { 2038 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2042 case IB_T10DIF_CRC: 2039 MLX5_DIF_CRC : MLX5_DIF_IPCS;
2043 *selector = FORMAT_DIF_CRC_INC; 2040 /*
2044 break; 2041 * increment reftag and don't check if
2045 case IB_T10DIF_CSUM: 2042 * apptag=0xffff and reftag=0xffffffff
2046 *selector = FORMAT_DIF_CSUM_INC; 2043 */
2047 break; 2044 inl->dif_inc_ref_guard_check = MLX5_BSF_INC_REFTAG |
2048 default: 2045 MLX5_BSF_APPREF_ESCAPE;
2049 return 1; 2046 inl->dif_app_bitmask_check = 0xffff;
2050 } 2047 /* repeating block */
2048 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2051 break; 2049 break;
2052 case IB_T10DIF_TYPE3: 2050 case IB_T10DIF_TYPE3:
2053 switch (domain->sig.dif.bg_type) { 2051 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2054 case IB_T10DIF_CRC: 2052 MLX5_DIF_CRC : MLX5_DIF_IPCS;
2055 *selector = domain->sig.dif.type3_inc_reftag ? 2053 /*
2056 FORMAT_DIF_CRC_INC : 2054 * Don't inc reftag and don't check if
2057 FORMAT_DIF_CRC_NO_INC; 2055 * apptag=0xffff and reftag=0xffffffff
2058 break; 2056 */
2059 case IB_T10DIF_CSUM: 2057 inl->dif_inc_ref_guard_check = MLX5_BSF_APPREF_ESCAPE;
2060 *selector = domain->sig.dif.type3_inc_reftag ? 2058 inl->dif_app_bitmask_check = 0xffff;
2061 FORMAT_DIF_CSUM_INC : 2059 /* Repeating block */
2062 FORMAT_DIF_CSUM_NO_INC; 2060 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2063 break;
2064 default:
2065 return 1;
2066 }
2067 break; 2061 break;
2068 default: 2062 default:
2069 return 1; 2063 return -EINVAL;
2070 } 2064 }
2071 2065
2072 return 0; 2066 return 0;
@@ -2080,7 +2074,7 @@ static int mlx5_set_bsf(struct ib_mr *sig_mr,
2080 struct mlx5_bsf_basic *basic = &bsf->basic; 2074 struct mlx5_bsf_basic *basic = &bsf->basic;
2081 struct ib_sig_domain *mem = &sig_attrs->mem; 2075 struct ib_sig_domain *mem = &sig_attrs->mem;
2082 struct ib_sig_domain *wire = &sig_attrs->wire; 2076 struct ib_sig_domain *wire = &sig_attrs->wire;
2083 int ret, selector; 2077 int ret;
2084 2078
2085 memset(bsf, 0, sizeof(*bsf)); 2079 memset(bsf, 0, sizeof(*bsf));
2086 switch (sig_attrs->mem.sig_type) { 2080 switch (sig_attrs->mem.sig_type) {
@@ -2088,12 +2082,14 @@ static int mlx5_set_bsf(struct ib_mr *sig_mr,
2088 if (sig_attrs->wire.sig_type != IB_SIG_TYPE_T10_DIF) 2082 if (sig_attrs->wire.sig_type != IB_SIG_TYPE_T10_DIF)
2089 return -EINVAL; 2083 return -EINVAL;
2090 2084
2085 /* Basic + Extended + Inline */
2086 basic->bsf_size_sbs = 1 << 7;
2091 /* Input domain check byte mask */ 2087 /* Input domain check byte mask */
2092 basic->check_byte_mask = sig_attrs->check_mask; 2088 basic->check_byte_mask = sig_attrs->check_mask;
2093 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 2089 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2094 mem->sig.dif.type == wire->sig.dif.type) { 2090 mem->sig.dif.type == wire->sig.dif.type) {
2095 /* Same block structure */ 2091 /* Same block structure */
2096 basic->bsf_size_sbs = 1 << 4; 2092 basic->bsf_size_sbs |= 1 << 4;
2097 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 2093 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2098 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 2094 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
2099 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 2095 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
@@ -2105,18 +2101,16 @@ static int mlx5_set_bsf(struct ib_mr *sig_mr,
2105 2101
2106 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 2102 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2107 basic->raw_data_size = cpu_to_be32(data_size); 2103 basic->raw_data_size = cpu_to_be32(data_size);
2104 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2105 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
2108 2106
2109 ret = format_selector(sig_attrs, mem, &selector); 2107 ret = mlx5_fill_inl_bsf(wire, &bsf->w_inl);
2110 if (ret) 2108 if (ret)
2111 return -EINVAL; 2109 return -EINVAL;
2112 basic->m_bfs_psv = cpu_to_be32(selector << 24 |
2113 msig->psv_memory.psv_idx);
2114 2110
2115 ret = format_selector(sig_attrs, wire, &selector); 2111 ret = mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2116 if (ret) 2112 if (ret)
2117 return -EINVAL; 2113 return -EINVAL;
2118 basic->w_bfs_psv = cpu_to_be32(selector << 24 |
2119 msig->psv_wire.psv_idx);
2120 break; 2114 break;
2121 2115
2122 default: 2116 default: