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authorBryan O'Sullivan <bos@pathscale.com>2006-07-01 07:36:05 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-01 12:56:00 -0400
commit57abad25f844e760082c0b1ab2b176dad682ea16 (patch)
tree5a61c70ed4ae1ad7ccb8c246c22480d8bb045f46 /drivers/infiniband/hw/ipath/ipath_intr.c
parentf5f99929ac584126ef3f47d805dc619abc54768c (diff)
[PATCH] IB/ipath: fix lost interrupts on HT-400
Do an extra check to see if in-memory tail changed while processing packets, and if so, going back through the loop again (but only once per call to ipath_kreceive()). In practice, this seems to be enough to guarantee that if we crossed the clearing of an interrupt at start of ipath_intr with a scheduled tail register update, that we'll process the "extra" packet that lost the interrupt because we cleared it just as it was about to arrive. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Bryan O'Sullivan <bryan.osullivan@qlogic.com> Cc: "Michael S. Tsirkin" <mst@mellanox.co.il> Cc: Roland Dreier <rolandd@cisco.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/infiniband/hw/ipath/ipath_intr.c')
-rw-r--r--drivers/infiniband/hw/ipath/ipath_intr.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_intr.c b/drivers/infiniband/hw/ipath/ipath_intr.c
index bad20a395265..83b51ed89527 100644
--- a/drivers/infiniband/hw/ipath/ipath_intr.c
+++ b/drivers/infiniband/hw/ipath/ipath_intr.c
@@ -766,7 +766,7 @@ irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
766 u32 istat, chk0rcv = 0; 766 u32 istat, chk0rcv = 0;
767 ipath_err_t estat = 0; 767 ipath_err_t estat = 0;
768 irqreturn_t ret; 768 irqreturn_t ret;
769 u32 p0bits, oldhead; 769 u32 oldhead, curtail;
770 static unsigned unexpected = 0; 770 static unsigned unexpected = 0;
771 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) | 771 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
772 (1U<<INFINIPATH_I_RCVURG_SHIFT); 772 (1U<<INFINIPATH_I_RCVURG_SHIFT);
@@ -809,15 +809,16 @@ irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
809 * lose intr for later packets that arrive while we are processing. 809 * lose intr for later packets that arrive while we are processing.
810 */ 810 */
811 oldhead = dd->ipath_port0head; 811 oldhead = dd->ipath_port0head;
812 if (oldhead != (u32) le64_to_cpu(*dd->ipath_hdrqtailptr)) { 812 curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
813 if (oldhead != curtail) {
813 if (dd->ipath_flags & IPATH_GPIO_INTR) { 814 if (dd->ipath_flags & IPATH_GPIO_INTR) {
814 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 815 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
815 (u64) (1 << 2)); 816 (u64) (1 << 2));
816 p0bits = port0rbits | INFINIPATH_I_GPIO; 817 istat = port0rbits | INFINIPATH_I_GPIO;
817 } 818 }
818 else 819 else
819 p0bits = port0rbits; 820 istat = port0rbits;
820 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, p0bits); 821 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
821 ipath_kreceive(dd); 822 ipath_kreceive(dd);
822 if (oldhead != dd->ipath_port0head) { 823 if (oldhead != dd->ipath_port0head) {
823 ipath_stats.sps_fastrcvint++; 824 ipath_stats.sps_fastrcvint++;
@@ -827,7 +828,6 @@ irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
827 } 828 }
828 829
829 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus); 830 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
830 p0bits = port0rbits;
831 831
832 if (unlikely(!istat)) { 832 if (unlikely(!istat)) {
833 ipath_stats.sps_nullintr++; 833 ipath_stats.sps_nullintr++;
@@ -890,19 +890,19 @@ irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
890 else { 890 else {
891 /* Clear GPIO status bit 2 */ 891 /* Clear GPIO status bit 2 */
892 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, 892 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
893 (u64) (1 << 2)); 893 (u64) (1 << 2));
894 p0bits |= INFINIPATH_I_GPIO;
895 chk0rcv = 1; 894 chk0rcv = 1;
896 } 895 }
897 } 896 }
898 chk0rcv |= istat & p0bits; 897 chk0rcv |= istat & port0rbits;
899 898
900 /* 899 /*
901 * clear the ones we will deal with on this round 900 * Clear the interrupt bits we found set, unless they are receive
902 * We clear it early, mostly for receive interrupts, so we 901 * related, in which case we already cleared them above, and don't
903 * know the chip will have seen this by the time we process 902 * want to clear them again, because we might lose an interrupt.
904 * the queue, and will re-interrupt if necessary. The processor 903 * Clear it early, so we "know" know the chip will have seen this by
905 * itself won't take the interrupt again until we return. 904 * the time we process the queue, and will re-interrupt if necessary.
905 * The processor itself won't take the interrupt again until we return.
906 */ 906 */
907 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); 907 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
908 908