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authorBryan O'Sullivan <bos@pathscale.com>2006-09-28 12:00:08 -0400
committerRoland Dreier <rolandd@cisco.com>2006-09-28 14:16:43 -0400
commit8d588f8bb79c86a5826f66946c1ea026b6b07bd8 (patch)
tree472dfec24f59ac565cd97e67dd62f8df4fa93d24 /drivers/infiniband/hw/ipath/ipath_iba6120.c
parent6a553af286653818bb5831f1b351eefdc8a93b61 (diff)
IB/ipath: Print more informative parity error messages
Signed-off-by: Bryan O'Sullivan <bryan.osullivan@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ipath/ipath_iba6120.c')
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba6120.c77
1 files changed, 27 insertions, 50 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6120.c b/drivers/infiniband/hw/ipath/ipath_iba6120.c
index d64b87bf1f97..a4ec50b0fe87 100644
--- a/drivers/infiniband/hw/ipath/ipath_iba6120.c
+++ b/drivers/infiniband/hw/ipath/ipath_iba6120.c
@@ -301,6 +301,26 @@ static const struct ipath_cregs ipath_pe_cregs = {
301 */ 301 */
302#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63) 302#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
303 303
304/* 6120 specific hardware errors... */
305static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
306 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
307 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
308 /*
309 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
310 * parity or memory parity error failures, because most likely we
311 * won't be able to talk to the core of the chip. Nonetheless, we
312 * might see them, if they are in parts of the PCIe core that aren't
313 * essential.
314 */
315 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
316 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
317 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
318 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
319 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
320 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
321 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
322};
323
304/** 324/**
305 * ipath_pe_handle_hwerrors - display hardware errors. 325 * ipath_pe_handle_hwerrors - display hardware errors.
306 * @dd: the infinipath device 326 * @dd: the infinipath device
@@ -403,24 +423,13 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
403 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 423 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
404 dd->ipath_hwerrmask); 424 dd->ipath_hwerrmask);
405 } 425 }
406 if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK 426
407 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) { 427 ipath_format_hwerrors(hwerrs,
408 bits = (u32) ((hwerrs >> 428 ipath_6120_hwerror_msgs,
409 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) & 429 sizeof(ipath_6120_hwerror_msgs)/
410 INFINIPATH_HWE_RXEMEMPARITYERR_MASK); 430 sizeof(ipath_6120_hwerror_msgs[0]),
411 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ", 431 msg, msgl);
412 bits); 432
413 strlcat(msg, bitsmsg, msgl);
414 }
415 if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
416 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
417 bits = (u32) ((hwerrs >>
418 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
419 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
420 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
421 bits);
422 strlcat(msg, bitsmsg, msgl);
423 }
424 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 433 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
425 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) { 434 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
426 bits = (u32) ((hwerrs >> 435 bits = (u32) ((hwerrs >>
@@ -430,10 +439,6 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
430 "[PCIe Mem Parity Errs %x] ", bits); 439 "[PCIe Mem Parity Errs %x] ", bits);
431 strlcat(msg, bitsmsg, msgl); 440 strlcat(msg, bitsmsg, msgl);
432 } 441 }
433 if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
434 strlcat(msg, "[IB2IPATH Parity]", msgl);
435 if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
436 strlcat(msg, "[IPATH2IB Parity]", msgl);
437 442
438#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \ 443#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
439 INFINIPATH_HWE_COREPLL_RFSLIP ) 444 INFINIPATH_HWE_COREPLL_RFSLIP )
@@ -459,34 +464,6 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
459 dd->ipath_hwerrmask); 464 dd->ipath_hwerrmask);
460 } 465 }
461 466
462 if (hwerrs & INFINIPATH_HWE_PCIEPOISONEDTLP)
463 strlcat(msg, "[PCIe Poisoned TLP]", msgl);
464 if (hwerrs & INFINIPATH_HWE_PCIECPLTIMEOUT)
465 strlcat(msg, "[PCIe completion timeout]", msgl);
466
467 /*
468 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
469 * parity or memory parity error failures, because most likely we
470 * won't be able to talk to the core of the chip. Nonetheless, we
471 * might see them, if they are in parts of the PCIe core that aren't
472 * essential.
473 */
474 if (hwerrs & INFINIPATH_HWE_PCIE1PLLFAILED)
475 strlcat(msg, "[PCIePLL1]", msgl);
476 if (hwerrs & INFINIPATH_HWE_PCIE0PLLFAILED)
477 strlcat(msg, "[PCIePLL0]", msgl);
478 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXTLH)
479 strlcat(msg, "[PCIe XTLH core parity]", msgl);
480 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXADM)
481 strlcat(msg, "[PCIe ADM TX core parity]", msgl);
482 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYRADM)
483 strlcat(msg, "[PCIe ADM RX core parity]", msgl);
484
485 if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
486 strlcat(msg, "[Rx Dsync]", msgl);
487 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
488 strlcat(msg, "[SerDes PLL]", msgl);
489
490 ipath_dev_err(dd, "%s hardware error\n", msg); 467 ipath_dev_err(dd, "%s hardware error\n", msg);
491 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) { 468 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
492 /* 469 /*