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authorJoachim Fenkes <fenkes@de.ibm.com>2007-07-09 09:21:45 -0400
committerRoland Dreier <rolandd@cisco.com>2007-07-09 23:12:27 -0400
commit91f13aa3fc22e357b494c5b8270e94543870928d (patch)
treee8f78c2549945f5e3bc42e33ce81a18a9292f746 /drivers/infiniband/hw/ehca/ehca_main.c
parentb8a3ba551369982180917a999d32fcedbba34115 (diff)
IB/ehca: HW level, HW caps and MTU autodetection
In preparation for support of new eHCA2 features, change adapter probing: - Hardware level is changed to encode major and minor chip version - Hardware capabilities are queried from the firmware - The maximum MTU is queried from the firmware instead of assuming a fixed value Signed-off-by: Joachim Fenkes <fenkes@de.ibm.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/ehca/ehca_main.c')
-rw-r--r--drivers/infiniband/hw/ehca/ehca_main.c62
1 files changed, 56 insertions, 6 deletions
diff --git a/drivers/infiniband/hw/ehca/ehca_main.c b/drivers/infiniband/hw/ehca/ehca_main.c
index fea199f01eaa..eb22a6b296d9 100644
--- a/drivers/infiniband/hw/ehca/ehca_main.c
+++ b/drivers/infiniband/hw/ehca/ehca_main.c
@@ -205,11 +205,35 @@ static void ehca_destroy_slab_caches(void)
205#define EHCA_HCAAVER EHCA_BMASK_IBM(32,39) 205#define EHCA_HCAAVER EHCA_BMASK_IBM(32,39)
206#define EHCA_REVID EHCA_BMASK_IBM(40,63) 206#define EHCA_REVID EHCA_BMASK_IBM(40,63)
207 207
208static struct cap_descr {
209 u64 mask;
210 char *descr;
211} hca_cap_descr[] = {
212 { HCA_CAP_AH_PORT_NR_CHECK, "HCA_CAP_AH_PORT_NR_CHECK" },
213 { HCA_CAP_ATOMIC, "HCA_CAP_ATOMIC" },
214 { HCA_CAP_AUTO_PATH_MIG, "HCA_CAP_AUTO_PATH_MIG" },
215 { HCA_CAP_BAD_P_KEY_CTR, "HCA_CAP_BAD_P_KEY_CTR" },
216 { HCA_CAP_SQD_RTS_PORT_CHANGE, "HCA_CAP_SQD_RTS_PORT_CHANGE" },
217 { HCA_CAP_CUR_QP_STATE_MOD, "HCA_CAP_CUR_QP_STATE_MOD" },
218 { HCA_CAP_INIT_TYPE, "HCA_CAP_INIT_TYPE" },
219 { HCA_CAP_PORT_ACTIVE_EVENT, "HCA_CAP_PORT_ACTIVE_EVENT" },
220 { HCA_CAP_Q_KEY_VIOL_CTR, "HCA_CAP_Q_KEY_VIOL_CTR" },
221 { HCA_CAP_WQE_RESIZE, "HCA_CAP_WQE_RESIZE" },
222 { HCA_CAP_RAW_PACKET_MCAST, "HCA_CAP_RAW_PACKET_MCAST" },
223 { HCA_CAP_SHUTDOWN_PORT, "HCA_CAP_SHUTDOWN_PORT" },
224 { HCA_CAP_RC_LL_QP, "HCA_CAP_RC_LL_QP" },
225 { HCA_CAP_SRQ, "HCA_CAP_SRQ" },
226 { HCA_CAP_UD_LL_QP, "HCA_CAP_UD_LL_QP" },
227 { HCA_CAP_RESIZE_MR, "HCA_CAP_RESIZE_MR" },
228 { HCA_CAP_MINI_QP, "HCA_CAP_MINI_QP" },
229};
230
208int ehca_sense_attributes(struct ehca_shca *shca) 231int ehca_sense_attributes(struct ehca_shca *shca)
209{ 232{
210 int ret = 0; 233 int i, ret = 0;
211 u64 h_ret; 234 u64 h_ret;
212 struct hipz_query_hca *rblock; 235 struct hipz_query_hca *rblock;
236 struct hipz_query_port *port;
213 237
214 rblock = ehca_alloc_fw_ctrlblock(GFP_KERNEL); 238 rblock = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
215 if (!rblock) { 239 if (!rblock) {
@@ -222,7 +246,7 @@ int ehca_sense_attributes(struct ehca_shca *shca)
222 ehca_gen_err("Cannot query device properties. h_ret=%lx", 246 ehca_gen_err("Cannot query device properties. h_ret=%lx",
223 h_ret); 247 h_ret);
224 ret = -EPERM; 248 ret = -EPERM;
225 goto num_ports1; 249 goto sense_attributes1;
226 } 250 }
227 251
228 if (ehca_nr_ports == 1) 252 if (ehca_nr_ports == 1)
@@ -242,18 +266,44 @@ int ehca_sense_attributes(struct ehca_shca *shca)
242 ehca_gen_dbg(" ... hardware version=%x:%x", hcaaver, revid); 266 ehca_gen_dbg(" ... hardware version=%x:%x", hcaaver, revid);
243 267
244 if ((hcaaver == 1) && (revid == 0)) 268 if ((hcaaver == 1) && (revid == 0))
245 shca->hw_level = 0; 269 shca->hw_level = 0x11;
246 else if ((hcaaver == 1) && (revid == 1)) 270 else if ((hcaaver == 1) && (revid == 1))
247 shca->hw_level = 1; 271 shca->hw_level = 0x12;
248 else if ((hcaaver == 1) && (revid == 2)) 272 else if ((hcaaver == 1) && (revid == 2))
249 shca->hw_level = 2; 273 shca->hw_level = 0x13;
274 else if ((hcaaver == 2) && (revid == 0))
275 shca->hw_level = 0x21;
276 else if ((hcaaver == 2) && (revid == 0x10))
277 shca->hw_level = 0x22;
278 else {
279 ehca_gen_warn("unknown hardware version"
280 " - assuming default level");
281 shca->hw_level = 0x22;
282 }
250 } 283 }
251 ehca_gen_dbg(" ... hardware level=%x", shca->hw_level); 284 ehca_gen_dbg(" ... hardware level=%x", shca->hw_level);
252 285
253 shca->sport[0].rate = IB_RATE_30_GBPS; 286 shca->sport[0].rate = IB_RATE_30_GBPS;
254 shca->sport[1].rate = IB_RATE_30_GBPS; 287 shca->sport[1].rate = IB_RATE_30_GBPS;
255 288
256num_ports1: 289 shca->hca_cap = rblock->hca_cap_indicators;
290 ehca_gen_dbg(" ... HCA capabilities:");
291 for (i = 0; i < ARRAY_SIZE(hca_cap_descr); i++)
292 if (EHCA_BMASK_GET(hca_cap_descr[i].mask, shca->hca_cap))
293 ehca_gen_dbg(" %s", hca_cap_descr[i].descr);
294
295 port = (struct hipz_query_port *) rblock;
296 h_ret = hipz_h_query_port(shca->ipz_hca_handle, 1, port);
297 if (h_ret != H_SUCCESS) {
298 ehca_gen_err("Cannot query port properties. h_ret=%lx",
299 h_ret);
300 ret = -EPERM;
301 goto sense_attributes1;
302 }
303
304 shca->max_mtu = port->max_mtu;
305
306sense_attributes1:
257 ehca_free_fw_ctrlblock(rblock); 307 ehca_free_fw_ctrlblock(rblock);
258 return ret; 308 return ret;
259} 309}