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authorRoland Dreier <rolandd@cisco.com>2010-05-05 17:45:40 -0400
committerRoland Dreier <rolandd@cisco.com>2010-05-05 17:45:40 -0400
commitbe4c9bad9d0edb6bc3bd8fffc2f98e0e2112da39 (patch)
tree1fbe204cb8f386e35581bd9fa8ea835950b076c4 /drivers/infiniband/hw/cxgb4/t4.h
parentcfdda9d764362ab77b11a410bb928400e6520d57 (diff)
MAINTAINERS: Add cxgb4 and iw_cxgb4 entries
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4/t4.h')
-rw-r--r--drivers/infiniband/hw/cxgb4/t4.h32
1 files changed, 23 insertions, 9 deletions
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h
index 3f0d2172efda..d0e8af352408 100644
--- a/drivers/infiniband/hw/cxgb4/t4.h
+++ b/drivers/infiniband/hw/cxgb4/t4.h
@@ -36,7 +36,6 @@
36#include "t4_msg.h" 36#include "t4_msg.h"
37#include "t4fw_ri_api.h" 37#include "t4fw_ri_api.h"
38 38
39#define T4_MAX_READ_DEPTH 16
40#define T4_QID_BASE 1024 39#define T4_QID_BASE 1024
41#define T4_MAX_QIDS 256 40#define T4_MAX_QIDS 256
42#define T4_MAX_NUM_QP (1<<16) 41#define T4_MAX_NUM_QP (1<<16)
@@ -450,11 +449,25 @@ struct t4_cq {
450static inline int t4_arm_cq(struct t4_cq *cq, int se) 449static inline int t4_arm_cq(struct t4_cq *cq, int se)
451{ 450{
452 u32 val; 451 u32 val;
453 452 u16 inc;
454 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) | 453
455 INGRESSQID(cq->cqid); 454 do {
456 cq->cidx_inc = 0; 455 /*
457 writel(val, cq->gts); 456 * inc must be less the both the max update value -and-
457 * the size of the CQ.
458 */
459 inc = cq->cidx_inc <= CIDXINC_MASK ? cq->cidx_inc :
460 CIDXINC_MASK;
461 inc = inc <= (cq->size - 1) ? inc : (cq->size - 1);
462 if (inc == cq->cidx_inc)
463 val = SEINTARM(se) | CIDXINC(inc) | TIMERREG(6) |
464 INGRESSQID(cq->cqid);
465 else
466 val = SEINTARM(0) | CIDXINC(inc) | TIMERREG(7) |
467 INGRESSQID(cq->cqid);
468 cq->cidx_inc -= inc;
469 writel(val, cq->gts);
470 } while (cq->cidx_inc);
458 return 0; 471 return 0;
459} 472}
460 473
@@ -489,11 +502,12 @@ static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
489static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 502static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
490{ 503{
491 int ret = 0; 504 int ret = 0;
505 u64 bits_type_ts = be64_to_cpu(cq->queue[cq->cidx].bits_type_ts);
492 506
493 if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { 507 if (G_CQE_GENBIT(bits_type_ts) == cq->gen) {
494 *cqe = &cq->queue[cq->cidx]; 508 *cqe = &cq->queue[cq->cidx];
495 cq->timestamp = CQE_TS(*cqe); 509 cq->timestamp = G_CQE_TS(bits_type_ts);
496 } else if (CQE_TS(&cq->queue[cq->cidx]) > cq->timestamp) 510 } else if (G_CQE_TS(bits_type_ts) > cq->timestamp)
497 ret = -EOVERFLOW; 511 ret = -EOVERFLOW;
498 else 512 else
499 ret = -ENODATA; 513 ret = -ENODATA;