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authorSteve Wise <swise@opengridcomputing.com>2014-04-09 10:38:27 -0400
committerRoland Dreier <roland@purestorage.com>2014-04-11 14:36:08 -0400
commita03d9f94cc54199bf681729b16ba649d7206369e (patch)
treee2bebbff12cd98b99d2e8110cdd1a4b8af5afea9 /drivers/infiniband/hw/cxgb4/qp.c
parentb4e2901c52cc79f287e2b25804e029880e5e4b07 (diff)
RDMA/cxgb4: Max fastreg depth depends on DSGL support
The max depth of a fastreg mr depends on whether the device supports DSGL or not. So compute it dynamically based on the device support and the module use_dsgl option. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4/qp.c')
-rw-r--r--drivers/infiniband/hw/cxgb4/qp.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 9b4a8b88908e..2c037e1746d3 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -566,7 +566,8 @@ static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
566 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 566 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
567 int rem; 567 int rem;
568 568
569 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 569 if (wr->wr.fast_reg.page_list_len >
570 t4_max_fr_depth(use_dsgl))
570 return -EINVAL; 571 return -EINVAL;
571 572
572 wqe->fr.qpbinde_to_dcacpu = 0; 573 wqe->fr.qpbinde_to_dcacpu = 0;