diff options
author | Steve Wise <swise@opengridcomputing.com> | 2008-07-15 02:48:53 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2008-07-15 02:48:53 -0400 |
commit | 4ab928f69208d240d3681336f34589e4b151824f (patch) | |
tree | aca612ffbf703870cac63efb5ec5d8955ac2bc3c /drivers/infiniband/hw/cxgb3/cxio_wr.h | |
parent | 96f15c03532282366364ecfd20f04e49b5d96f3a (diff) |
RDMA/cxgb3: Fixes for zero STag
Handling the zero STag in receive work request requires some extra
logic in the driver:
- Only set the QP_PRIV bit for kernel mode QPs.
- Add a zero STag build function for recv wrs. The uP needs a PBL
allocated and passed down in the recv WR so it can construct a HW
PBL for the zero STag S/G entries. Note: we need to place a few
restrictions on zero STag usage because of this:
1) all SGEs in a recv WR must either be zero STag or not. No mixing.
2) an individual SGE length cannot exceed 128MB for a zero-stag SGE.
This should be OK since it's not really practical to allocate
such a large chunk of pinned contiguous DMA mapped memory.
- Add an optimized non-zero-STag recv wr format for kernel users.
This is needed to optimize both zero and non-zero STag cracking in
the recv path for kernel users.
- Remove the iwch_ prefix from the static build functions.
- Bump required FW version.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb3/cxio_wr.h')
-rw-r--r-- | drivers/infiniband/hw/cxgb3/cxio_wr.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/infiniband/hw/cxgb3/cxio_wr.h b/drivers/infiniband/hw/cxgb3/cxio_wr.h index de760e9f1cc6..04618f7bfbb3 100644 --- a/drivers/infiniband/hw/cxgb3/cxio_wr.h +++ b/drivers/infiniband/hw/cxgb3/cxio_wr.h | |||
@@ -39,6 +39,9 @@ | |||
39 | 39 | ||
40 | #define T3_MAX_SGE 4 | 40 | #define T3_MAX_SGE 4 |
41 | #define T3_MAX_INLINE 64 | 41 | #define T3_MAX_INLINE 64 |
42 | #define T3_STAG0_PBL_SIZE (2 * T3_MAX_SGE << 3) | ||
43 | #define T3_STAG0_MAX_PBE_LEN (128 * 1024 * 1024) | ||
44 | #define T3_STAG0_PAGE_SHIFT 15 | ||
42 | 45 | ||
43 | #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) | 46 | #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) |
44 | #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ | 47 | #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ |
@@ -665,6 +668,11 @@ struct t3_swsq { | |||
665 | int signaled; | 668 | int signaled; |
666 | }; | 669 | }; |
667 | 670 | ||
671 | struct t3_swrq { | ||
672 | __u64 wr_id; | ||
673 | __u32 pbl_addr; | ||
674 | }; | ||
675 | |||
668 | /* | 676 | /* |
669 | * A T3 WQ implements both the SQ and RQ. | 677 | * A T3 WQ implements both the SQ and RQ. |
670 | */ | 678 | */ |
@@ -681,14 +689,15 @@ struct t3_wq { | |||
681 | u32 sq_wptr; /* sq_wptr - sq_rptr == count of */ | 689 | u32 sq_wptr; /* sq_wptr - sq_rptr == count of */ |
682 | u32 sq_rptr; /* pending wrs */ | 690 | u32 sq_rptr; /* pending wrs */ |
683 | u32 sq_size_log2; /* sq size */ | 691 | u32 sq_size_log2; /* sq size */ |
684 | u64 *rq; /* SW RQ (holds consumer wr_ids */ | 692 | struct t3_swrq *rq; /* SW RQ (holds consumer wr_ids */ |
685 | u32 rq_wptr; /* rq_wptr - rq_rptr == count of */ | 693 | u32 rq_wptr; /* rq_wptr - rq_rptr == count of */ |
686 | u32 rq_rptr; /* pending wrs */ | 694 | u32 rq_rptr; /* pending wrs */ |
687 | u64 *rq_oldest_wr; /* oldest wr on the SW RQ */ | 695 | struct t3_swrq *rq_oldest_wr; /* oldest wr on the SW RQ */ |
688 | u32 rq_size_log2; /* rq size */ | 696 | u32 rq_size_log2; /* rq size */ |
689 | u32 rq_addr; /* rq adapter address */ | 697 | u32 rq_addr; /* rq adapter address */ |
690 | void __iomem *doorbell; /* kernel db */ | 698 | void __iomem *doorbell; /* kernel db */ |
691 | u64 udb; /* user db if any */ | 699 | u64 udb; /* user db if any */ |
700 | struct cxio_rdev *rdev; | ||
692 | }; | 701 | }; |
693 | 702 | ||
694 | struct t3_cq { | 703 | struct t3_cq { |